CN104883253B - A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees - Google Patents
A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees Download PDFInfo
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- CN104883253B CN104883253B CN201510279463.0A CN201510279463A CN104883253B CN 104883253 B CN104883253 B CN 104883253B CN 201510279463 A CN201510279463 A CN 201510279463A CN 104883253 B CN104883253 B CN 104883253B
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Abstract
The invention provides a kind of Lorenz type hyperchaotic system structure circuit that ultimate boundary is estimated of being convenient to of different variablees, utilize operational amplifier U1, operational amplifier U2 and resistance, electric capacity is realized addition and integral operation, utilize operational amplifier U3 and resistance to realize anti-phase computing, multiplier U4 and multiplier U5 realize the multiplying in system, described operational amplifier U1 concatenation operation amplifier U2, operational amplifier U3 and multiplier U5, described operational amplifier U2 concatenation operation amplifier U3 and multiplier U4, described operational amplifier U1, U2 and U3 adopt LF347BN, described multiplier U4 and U5 adopt AD633JN, the present invention is on the basis of Lorenz type chaos system, design a kind of Lorenz type hyperchaotic system construction method and circuits built method of being convenient to ultimate boundary estimation of different variablees and design an analog circuit and realize this chaos system, for the synchronous and control of chaos provides new hyperchaotic system signal source.
Description
Technical field
The present invention relates to a kind of chaos system and circuit, particularly a kind of Lorenz that is beneficial to ultimate boundary estimation of different variableesType hyperchaotic system circuit.
Background technology
Estimate to have great importance in the control of chaos, the engineering application aspect such as synchronous in the border of hyperchaotic system, current,The method of constructing four-dimensional hyperchaos is mainly on the basis of three-dimensional chaotic system, increases one dimension and forms four-dimensional hyperchaotic system, butThe hyperchaotic system forming is not easy to carry out ultimate boundary estimation, can carry out that the hyperchaotic system of ultimate boundary estimation hasFeature is: the characteristic element of Jacobian matrix leading diagonal is all negative value, and the hyperchaotic system of the present invention's structure has JacobiThe characteristic element of matrix leading diagonal is all the feature of negative value, can carry out ultimate boundary estimation, this control for hyperchaos,Synchronous grade has important job applications prospect.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of Lorenz type hyperchaos that ultimate boundary is estimated that is beneficial to of different variableesCircuit system:
1. a Lorenz type hyperchaotic system construction method that is beneficial to ultimate boundary estimation for different variablees, is characterized in that, comprisesFollowing steps:
(1) Lorenz type chaos system i is:
X in formula, y, z is state variable, a, b, c, d is systematic parameter;
(2) build a variable w who reforms1：
dw1/dt＝-kx-rw1k＝5,r＝0.1ii
W in formula1For state variable, k, r is systematic parameter;
(3) build a variable w who reforms2：
dw2/dt＝-ky-rw2k＝5,r＝0.1iii
W in formula2For state variable, k, r is systematic parameter;
(4) ii and iii composition one dimension are switched variable w by choice function iv of structure:
dw/dt＝kf(x)-rwk＝5,r＝0.1v
In formula, w is state variable, and f (x) is switching function, k, and r is systematic parameter;
(5) using variable w as unidimensional system variable, be added on the second equation of Lorenz type chaos system i, obtain one and be beneficial to endThe Lorenz type hyperchaotic system vi that utmost point border is estimated is:
X in formula, y, z, w is state variable, f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;(6) circuit based on system vi structure, utilizes operational amplifier U1, operational amplifier U2 and resistance, electric capacity to realize additionAnd integral operation, utilize operational amplifier U3 and resistance to realize anti-phase computing, multiplier U4 and multiplier U5 realize in systemMultiplying, operational amplifier U6 and selector U7 realize switching function computing, described operational amplifier U1, U2, U3Adopt LF347BN with U6, described multiplier U4 and U5 adopt AD633JN, and described selector U7 adopts ADG409;
Described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operation amplifierDevice U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, and described operational amplifier U3 concatenation operation is amplifiedDevice U1, operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, described multiplier U4 concatenation operationAmplifier U1, described multiplier U5 concatenation operation amplifier U2; Described operational amplifier U6 connects selector U7, described inSelector U7 concatenation operation amplifier U2;
The 1st pin of described operational amplifier U1 joins by resistance R 2 and the 6th pin of operational amplifier U1, and computing is putThe 2nd pin of large device U1 joins by the 1st pin of resistance R y and operational amplifier U1, the 3rd of operational amplifier U1Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is putThe 11st pin of large device U1 meets VEE, and the 6th pin of operational amplifier U1 is by capacitor C y and operational amplifier U1The 7th pin joins, and the 7th pin of operational amplifier U1 is the 13rd pin phase with operational amplifier U1 by resistance R x2Connect, the 7th pin of operational amplifier U1 and the 1st pin of multiplier U5 join, and the 7th pin of operational amplifier U1 is logicalCross resistance R 7 and join with the 6th pin of operational amplifier U3, the 7th pin of operational amplifier U1 meets output y, and computing is putThe 8th pin of large device U1 joins by the 9th pin of capacitor C x and operational amplifier U1, the 8th of operational amplifier U1Pin joins by the 2nd pin of resistance R y1 and operational amplifier U1, and the 8th pin of operational amplifier U1 passes through resistanceThe 2nd pin of R5 and operational amplifier U3 joins, the 8th pin of operational amplifier U1 and the 3rd pin of multiplier U5Join, the 8th pin of operational amplifier U1 and the 2nd pin of operational amplifier U6 join, the 8th of operational amplifier U1Pin meets output x, and the 13rd pin of operational amplifier U1 is the 14th pin phase with operational amplifier U1 by resistance R xConnect, the 14th pin of operational amplifier U1 joins by resistance R 1 and the 9th pin of operational amplifier U1;
The 1st pin of described operational amplifier U2 joins by resistance R 4 and the 6th pin of operational amplifier U2, and computing is putThe 2nd pin of large device U2 joins by the 1st pin of resistance R w and operational amplifier U2, the 3rd of operational amplifier U2Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, computingThe 6th pin of amplifier U2 joins by the 7th pin of capacitor C w and operational amplifier U2, of operational amplifier U27 pins join by the 2nd pin of resistance R y4 and operational amplifier U1, and the 7th pin of operational amplifier U2 passes through resistanceThe 13rd pin of R11 and operational amplifier U3 joins, and the 7th pin of operational amplifier U2 connects output w, operational amplifierThe 8th pin of U2 joins by the 9th pin of capacitor C z and operational amplifier U2, the 8th pin of operational amplifier U2Join with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R 9 and operational amplifier U3'sThe 9th pin joins, and the 8th pin of operational amplifier U2 meets output z, and the 13rd pin of operational amplifier U2 passes through resistanceThe 14th pin of Rz and operational amplifier U2 joins, and the 14th pin of operational amplifier U2 is put by resistance R 3 and computingThe 9th pin of large device U2 joins;
The 1st pin of described operational amplifier U3 joins by the 13rd pin of resistance R x1 and operational amplifier U1, computingThe 1st pin of amplifier U3 and the 4th pin of selector U7 join, the 1st pin and the multiplier of operational amplifier U3The 1st pin of U4 joins, and the 2nd pin of operational amplifier U3 is the 1st pin with operational amplifier U3 by resistance R 6Join, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin connectsVCC, the 11st pin meets VEE, and the 6th pin of operational amplifier U3 is by resistance R 8 and the 7th of operational amplifier U3Pin joins, and the 7th pin of operational amplifier U3 joins by the 2nd pin of resistance R y2 and operational amplifier U1, fortuneCalculate the 7th pin of amplifier U3 and the 5th pin of selector U7 and join, the 8th pin of operational amplifier U3 passes through resistanceThe 9th pin of R10 and operational amplifier U3 joins, and the 8th pin of operational amplifier U3 is put by resistance R z2 and computingThe 13rd pin of large device U2 joins, and the 13rd pin of operational amplifier U3 is by the of resistance R 12 and operational amplifier U314 pins join, and the 14th pin of operational amplifier U3 joins by the 2nd pin of resistance R w2 and operational amplifier U2;
The 2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinThe 2nd pin that meets operational amplifier U1 by resistance R y3, the 8th pin meets VCC;
The 2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinConnect operational amplifier U2 the 13rd pin by resistance R z1, the 8th pin meets VCC;
The 1st pin of described operational amplifier U6 joins by resistance R 13 and the 1st pin of selector U7, operation amplifierThe 1st pin of device U6 joins with ground by resistance R 13 and resistance R 14, and the 3rd pin, the 5th of operational amplifier U6 drawsPin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U66 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.
The 2nd pin of described selector U7 and the 14th pin rank VCC, the 3rd pin of selector U7 meets VEE, selectorThe 15th pin of U7 and the 16th pin ground connection, the 8th pin of selector U7 is by resistance R w1 and operational amplifier U2The 2nd pin joins, the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin,12 pins, the 13rd pin are unsettled.
2. a Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation for different variablees, is characterized in that, utilizes computingAmplifier U1, operational amplifier U2 and resistance, electric capacity are realized addition and integral operation, utilize operational amplifier U3 and resistanceRealize anti-phase computing, multiplier U4 and multiplier U5 realize the multiplying in system, operational amplifier U6 and selectorU7 realizes switching function computing, operational amplifier U1 concatenation operation amplifier U3 and U6, and operational amplifier U1 connects multiplicationDevice U4 and U5 and selector U7, described operational amplifier U1, U2, U3 and U6 adopt LF347BN, described multiplierU4 and U5 adopt AD633JN, and described selector U7 adopts ADG409;
Described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operation amplifierDevice U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, and described operational amplifier U3 concatenation operation is amplifiedDevice U1, operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, described multiplier U4 concatenation operationAmplifier U1, described multiplier U5 concatenation operation amplifier U2; Described operational amplifier U6 connects selector U7, described inSelector U7 concatenation operation amplifier U2;
The 1st pin of described operational amplifier U1 joins by resistance R 2 and the 6th pin of operational amplifier U1, and computing is putThe 2nd pin of large device U1 joins by the 1st pin of resistance R y and operational amplifier U1, the 3rd of operational amplifier U1Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is putThe 11st pin of large device U1 meets VEE, and the 6th pin of operational amplifier U1 is by capacitor C y and operational amplifier U1The 7th pin joins, and the 7th pin of operational amplifier U1 is the 13rd pin phase with operational amplifier U1 by resistance R x2Connect, the 7th pin of operational amplifier U1 and the 1st pin of multiplier U5 join, and the 7th pin of operational amplifier U1 is logicalCross resistance R 7 and join with the 6th pin of operational amplifier U3, the 7th pin of operational amplifier U1 meets output y, and computing is putThe 8th pin of large device U1 joins by the 9th pin of capacitor C x and operational amplifier U1, the 8th of operational amplifier U1Pin joins by the 2nd pin of resistance R y1 and operational amplifier U1, and the 8th pin of operational amplifier U1 passes through resistanceThe 2nd pin of R5 and operational amplifier U3 joins, the 8th pin of operational amplifier U1 and the 3rd pin of multiplier U5Join, the 8th pin of operational amplifier U1 and the 2nd pin of operational amplifier U6 join, the 8th of operational amplifier U1Pin meets output x, and the 13rd pin of operational amplifier U1 is the 14th pin phase with operational amplifier U1 by resistance R xConnect, the 14th pin of operational amplifier U1 joins by resistance R 1 and the 9th pin of operational amplifier U1;
The 1st pin of described operational amplifier U2 joins by resistance R 4 and the 6th pin of operational amplifier U2, and computing is putThe 2nd pin of large device U2 joins by the 1st pin of resistance R w and operational amplifier U2, the 3rd of operational amplifier U2Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, computingThe 6th pin of amplifier U2 joins by the 7th pin of capacitor C w and operational amplifier U2, of operational amplifier U27 pins join by the 2nd pin of resistance R y4 and operational amplifier U1, and the 7th pin of operational amplifier U2 passes through resistanceThe 13rd pin of R11 and operational amplifier U3 joins, and the 7th pin of operational amplifier U2 connects output w, operational amplifierThe 8th pin of U2 joins by the 9th pin of capacitor C z and operational amplifier U2, the 8th pin of operational amplifier U2Join with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R 9 and operational amplifier U3'sThe 9th pin joins, and the 8th pin of operational amplifier U2 meets output z, and the 13rd pin of operational amplifier U2 passes through resistanceThe 14th pin of Rz and operational amplifier U2 joins, and the 14th pin of operational amplifier U2 is put by resistance R 3 and computingThe 9th pin of large device U2 joins;
The 1st pin of described operational amplifier U3 joins by the 13rd pin of resistance R x1 and operational amplifier U1, computingThe 1st pin of amplifier U3 and the 4th pin of selector U7 join, the 1st pin and the multiplier of operational amplifier U3The 1st pin of U4 joins, and the 2nd pin of operational amplifier U3 is the 1st pin with operational amplifier U3 by resistance R 6Join, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin connectsVCC, the 11st pin meets VEE, and the 6th pin of operational amplifier U3 is by resistance R 8 and the 7th of operational amplifier U3Pin joins, and the 7th pin of operational amplifier U3 joins by the 2nd pin of resistance R y2 and operational amplifier U1, fortuneCalculate the 7th pin of amplifier U3 and the 5th pin of selector U7 and join, the 8th pin of operational amplifier U3 passes through resistanceThe 9th pin of R10 and operational amplifier U3 joins, and the 8th pin of operational amplifier U3 is put by resistance R z2 and computingThe 13rd pin of large device U2 joins, and the 13rd pin of operational amplifier U3 is by the of resistance R 12 and operational amplifier U314 pins join, and the 14th pin of operational amplifier U3 joins by the 2nd pin of resistance R w2 and operational amplifier U2;
The 2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinThe 2nd pin that meets operational amplifier U1 by resistance R y3, the 8th pin meets VCC;
The 2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinConnect operational amplifier U2 the 13rd pin by resistance R z1, the 8th pin meets VCC;
The 1st pin of described operational amplifier U6 joins by resistance R 13 and the 1st pin of selector U7, operation amplifierThe 1st pin of device U6 joins with ground by resistance R 13 and resistance R 14, and the 3rd pin, the 5th of operational amplifier U6 drawsPin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U66 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.
The 2nd pin of described selector U7 and the 14th pin rank VCC, the 3rd pin of selector U7 meets VEE, selector U7The 15th pin and the 16th pin ground connection, the 8th pin of selector U7 is by the of resistance R w1 and operational amplifier U22 pins join, the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12ndPin, the 13rd pin are unsettled.
Beneficial effect: the present invention, on the basis of Lorenz type chaos system, has designed being beneficial to of a kind of different variablees ultimateThe Lorenz type hyperchaotic system construction method that border is estimated also designs an analog circuit and realizes this chaos system, for mixedIgnorant synchronous and control provides new hyperchaotic system signal source.
Brief description of the drawings
Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.
Fig. 2 is the actual connection layout of circuit of multiplier U4 and operational amplifier U1.
Fig. 3 is the actual connection layout of the circuit of operational amplifier U3.
Fig. 4 is the actual connection layout of circuit of multiplier U5 and operational amplifier U2.
Fig. 5 is the actual connection layout of circuit of selector U7 and operational amplifier U6.
Detailed description of the invention
Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, referring to Fig. 1-Fig. 5.
1. a Lorenz type hyperchaotic system construction method that is beneficial to ultimate boundary estimation for different variablees, is characterized in that, comprisesFollowing steps:
(1) Lorenz type chaos system i is:
X in formula, y, z is state variable, a, b, c, d is systematic parameter;
(2) build a variable w who reforms1：
dw1/dt＝-kx-rw1k＝5,r＝0.1ii
W in formula1For state variable, k, r is systematic parameter;
(3) build a variable w who reforms2：
dw2/dt＝-ky-rw2k＝5,r＝0.1iii
W in formula2For state variable, k, r is systematic parameter;
(4) ii and iii composition one dimension are switched variable w by choice function iv of structure:
dw/dt＝kf(x)-rwk＝5,r＝0.1v
In formula, w is state variable, and f (x) is switching function, k, and r is systematic parameter;
(5) using variable w as unidimensional system variable, be added on the second equation of Lorenz type chaos system i, obtain one and be beneficial to endThe Lorenz type hyperchaotic system vi that utmost point border is estimated is:
X in formula, y, z, w is state variable, f (x) is switching function, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;(6) circuit based on system vi structure, utilizes operational amplifier U1, operational amplifier U2 and resistance, electric capacity to realize additionAnd integral operation, utilize operational amplifier U3 and resistance to realize anti-phase computing, multiplier U4 and multiplier U5 realize in systemMultiplying, operational amplifier U6 and selector U7 realize switching function computing, described operational amplifier U1, U2, U3Adopt LF347BN with U6, described multiplier U4 and U5 adopt AD633JN, and described selector U7 adopts ADG409;
Described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operation amplifierDevice U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, and described operational amplifier U3 concatenation operation is amplifiedDevice U1, operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, described multiplier U4 concatenation operationAmplifier U1, described multiplier U5 concatenation operation amplifier U2; Described operational amplifier U6 connects selector U7, described inSelector U7 concatenation operation amplifier U2;
The 1st pin of described operational amplifier U1 joins by resistance R 2 and the 6th pin of operational amplifier U1, and computing is putThe 2nd pin of large device U1 joins by the 1st pin of resistance R y and operational amplifier U1, the 3rd of operational amplifier U1Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is putThe 11st pin of large device U1 meets VEE, and the 6th pin of operational amplifier U1 is by capacitor C y and operational amplifier U1The 7th pin joins, and the 7th pin of operational amplifier U1 is the 13rd pin phase with operational amplifier U1 by resistance R x2Connect, the 7th pin of operational amplifier U1 and the 1st pin of multiplier U5 join, and the 7th pin of operational amplifier U1 is logicalCross resistance R 7 and join with the 6th pin of operational amplifier U3, the 7th pin of operational amplifier U1 meets output y, and computing is putThe 8th pin of large device U1 joins by the 9th pin of capacitor C x and operational amplifier U1, the 8th of operational amplifier U1Pin joins by the 2nd pin of resistance R y1 and operational amplifier U1, and the 8th pin of operational amplifier U1 passes through resistanceThe 2nd pin of R5 and operational amplifier U3 joins, the 8th pin of operational amplifier U1 and the 3rd pin of multiplier U5Join, the 8th pin of operational amplifier U1 and the 2nd pin of operational amplifier U6 join, the 8th of operational amplifier U1Pin meets output x, and the 13rd pin of operational amplifier U1 is the 14th pin phase with operational amplifier U1 by resistance R xConnect, the 14th pin of operational amplifier U1 joins by resistance R 1 and the 9th pin of operational amplifier U1;
The 1st pin of described operational amplifier U2 joins by resistance R 4 and the 6th pin of operational amplifier U2, and computing is putThe 2nd pin of large device U2 joins by the 1st pin of resistance R w and operational amplifier U2, the 3rd of operational amplifier U2Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, computingThe 6th pin of amplifier U2 joins by the 7th pin of capacitor C w and operational amplifier U2, of operational amplifier U27 pins join by the 2nd pin of resistance R y4 and operational amplifier U1, and the 7th pin of operational amplifier U2 passes through resistanceThe 13rd pin of R11 and operational amplifier U3 joins, and the 7th pin of operational amplifier U2 connects output w, operational amplifierThe 8th pin of U2 joins by the 9th pin of capacitor C z and operational amplifier U2, the 8th pin of operational amplifier U2Join with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R 9 and operational amplifier U3'sThe 9th pin joins, and the 8th pin of operational amplifier U2 meets output z, and the 13rd pin of operational amplifier U2 passes through resistanceThe 14th pin of Rz and operational amplifier U2 joins, and the 14th pin of operational amplifier U2 is put by resistance R 3 and computingThe 9th pin of large device U2 joins;
The 1st pin of described operational amplifier U3 joins by the 13rd pin of resistance R x1 and operational amplifier U1, computingThe 1st pin of amplifier U3 and the 4th pin of selector U7 join, the 1st pin and the multiplier of operational amplifier U3The 1st pin of U4 joins, and the 2nd pin of operational amplifier U3 is the 1st pin with operational amplifier U3 by resistance R 6Join, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin connectsVCC, the 11st pin meets VEE, and the 6th pin of operational amplifier U3 is by resistance R 8 and the 7th of operational amplifier U3Pin joins, and the 7th pin of operational amplifier U3 joins by the 2nd pin of resistance R y2 and operational amplifier U1, fortuneCalculate the 7th pin of amplifier U3 and the 5th pin of selector U7 and join, the 8th pin of operational amplifier U3 passes through resistanceThe 9th pin of R10 and operational amplifier U3 joins, and the 8th pin of operational amplifier U3 is put by resistance R z2 and computingThe 13rd pin of large device U2 joins, and the 13rd pin of operational amplifier U3 is by the of resistance R 12 and operational amplifier U314 pins join, and the 14th pin of operational amplifier U3 joins by the 2nd pin of resistance R w2 and operational amplifier U2;
The 2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinThe 2nd pin that meets operational amplifier U1 by resistance R y3, the 8th pin meets VCC;
The 2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinConnect operational amplifier U2 the 13rd pin by resistance R z1, the 8th pin meets VCC;
The 1st pin of described operational amplifier U6 joins by resistance R 13 and the 1st pin of selector U7, operation amplifierThe 1st pin of device U6 joins with ground by resistance R 13 and resistance R 14, and the 3rd pin, the 5th of operational amplifier U6 drawsPin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U66 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.
The 2nd pin of described selector U7 and the 14th pin rank VCC, the 3rd pin of selector U7 meets VEE, selectorThe 15th pin of U7 and the 16th pin ground connection, the 8th pin of selector U7 is by resistance R w1 and operational amplifier U2The 2nd pin joins, the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin,12 pins, the 13rd pin are unsettled.
2. a Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation for different variablees, is characterized in that, utilizes computingAmplifier U1, operational amplifier U2 and resistance, electric capacity are realized addition and integral operation, utilize operational amplifier U3 and resistanceRealize anti-phase computing, multiplier U4 and multiplier U5 realize the multiplying in system, operational amplifier U6 and selectorU7 realizes switching function computing, operational amplifier U1 concatenation operation amplifier U3 and U6, and operational amplifier U1 connects multiplicationDevice U4 and U5 and selector U7, described operational amplifier U1, U2, U3 and U6 adopt LF347BN, described multiplierU4 and U5 adopt AD633JN, and described selector U7 adopts ADG409;
Described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operation amplifierDevice U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, and described operational amplifier U3 concatenation operation is amplifiedDevice U1, operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, described multiplier U4 concatenation operationAmplifier U1, described multiplier U5 concatenation operation amplifier U2; Described operational amplifier U6 connects selector U7, described inSelector U7 concatenation operation amplifier U2;
The 1st pin of described operational amplifier U1 joins by resistance R 2 and the 6th pin of operational amplifier U1, and computing is putThe 2nd pin of large device U1 joins by the 1st pin of resistance R y and operational amplifier U1, the 3rd of operational amplifier U1Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is putThe 11st pin of large device U1 meets VEE, and the 6th pin of operational amplifier U1 is by capacitor C y and operational amplifier U1The 7th pin joins, and the 7th pin of operational amplifier U1 is the 13rd pin phase with operational amplifier U1 by resistance R x2Connect, the 7th pin of operational amplifier U1 and the 1st pin of multiplier U5 join, and the 7th pin of operational amplifier U1 is logicalCross resistance R 7 and join with the 6th pin of operational amplifier U3, the 7th pin of operational amplifier U1 meets output y, and computing is putThe 8th pin of large device U1 joins by the 9th pin of capacitor C x and operational amplifier U1, the 8th of operational amplifier U1Pin joins by the 2nd pin of resistance R y1 and operational amplifier U1, and the 8th pin of operational amplifier U1 passes through resistanceThe 2nd pin of R5 and operational amplifier U3 joins, the 8th pin of operational amplifier U1 and the 3rd pin of multiplier U5Join, the 8th pin of operational amplifier U1 and the 2nd pin of operational amplifier U6 join, the 8th of operational amplifier U1Pin meets output x, and the 13rd pin of operational amplifier U1 is the 14th pin phase with operational amplifier U1 by resistance R xConnect, the 14th pin of operational amplifier U1 joins by resistance R 1 and the 9th pin of operational amplifier U1;
The 1st pin of described operational amplifier U2 joins by resistance R 4 and the 6th pin of operational amplifier U2, and computing is putThe 2nd pin of large device U2 joins by the 1st pin of resistance R w and operational amplifier U2, the 3rd of operational amplifier U2Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, computingThe 6th pin of amplifier U2 joins by the 7th pin of capacitor C w and operational amplifier U2, of operational amplifier U27 pins join by the 2nd pin of resistance R y4 and operational amplifier U1, and the 7th pin of operational amplifier U2 passes through resistanceThe 13rd pin of R11 and operational amplifier U3 joins, and the 7th pin of operational amplifier U2 connects output w, operational amplifierThe 8th pin of U2 joins by the 9th pin of capacitor C z and operational amplifier U2, the 8th pin of operational amplifier U2Join with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R 9 and operational amplifier U3'sThe 9th pin joins, and the 8th pin of operational amplifier U2 meets output z, and the 13rd pin of operational amplifier U2 passes through resistanceThe 14th pin of Rz and operational amplifier U2 joins, and the 14th pin of operational amplifier U2 is put by resistance R 3 and computingThe 9th pin of large device U2 joins;
The 1st pin of described operational amplifier U3 joins by the 13rd pin of resistance R x1 and operational amplifier U1, computingThe 1st pin of amplifier U3 and the 4th pin of selector U7 join, the 1st pin and the multiplier of operational amplifier U3The 1st pin of U4 joins, and the 2nd pin of operational amplifier U3 is the 1st pin with operational amplifier U3 by resistance R 6Join, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin connectsVCC, the 11st pin meets VEE, and the 6th pin of operational amplifier U3 is by resistance R 8 and the 7th of operational amplifier U3Pin joins, and the 7th pin of operational amplifier U3 joins by the 2nd pin of resistance R y2 and operational amplifier U1, fortuneCalculate the 7th pin of amplifier U3 and the 5th pin of selector U7 and join, the 8th pin of operational amplifier U3 passes through resistanceThe 9th pin of R10 and operational amplifier U3 joins, and the 8th pin of operational amplifier U3 is put by resistance R z2 and computingThe 13rd pin of large device U2 joins, and the 13rd pin of operational amplifier U3 is by the of resistance R 12 and operational amplifier U314 pins join, and the 14th pin of operational amplifier U3 joins by the 2nd pin of resistance R w2 and operational amplifier U2;
The 2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinThe 2nd pin that meets operational amplifier U1 by resistance R y3, the 8th pin meets VCC;
The 2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinConnect operational amplifier U2 the 13rd pin by resistance R z1, the 8th pin meets VCC;
The 1st pin of described operational amplifier U6 joins by resistance R 13 and the 1st pin of selector U7, operation amplifierThe 1st pin of device U6 joins with ground by resistance R 13 and resistance R 14, and the 3rd pin, the 5th of operational amplifier U6 drawsPin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U66 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled.
The 2nd pin of described selector U7 and the 14th pin rank VCC, the 3rd pin of selector U7 meets VEE, selector U7The 15th pin and the 16th pin ground connection, the 8th pin of selector U7 is by the of resistance R w1 and operational amplifier U22 pins join, the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12ndPin, the 13rd pin are unsettled.
Certainly, above-mentioned explanation is the restriction to invention not, and the present invention is also not limited only to above-mentioned giving an example, the common skill of the artVariation, remodeling, interpolation or replacement that art personnel make in essential scope of the present invention, also belong to protection scope of the present invention.
Claims (1)
1. a Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation for different variablees, is characterized in that, utilizes computingAmplifier U1, operational amplifier U2 and resistance, electric capacity are realized addition and integral operation, utilize operational amplifier U3 and resistanceRealize anti-phase computing, multiplier U4 and multiplier U5 realize the multiplying in system, operational amplifier U6 and selectorU7 realizes switching function computing, operational amplifier U1 concatenation operation amplifier U3 and U6, and operational amplifier U1 connects multiplicationDevice U4 and U5 and selector U7, described operational amplifier U1, U2, U3 and U6 adopt LF347BN, described multiplierU4 and U5 adopt AD633JN, and described selector U7 adopts ADG409;
Described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, described operation amplifierDevice U2 connects multiplier U4, operational amplifier U1 and operational amplifier U3, and described operational amplifier U3 concatenation operation is amplifiedDevice U1, operational amplifier U2, operational amplifier U6, selector U7 and multiplier U4, described multiplier U4 concatenation operationAmplifier U1, described multiplier U5 concatenation operation amplifier U2; Described operational amplifier U6 connects selector U7, described inSelector U7 concatenation operation amplifier U2;
The 1st pin of described operational amplifier U1 joins by resistance R 2 and the 6th pin of operational amplifier U1, and computing is putThe 2nd pin of large device U1 joins by the 1st pin of resistance R y and operational amplifier U1, the 3rd of operational amplifier U1Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is putThe 11st pin of large device U1 meets VEE, and the 6th pin of operational amplifier U1 is by capacitor C y and operational amplifier U1The 7th pin joins, and the 7th pin of operational amplifier U1 is the 13rd pin phase with operational amplifier U1 by resistance R x2Connect, the 7th pin of operational amplifier U1 and the 1st pin of multiplier U5 join, and the 7th pin of operational amplifier U1 is logicalCross resistance R 7 and join with the 6th pin of operational amplifier U3, the 7th pin of operational amplifier U1 meets output y, and computing is putThe 8th pin of large device U1 joins by the 9th pin of capacitor C x and operational amplifier U1, the 8th of operational amplifier U1Pin joins by the 2nd pin of resistance R y1 and operational amplifier U1, and the 8th pin of operational amplifier U1 passes through resistanceThe 2nd pin of R5 and operational amplifier U3 joins, the 8th pin of operational amplifier U1 and the 3rd pin of multiplier U5Join, the 8th pin of operational amplifier U1 and the 2nd pin of operational amplifier U6 join, the 8th of operational amplifier U1Pin meets output x, and the 13rd pin of operational amplifier U1 is the 14th pin phase with operational amplifier U1 by resistance R xConnect, the 14th pin of operational amplifier U1 joins by resistance R 1 and the 9th pin of operational amplifier U1;
The 1st pin of described operational amplifier U2 joins by resistance R 4 and the 6th pin of operational amplifier U2, and computing is putThe 2nd pin of large device U2 joins by the 1st pin of resistance R w and operational amplifier U2, the 3rd of operational amplifier U2Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, computingThe 6th pin of amplifier U2 joins by the 7th pin of capacitor C w and operational amplifier U2, of operational amplifier U27 pins join by the 2nd pin of resistance R y4 and operational amplifier U1, and the 7th pin of operational amplifier U2 passes through resistanceThe 13rd pin of R11 and operational amplifier U3 joins, and the 7th pin of operational amplifier U2 connects output w, operational amplifierThe 8th pin of U2 joins by the 9th pin of capacitor C z and operational amplifier U2, the 8th pin of operational amplifier U2Join with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R 9 and operational amplifier U3'sThe 9th pin joins, and the 8th pin of operational amplifier U2 meets output z, and the 13rd pin of operational amplifier U2 passes through resistanceThe 14th pin of Rz and operational amplifier U2 joins, and the 14th pin of operational amplifier U2 is put by resistance R 3 and computingThe 9th pin of large device U2 joins;
The 1st pin of described operational amplifier U3 joins by the 13rd pin of resistance R x1 and operational amplifier U1, computingThe 1st pin of amplifier U3 and the 4th pin of selector U7 join, the 1st pin and the multiplier of operational amplifier U3The 1st pin of U4 joins, and the 2nd pin of operational amplifier U3 is the 1st pin with operational amplifier U3 by resistance R 6Join, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin connectsVCC, the 11st pin meets VEE, and the 6th pin of operational amplifier U3 is by resistance R 8 and the 7th of operational amplifier U3Pin joins, and the 7th pin of operational amplifier U3 joins by the 2nd pin of resistance R y2 and operational amplifier U1, fortuneCalculate the 7th pin of amplifier U3 and the 5th pin of selector U7 and join, the 8th pin of operational amplifier U3 passes through resistanceThe 9th pin of R10 and operational amplifier U3 joins, and the 8th pin of operational amplifier U3 is put by resistance R z2 and computingThe 13rd pin of large device U2 joins, and the 13rd pin of operational amplifier U3 is by the of resistance R 12 and operational amplifier U314 pins join, and the 14th pin of operational amplifier U3 joins by the 2nd pin of resistance R w2 and operational amplifier U2;
The 2nd pin of described multiplier U4, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinThe 2nd pin that meets operational amplifier U1 by resistance R y3, the 8th pin meets VCC;
The 2nd pin of described multiplier U5, the 4th pin, the equal ground connection of the 6th pin, the 5th pin meets VEE, the 7th pinConnect operational amplifier U2 the 13rd pin by resistance R z1, the 8th pin meets VCC;
The 1st pin of described operational amplifier U6 joins by resistance R 13 and the 1st pin of selector U7, operation amplifierThe 1st pin of device U6 joins with ground by resistance R 13 and resistance R 14, and the 3rd pin, the 5th of operational amplifier U6 drawsPin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U66 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
The 2nd pin of described selector U7 and the 14th pin rank VCC, the 3rd pin of selector U7 meets VEE, selector U7The 15th pin and the 16th pin ground connection, the 8th pin of selector U7 is by the of resistance R w1 and operational amplifier U22 pins join, the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12ndPin, the 13rd pin are unsettled.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610118818.2A CN105634725B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable |
| CN201510279463.0A CN104883253B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees |
| PCT/CN2015/000571 WO2016187738A1 (en) | 2015-05-27 | 2015-08-07 | Construction method for hyperchaotic lorenz system of different variables and facilitating ultimate boundary estimation and circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510279463.0A CN104883253B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system circuit that is beneficial to ultimate boundary estimation of different variablees |
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| CN201610118818.2A Division CN105634725B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable |
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| CN104883253B true CN104883253B (en) | 2016-05-11 |
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| CN201610118818.2A Active CN105634725B (en) | 2015-05-27 | 2015-05-27 | A kind of Lorenz type hyperchaotic system construction methods for being conducive to ultimate boundary estimation of difference variable |
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| CN105610572B (en) * | 2015-05-27 | 2018-08-07 | 成都市中电伟业科技有限公司 | A kind of different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation of variable |
| CN105119710A (en) * | 2015-09-09 | 2015-12-02 | 王春梅 | Lorenz type hyper-chaotic system adaptive synchronization method and circuit beneficial to ultimate edge estimation |
| CN105141411A (en) * | 2015-09-09 | 2015-12-09 | 王春梅 | Self-adaptive synchronization method of Lorenz type hyperchaotic system having different variables and circuit |
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| US7020286B2 (en) * | 2001-02-15 | 2006-03-28 | Massachusetts Institute Of Technology | Modulation of dynamical systems for communication |
| KR100353082B1 (en) * | 2001-02-27 | 2002-09-18 | 한국과학기술원 | Random Hyperchaos signal generating circuit using HVSM model |
| CN101373563B (en) * | 2008-08-01 | 2010-06-02 | 张新国 | Lorentz chaos circuit |
| CN102332976B (en) * | 2011-09-15 | 2013-11-06 | 江西理工大学 | Different-dimensional switchable chaotic system design method and circuit |
| CN104202146A (en) * | 2014-09-09 | 2014-12-10 | 王忠林 | Yang-Chen system based automatic switching hyper-chaos system construction method and analog circuit |
| CN104378197B (en) * | 2014-12-03 | 2015-08-19 | 国网山东省电力公司淄博供电公司 | Based on construction method and the circuit of the Lorenz type hyperchaotic system containing x side of memristor |
| CN104468082B (en) * | 2014-12-03 | 2016-10-05 | 国家电网公司 | The construction method of the Lorenz type hyperchaotic system containing y side based on memristor |
| CN104486061A (en) * | 2014-12-03 | 2015-04-01 | 李敏 | Construction method and circuit of classic Lorenz hyper-chaos system based on memristor |
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- 2015-05-27 CN CN201610118818.2A patent/CN105634725B/en active Active
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| CN105634725A (en) | 2016-06-01 |
| CN104883253A (en) | 2015-09-02 |
| WO2016187738A1 (en) | 2016-12-01 |
| CN105634725B (en) | 2018-10-09 |
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