CN104836658B - A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated - Google Patents

A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated Download PDF

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CN104836658B
CN104836658B CN201510279462.6A CN201510279462A CN104836658B CN 104836658 B CN104836658 B CN 104836658B CN 201510279462 A CN201510279462 A CN 201510279462A CN 104836658 B CN104836658 B CN 104836658B
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operational amplifier
resistance
connects
multiplier
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CN104836658A (en
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陈先学
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Suqian Shengda Construction Industry Co ltd
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Chongqing Xuxinyue Nc Machinery Co Ltd
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Priority to PCT/CN2015/000572 priority patent/WO2016187739A1/en
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Abstract

The present invention provides a kind of and feeds back the different Lorenz type hyperchaotic system construction methods being easy to ultimate boundary estimation, operational amplifier U1, operational amplifier U2 and resistance, electric capacity is utilized to realize addition and integral operation, operational amplifier U3 and resistance is utilized to realize anti-phase computing, multiplier U4 and multiplier U5 realizes the multiplying in system, described operational amplifier U1, U2, U3 and U6 use LF347BN, described multiplier U4 and U5 uses AD633JN, and described selector uses ADG409;The present invention is on the basis of Lorenz type chaos system, designing a kind of feedback different are easy to Lorenz type hyperchaos system's construction method that ultimate boundary estimates and circuit construction method and design an analog circuit and carry out realizing this chaos system, synchronization and control for chaos provide new hyperchaotic system signal source.

Description

A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated
Technical field
The present invention relates to a kind of chaos system, different are easy to the Lorenz type that ultimate boundary estimates particularly to a kind of feedback and surpass Chaos system construction method.
Background technology
Estimate to have great importance in terms of the engineer applied such as the control of chaos, synchronization in the border of hyperchaotic system, currently, The method constructing four dimension ultra-chaos is mainly on the basis of three-dimensional chaotic system, increases the four-dimensional hyperchaotic system of one-dimensional composition, but The hyperchaotic system constituted is not easy to carry out ultimate boundary estimation, can carry out what the hyperchaotic system of ultimate boundary estimation had Feature is: all negative values of characteristic element of Jacobian matrix leading diagonal, and the hyperchaotic system of present invention structure has Jacobi The feature of all negative values of characteristic element of matrix leading diagonal, can carry out ultimate boundary estimation, and this is for the control of hyperchaos System, synchronization etc. have important job applications prospect.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of feedback and different is easy to the Lorenz type hyperchaos that ultimate boundary is estimated System constituting method:
1. the Lorenz type hyperchaotic system construction method being easy to ultimate boundary estimation that a feedback is different, it is characterised in that include Following steps:
(1) Lorenz type chaos system i is:
d x / d t = a ( y - x ) d y / d t = b x - x z - c y d z / d t = x y - d z a = 12 , b = 23 , c = 1 , d = 2.1 - - - i
X in formula, y, z are state variable, and a, b, c, d are systematic parameter;
(2) on chaos system i, one-dimensional variable w is increased:
Dw/dt=-ky-rw k=5, r=0.1 ii
In formula, w is state variable, and k, r are systematic parameter;
(3) using variable i i as unidimensional system variable, it is added on first equation of Lorenz type chaos system i, it is thus achieved that one is easy to Lorenz type hyperchaotic system iii that ultimate boundary is estimated is:
d x / d t = a ( y - x ) + w d y / d t = b x - x z - c y d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , = 5 , r = 0.1 - - - i i i
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(4) using variable i i as unidimensional system variable, it is added on second equation of Lorenz type chaos system i, it is thus achieved that one is easy to Lorenz type hyperchaotic system iv that ultimate boundary is estimated is:
d x / d t = a ( y - x ) d y / d t = b x - x z - c y + w d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - i v
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(5) structure one selects function v and vi to switch super mixed by a kind of for iii and iv composition Lorenz type being easy to ultimate boundary estimation Ignorant system vii is:
f ( y ) = 1 y &GreaterEqual; 0 0 y < 0 - - - v
f ( - y ) = 0 y &GreaterEqual; 0 1 y < 0 - - - v i
d x / d t = a ( y - x ) + f ( y ) w d y / d t = b x - x z - c y + f ( - y ) w d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - v i i
X in formula, y, z, w are state variable, and f (x), f (-x) are switching functions, and a, b, c, d, k, r are systematic parameter;
(6) circuit based on system vii structure, utilizes operational amplifier U1, operational amplifier U2 and resistance, electric capacity to realize adding Method and integral operation, utilize operational amplifier U3 and resistance to realize anti-phase computing, multiplier U4 and multiplier U5 and realize system Multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, Described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, institute State multiplier U5 concatenation operation amplifier U2;Described operational amplifier U6 connects selector U7, described selector U7 and connects Operational amplifier U1, described operational amplifier U1, U2, U3 and U6 use LF347BN, described multiplier U4 and U5 Using AD633JN, described selector uses ADG409;
1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R2 and operational amplifier U1, and computing is put 2nd pin of big device U1 is connected by the 1st pin of resistance Ry and operational amplifier U1, the 3rd of operational amplifier U1 Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is put 11st pin of big device U1 connects the 6th pin of VEE, operational amplifier U1 by electric capacity Cy and operational amplifier U1's 7th pin connects, the 7th pin of operational amplifier U1 the 13rd pin phase by resistance Rx2 and operational amplifier U1 Connecing, the 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, the 7th pin of operational amplifier U1 Being connected by the 6th pin of resistance R7 and operational amplifier U3, the 7th pin of operational amplifier U1 connects output y, computing 8th pin of amplifier U1 is connected by the 9th pin of electric capacity Cx and operational amplifier U1, the of operational amplifier U1 8 pins are connected by the 2nd pin of resistance Ry1 and operational amplifier U1, and the 8th pin of operational amplifier U1 is by electricity 2nd pin of resistance R5 and operational amplifier U3 connects, and the 8th pin of operational amplifier U1 draws with the 3rd of multiplier U5 Foot connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operational amplifier U1's 8th pin is connect the 13rd pin of output x, operational amplifier U1 and is drawn with the 14th of operational amplifier U1 by resistance Rx Foot connects, and the 14th pin of operational amplifier U1 is connected by the 9th pin of resistance R1 and operational amplifier U1;
1st pin of described operational amplifier U2 is connected by the 6th pin of resistance R4 and operational amplifier U2, computing 2nd pin of amplifier U2 is connected by the 1st pin of resistance Rw and operational amplifier U2, the of operational amplifier U2 3 pins, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, fortune The 6th pin calculating amplifier U2 is connected by the 7th pin of electric capacity Cw and operational amplifier U2, operational amplifier U2's 7th pin connects with the 4th pin and the 12nd pin of selector U7, and the 7th pin of operational amplifier U2 passes through resistance 13rd pin of R11 and operational amplifier U3 connects, and the 7th pin of operational amplifier U2 connects output w, operational amplifier 8th pin of U2 is connected by the 9th pin of electric capacity Cz and operational amplifier U2, the 8th pin of operational amplifier U2 Connecting with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R9 and operational amplifier U3's 9th pin connects, and the 8th pin of operational amplifier U2 connects the 13rd pin of output z, operational amplifier U2 and passes through resistance 14th pin of Rz and operational amplifier U2 connects, and the 14th pin of operational amplifier U2 is put with computing by resistance R3 9th pin of big device U2 connects;
1st pin of described operational amplifier U3 is connected by the 13rd pin of resistance Rx1 and operational amplifier U1, computing 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance 1st pin of R6 and operational amplifier U3 connects, and the 3rd pin of operational amplifier U3, the 5th pin, the 10th draws Foot, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin connects the 6th pin of VEE, operational amplifier U3 and leads to The 7th pin crossing resistance R8 and operational amplifier U3 connects, the 7th pin of operational amplifier U3 by resistance Ry2 with 2nd pin of operational amplifier U1 connects, and the 7th pin of operational amplifier U3 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 8th pin of operational amplifier U3 is by the 9th pin of resistance R10 and operational amplifier U3 Connecting, the 8th pin of operational amplifier U3 is connected by the 13rd pin of resistance Rz2 and operational amplifier U2, and computing is put 13rd pin of big device U3 is connected by the 14th pin of resistance R12 and operational amplifier U3, operational amplifier U3's 14th pin is connected by the 2nd pin of resistance Rw2 and operational amplifier U2;
2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected by the 1st pin of resistance R13 and selector U7, operation amplifier 1st pin of device U6 by resistance R13 and resistance R14 with connect, the 3rd pin of operational amplifier U6, the 5th draw Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U6 6 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin of described selector U7 and the 14th pin connect the 3rd pin of VCC, selector U7 and meet VEE, select 15th pin of device U7 and the 16th pin ground connection, the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st draws Foot, the 12nd pin, the 13rd pin are unsettled.
2. the Lorenz type hyperchaotic system circuit being easy to ultimate boundary estimation that a feedback is different, it is characterised in that utilize fortune Calculate amplifier U1, operational amplifier U2 and resistance, electric capacity realize addition and integral operation, utilize operational amplifier U3 and electricity Resistance realizes anti-phase computing, multiplier U4 and multiplier U5 and realizes the multiplying in system, and described operational amplifier U1 is even Meeting operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and computing Amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and take advantage of Musical instruments used in a Buddhist or Taoist mass U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2;Described fortune Calculation amplifier U6 connection selector U7, described selector U7 concatenation operation amplifier U1, described operational amplifier U1, U2, U3 and U6 use LF347BN, described multiplier U4 and U5 to use AD633JN, and described selector uses ADG409;
1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R2 and operational amplifier U1, and computing is put 2nd pin of big device U1 is connected by the 1st pin of resistance Ry and operational amplifier U1, the 3rd of operational amplifier U1 Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is put 11st pin of big device U1 connects the 6th pin of VEE, operational amplifier U1 by electric capacity Cy and operational amplifier U1's 7th pin connects, the 7th pin of operational amplifier U1 the 13rd pin phase by resistance Rx2 and operational amplifier U1 Connecing, the 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, the 7th pin of operational amplifier U1 Being connected by the 6th pin of resistance R7 and operational amplifier U3, the 7th pin of operational amplifier U1 connects output y, computing 8th pin of amplifier U1 is connected by the 9th pin of electric capacity Cx and operational amplifier U1, the of operational amplifier U1 8 pins are connected by the 2nd pin of resistance Ry1 and operational amplifier U1, and the 8th pin of operational amplifier U1 is by electricity 2nd pin of resistance R5 and operational amplifier U3 connects, and the 8th pin of operational amplifier U1 draws with the 3rd of multiplier U5 Foot connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operational amplifier U1's 8th pin is connect the 13rd pin of output x, operational amplifier U1 and is drawn with the 14th of operational amplifier U1 by resistance Rx Foot connects, and the 14th pin of operational amplifier U1 is connected by the 9th pin of resistance R1 and operational amplifier U1;
1st pin of described operational amplifier U2 is connected by the 6th pin of resistance R4 and operational amplifier U2, computing 2nd pin of amplifier U2 is connected by the 1st pin of resistance Rw and operational amplifier U2, the of operational amplifier U2 3 pins, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, fortune The 6th pin calculating amplifier U2 is connected by the 7th pin of electric capacity Cw and operational amplifier U2, operational amplifier U2's 7th pin connects with the 4th pin and the 12nd pin of selector U7, and the 7th pin of operational amplifier U2 passes through resistance 13rd pin of R11 and operational amplifier U3 connects, and the 7th pin of operational amplifier U2 connects output w, operational amplifier 8th pin of U2 is connected by the 9th pin of electric capacity Cz and operational amplifier U2, the 8th pin of operational amplifier U2 Connecting with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R9 and operational amplifier U3's 9th pin connects, and the 8th pin of operational amplifier U2 connects the 13rd pin of output z, operational amplifier U2 and passes through resistance 14th pin of Rz and operational amplifier U2 connects, and the 14th pin of operational amplifier U2 is put with computing by resistance R3 9th pin of big device U2 connects;
1st pin of described operational amplifier U3 is connected by the 13rd pin of resistance Rx1 and operational amplifier U1, computing 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance 1st pin of R6 and operational amplifier U3 connects, and the 3rd pin of operational amplifier U3, the 5th pin, the 10th draws Foot, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin connects the 6th pin of VEE, operational amplifier U3 and leads to The 7th pin crossing resistance R8 and operational amplifier U3 connects, the 7th pin of operational amplifier U3 by resistance Ry2 with 2nd pin of operational amplifier U1 connects, and the 7th pin of operational amplifier U3 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 8th pin of operational amplifier U3 is by the 9th pin of resistance R10 and operational amplifier U3 Connecting, the 8th pin of operational amplifier U3 is connected by the 13rd pin of resistance Rz2 and operational amplifier U2, and computing is put 13rd pin of big device U3 is connected by the 14th pin of resistance R12 and operational amplifier U3, operational amplifier U3's 14th pin is connected by the 2nd pin of resistance Rw2 and operational amplifier U2;
2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected by the 1st pin of resistance R13 and selector U7, operation amplifier 1st pin of device U6 by resistance R13 and resistance R14 with connect, the 3rd pin of operational amplifier U6, the 5th draw Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U6 6 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin of described selector U7 and the 14th pin connect the 3rd pin of VCC, selector U7 and meet VEE, select 15th pin of device U7 and the 16th pin ground connection, the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st draws Foot, the 12nd pin, the 13rd pin are unsettled.
Beneficial effect: the present invention, on the basis of Lorenz type chaos system, devises a kind of feedback and different is easy to ultimate limit Lorenz type hyperchaotic system construction method that boundary estimates also designs an analog circuit and carries out realizing this chaos system, for chaos Synchronization and control provide new hyperchaotic system signal source.
Accompanying drawing explanation
Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.
Fig. 2 is the circuit actual connection figure of multiplier U4 and operational amplifier U1.
Fig. 3 is the circuit actual connection figure of operational amplifier U3.
Fig. 4 is the circuit actual connection figure of multiplier U5 and operational amplifier U2.
Fig. 5 is the circuit actual connection figure of selector U7 and operational amplifier U6.
Detailed description of the invention
With preferred embodiment, the present invention is further described in detail below in conjunction with the accompanying drawings, sees Fig. 1-Fig. 5.
1. the Lorenz type hyperchaotic system construction method being easy to ultimate boundary estimation that a feedback is different, it is characterised in that include Following steps:
(1) Lorenz type chaos system i is:
d x / d t = a ( y - x ) d y / d t = b x - x z - c y d z / d t = x y - d z a = 12 , b = 23 , c = 1 , d = 2.1 - - - i
X in formula, y, z are state variable, and a, b, c, d are systematic parameter;
(2) on chaos system i, one-dimensional variable w is increased:
Dw/dt=-ky-rw k=5, r=0.1 ii
In formula, w is state variable, and k, r are systematic parameter;
(3) using variable i i as unidimensional system variable, it is added on first equation of Lorenz type chaos system i, it is thus achieved that one is easy to Lorenz type hyperchaotic system iii that ultimate boundary is estimated is:
d x / d t = a ( y - x ) + w d y / d t = b x - x z - c y d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , = 5 , r = 0.1 - - - i i i
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(4) using variable i i as unidimensional system variable, it is added on second equation of Lorenz type chaos system i, it is thus achieved that one is easy to Lorenz type hyperchaotic system iv that ultimate boundary is estimated is:
d x / d t = a ( y - x ) d y / d t = b x - x z - c y + w d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - i v
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(5) structure one selects function v and vi to switch super mixed by a kind of for iii and iv composition Lorenz type being easy to ultimate boundary estimation Ignorant system vii is:
f ( y ) = 1 y &GreaterEqual; 0 0 y < 0 - - - v
f ( - y ) = 0 y &GreaterEqual; 0 1 y < 0 - - - v i
d x / d t = a ( y - x ) + f ( y ) w d y / d t = b x - x z - c y + f ( - y ) w d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - v i i
X in formula, y, z, w are state variable, and f (x), f (-x) are switching functions, and a, b, c, d, k, r are systematic parameter;
(6) circuit based on system vii structure, utilizes operational amplifier U1, operational amplifier U2 and resistance, electric capacity to realize adding Method and integral operation, utilize operational amplifier U3 and resistance to realize anti-phase computing, multiplier U4 and multiplier U5 and realize system Multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, Described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, institute State multiplier U5 concatenation operation amplifier U2;Described operational amplifier U6 connects selector U7, described selector U7 and connects Operational amplifier U1, described operational amplifier U1, U2, U3 and U6 use LF347BN, described multiplier U4 and U5 Using AD633JN, described selector uses ADG409;
1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R2 and operational amplifier U1, and computing is put 2nd pin of big device U1 is connected by the 1st pin of resistance Ry and operational amplifier U1, the 3rd of operational amplifier U1 Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is put 11st pin of big device U1 connects the 6th pin of VEE, operational amplifier U1 by electric capacity Cy and operational amplifier U1's 7th pin connects, the 7th pin of operational amplifier U1 the 13rd pin phase by resistance Rx2 and operational amplifier U1 Connecing, the 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, the 7th pin of operational amplifier U1 Being connected by the 6th pin of resistance R7 and operational amplifier U3, the 7th pin of operational amplifier U1 connects output y, computing 8th pin of amplifier U1 is connected by the 9th pin of electric capacity Cx and operational amplifier U1, the of operational amplifier U1 8 pins are connected by the 2nd pin of resistance Ry1 and operational amplifier U1, and the 8th pin of operational amplifier U1 is by electricity 2nd pin of resistance R5 and operational amplifier U3 connects, and the 8th pin of operational amplifier U1 draws with the 3rd of multiplier U5 Foot connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operational amplifier U1's 8th pin is connect the 13rd pin of output x, operational amplifier U1 and is drawn with the 14th of operational amplifier U1 by resistance Rx Foot connects, and the 14th pin of operational amplifier U1 is connected by the 9th pin of resistance R1 and operational amplifier U1;
1st pin of described operational amplifier U2 is connected by the 6th pin of resistance R4 and operational amplifier U2, computing 2nd pin of amplifier U2 is connected by the 1st pin of resistance Rw and operational amplifier U2, the of operational amplifier U2 3 pins, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, fortune The 6th pin calculating amplifier U2 is connected by the 7th pin of electric capacity Cw and operational amplifier U2, operational amplifier U2's 7th pin connects with the 4th pin and the 12nd pin of selector U7, and the 7th pin of operational amplifier U2 passes through resistance 13rd pin of R11 and operational amplifier U3 connects, and the 7th pin of operational amplifier U2 connects output w, operational amplifier 8th pin of U2 is connected by the 9th pin of electric capacity Cz and operational amplifier U2, the 8th pin of operational amplifier U2 Connecting with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R9 and operational amplifier U3's 9th pin connects, and the 8th pin of operational amplifier U2 connects the 13rd pin of output z, operational amplifier U2 and passes through resistance 14th pin of Rz and operational amplifier U2 connects, and the 14th pin of operational amplifier U2 is put with computing by resistance R3 9th pin of big device U2 connects;
1st pin of described operational amplifier U3 is connected by the 13rd pin of resistance Rx1 and operational amplifier U1, computing 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance 1st pin of R6 and operational amplifier U3 connects, and the 3rd pin of operational amplifier U3, the 5th pin, the 10th draws Foot, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin connects the 6th pin of VEE, operational amplifier U3 and leads to The 7th pin crossing resistance R8 and operational amplifier U3 connects, the 7th pin of operational amplifier U3 by resistance Ry2 with 2nd pin of operational amplifier U1 connects, and the 7th pin of operational amplifier U3 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 8th pin of operational amplifier U3 is by the 9th pin of resistance R10 and operational amplifier U3 Connecting, the 8th pin of operational amplifier U3 is connected by the 13rd pin of resistance Rz2 and operational amplifier U2, and computing is put 13rd pin of big device U3 is connected by the 14th pin of resistance R12 and operational amplifier U3, operational amplifier U3's 14th pin is connected by the 2nd pin of resistance Rw2 and operational amplifier U2;
2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected by the 1st pin of resistance R13 and selector U7, operation amplifier 1st pin of device U6 by resistance R13 and resistance R14 with connect, the 3rd pin of operational amplifier U6, the 5th draw Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U6 6 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin of described selector U7 and the 14th pin connect the 3rd pin of VCC, selector U7 and meet VEE, select 15th pin of device U7 and the 16th pin ground connection, the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st draws Foot, the 12nd pin, the 13rd pin are unsettled.
2. the Lorenz type hyperchaotic system circuit being easy to ultimate boundary estimation that a feedback is different, it is characterised in that utilize fortune Calculate amplifier U1, operational amplifier U2 and resistance, electric capacity realize addition and integral operation, utilize operational amplifier U3 and electricity Resistance realizes anti-phase computing, multiplier U4 and multiplier U5 and realizes the multiplying in system, and described operational amplifier U1 is even Meeting operational amplifier U3, operational amplifier U6 and multiplier U5, described operational amplifier U2 connects multiplier U4 and computing Amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and take advantage of Musical instruments used in a Buddhist or Taoist mass U4, described multiplier U4 concatenation operation amplifier U1, described multiplier U5 concatenation operation amplifier U2;Described fortune Calculation amplifier U6 connection selector U7, described selector U7 concatenation operation amplifier U1, described operational amplifier U1, U2, U3 and U6 use LF347BN, described multiplier U4 and U5 to use AD633JN, and described selector uses ADG409;
1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R2 and operational amplifier U1, and computing is put 2nd pin of big device U1 is connected by the 1st pin of resistance Ry and operational amplifier U1, the 3rd of operational amplifier U1 Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is put 11st pin of big device U1 connects the 6th pin of VEE, operational amplifier U1 by electric capacity Cy and operational amplifier U1's 7th pin connects, the 7th pin of operational amplifier U1 the 13rd pin phase by resistance Rx2 and operational amplifier U1 Connecing, the 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, the 7th pin of operational amplifier U1 Being connected by the 6th pin of resistance R7 and operational amplifier U3, the 7th pin of operational amplifier U1 connects output y, computing 8th pin of amplifier U1 is connected by the 9th pin of electric capacity Cx and operational amplifier U1, the of operational amplifier U1 8 pins are connected by the 2nd pin of resistance Ry1 and operational amplifier U1, and the 8th pin of operational amplifier U1 is by electricity 2nd pin of resistance R5 and operational amplifier U3 connects, and the 8th pin of operational amplifier U1 draws with the 3rd of multiplier U5 Foot connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operational amplifier U1's 8th pin is connect the 13rd pin of output x, operational amplifier U1 and is drawn with the 14th of operational amplifier U1 by resistance Rx Foot connects, and the 14th pin of operational amplifier U1 is connected by the 9th pin of resistance R1 and operational amplifier U1;
1st pin of described operational amplifier U2 is connected by the 6th pin of resistance R4 and operational amplifier U2, computing 2nd pin of amplifier U2 is connected by the 1st pin of resistance Rw and operational amplifier U2, the of operational amplifier U2 3 pins, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, fortune The 6th pin calculating amplifier U2 is connected by the 7th pin of electric capacity Cw and operational amplifier U2, operational amplifier U2's 7th pin connects with the 4th pin and the 12nd pin of selector U7, and the 7th pin of operational amplifier U2 passes through resistance 13rd pin of R11 and operational amplifier U3 connects, and the 7th pin of operational amplifier U2 connects output w, operational amplifier 8th pin of U2 is connected by the 9th pin of electric capacity Cz and operational amplifier U2, the 8th pin of operational amplifier U2 Connecting with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R9 and operational amplifier U3's 9th pin connects, and the 8th pin of operational amplifier U2 connects the 13rd pin of output z, operational amplifier U2 and passes through resistance 14th pin of Rz and operational amplifier U2 connects, and the 14th pin of operational amplifier U2 is put with computing by resistance R3 9th pin of big device U2 connects;
1st pin of described operational amplifier U3 is connected by the 13rd pin of resistance Rx1 and operational amplifier U1, computing 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance 1st pin of R6 and operational amplifier U3 connects, and the 3rd pin of operational amplifier U3, the 5th pin, the 10th draws Foot, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin connects the 6th pin of VEE, operational amplifier U3 and leads to The 7th pin crossing resistance R8 and operational amplifier U3 connects, the 7th pin of operational amplifier U3 by resistance Ry2 with 2nd pin of operational amplifier U1 connects, and the 7th pin of operational amplifier U3 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 8th pin of operational amplifier U3 is by the 9th pin of resistance R10 and operational amplifier U3 Connecting, the 8th pin of operational amplifier U3 is connected by the 13rd pin of resistance Rz2 and operational amplifier U2, and computing is put 13rd pin of big device U3 is connected by the 14th pin of resistance R12 and operational amplifier U3, operational amplifier U3's 14th pin is connected by the 2nd pin of resistance Rw2 and operational amplifier U2;
2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected by the 1st pin of resistance R13 and selector U7, operation amplifier 1st pin of device U6 by resistance R13 and resistance R14 with connect, the 3rd pin of operational amplifier U6, the 5th draw Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U6 6 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin of described selector U7 and the 14th pin connect the 3rd pin of VCC, selector U7 and meet VEE, select 15th pin of device U7 and the 16th pin ground connection, the 8th pin of selector U7 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st draws Foot, the 12nd pin, the 13rd pin are unsettled.
Certainly, described above is not to the restriction invented, and the present invention is also not limited to the example above, the common skill of the art Change that art personnel are made in the essential scope of the present invention, retrofit, add or replace, fall within the protection model of the present invention Enclose.

Claims (1)

1. the Lorenz type hyperchaotic system construction method being easy to ultimate boundary estimation that a feedback is different, it is characterised in that include Following steps:
(1) Lorenz type chaos system i is:
d x / d t = a ( y - x ) d y / d t = b x - x z - c y d z / d t = x y - d z a = 12 , b = 23 , c = 1 , d = 2.1 - - - i
X in formula, y, z are state variable, and a, b, c, d are systematic parameter;
(2) on chaos system i, one-dimensional variable w is increased:
Dw/dt=-ky-rw k=5, r=0.1 ii
In formula, w is state variable, and k, r are systematic parameter;
(3) using variable i i as unidimensional system variable, it is added on first equation of Lorenz type chaos system i, it is thus achieved that one is easy to Lorenz type hyperchaotic system iii that ultimate boundary is estimated is:
d x / d t = a ( y - x ) + w d y / d t = b x - x z - c y d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - i i i
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(4) using variable i i as unidimensional system variable, it is added on second equation of Lorenz type chaos system i, it is thus achieved that one is easy to Lorenz type hyperchaotic system iv that ultimate boundary is estimated is:
d x / d t = a ( y - x ) d y / d t = b x - x z - c y + w d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - i v
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1;
(5) structure one selects function v and vi to switch super mixed by a kind of for iii and iv composition Lorenz type being easy to ultimate boundary estimation Ignorant system vii is:
f ( y ) = 1 y &GreaterEqual; 0 0 y < 0 - - - v
f ( - y ) = 0 y &GreaterEqual; 0 1 y < 0 - - - v i
d x / d t = a ( y - x ) + f ( y ) w d y / d t = b x - x z - x y + f ( - y ) w d z / d t = x y - d z d w / d t = - k y - r w a = 12 , b = 23 , c = 1 , d = 2.1 , k = 5 , r = 0.1 - - - v i i
X in formula, y, z, w are state variable, and f (x), f (-x) are switching functions, and a, b, c, d, k, r are systematic parameter;
(6) circuit based on system vii structure, utilizes operational amplifier U1, operational amplifier U2 and resistance, electric capacity to realize adding Method and integral operation, utilize operational amplifier U3 and resistance to realize anti-phase computing, multiplier U4 and multiplier U5 and realize system Multiplying in system, described operational amplifier U1 concatenation operation amplifier U3, operational amplifier U6 and multiplier U5, Described operational amplifier U2 connects multiplier U4 and operational amplifier U3, described operational amplifier U3 concatenation operation amplifier U1, operational amplifier U2, operational amplifier U6 and multiplier U4, described multiplier U4 concatenation operation amplifier U1, institute State multiplier U5 concatenation operation amplifier U2;Described operational amplifier U6 connects selector U7, described selector U7 and connects Operational amplifier U1, described operational amplifier U1, U2, U3 and U6 use LF347BN, described multiplier U4 and U5 Using AD633JN, described selector uses ADG409;
1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R2 and operational amplifier U1, and computing is put 2nd pin of big device U1 is connected by the 1st pin of resistance Ry and operational amplifier U1, the 3rd of operational amplifier U1 Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meets VCC, and computing is put 11st pin of big device U1 connects the 6th pin of VEE, operational amplifier U1 by electric capacity Cy and operational amplifier U1's 7th pin connects, the 7th pin of operational amplifier U1 the 13rd pin phase by resistance Rx2 and operational amplifier U1 Connecing, the 7th pin of operational amplifier U1 connects with the 1st pin of multiplier U5, the 7th pin of operational amplifier U1 Being connected by the 6th pin of resistance R7 and operational amplifier U3, the 7th pin of operational amplifier U1 connects output y, computing 8th pin of amplifier U1 is connected by the 9th pin of electric capacity Cx and operational amplifier U1, the of operational amplifier U1 8 pins are connected by the 2nd pin of resistance Ry1 and operational amplifier U1, and the 8th pin of operational amplifier U1 is by electricity 2nd pin of resistance R5 and operational amplifier U3 connects, and the 8th pin of operational amplifier U1 draws with the 3rd of multiplier U5 Foot connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operational amplifier U1's 8th pin is connect the 13rd pin of output x, operational amplifier U1 and is drawn with the 14th of operational amplifier U1 by resistance Rx Foot connects, and the 14th pin of operational amplifier U1 is connected by the 9th pin of resistance R1 and operational amplifier U1;
1st pin of described operational amplifier U2 is connected by the 6th pin of resistance R4 and operational amplifier U2, computing 2nd pin of amplifier U2 is connected by the 1st pin of resistance Rw and operational amplifier U2, the of operational amplifier U2 3 pins, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, fortune The 6th pin calculating amplifier U2 is connected by the 7th pin of electric capacity Cw and operational amplifier U2, operational amplifier U2's 7th pin connects with the 4th pin and the 12nd pin of selector U7, and the 7th pin of operational amplifier U2 passes through resistance 13rd pin of R11 and operational amplifier U3 connects, and the 7th pin of operational amplifier U2 connects output w, operational amplifier 8th pin of U2 is connected by the 9th pin of electric capacity Cz and operational amplifier U2, the 8th pin of operational amplifier U2 Connecting with the 3rd pin of multiplier U4, the 8th pin of operational amplifier U2 is by resistance R9 and operational amplifier U3's 9th pin connects, and the 8th pin of operational amplifier U2 connects the 13rd pin of output z, operational amplifier U2 and passes through resistance 14th pin of Rz and operational amplifier U2 connects, and the 14th pin of operational amplifier U2 is put with computing by resistance R3 9th pin of big device U2 connects;
1st pin of described operational amplifier U3 is connected by the 13rd pin of resistance Rx1 and operational amplifier U1, computing 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance 1st pin of R6 and operational amplifier U3 connects, and the 3rd pin of operational amplifier U3, the 5th pin, the 10th draws Foot, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin connects the 6th pin of VEE, operational amplifier U3 and leads to The 7th pin crossing resistance R8 and operational amplifier U3 connects, the 7th pin of operational amplifier U3 by resistance Ry2 with 2nd pin of operational amplifier U1 connects, and the 7th pin of operational amplifier U3 passes through resistance Rw1 and operational amplifier 2nd pin of U2 connects, and the 8th pin of operational amplifier U3 is by the 9th pin of resistance R10 and operational amplifier U3 Connecting, the 8th pin of operational amplifier U3 is connected by the 13rd pin of resistance Rz2 and operational amplifier U2, and computing is put 13rd pin of big device U3 is connected by the 14th pin of resistance R12 and operational amplifier U3, operational amplifier U3's 14th pin is connected by the 2nd pin of resistance Rw2 and operational amplifier U2;
2nd pin of described multiplier U4, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects the 2nd pin of operational amplifier U1 by resistance Ry3, and the 8th pin meets VCC;
2nd pin of described multiplier U5, the 4th pin, the 6th equal ground connection of pin, the 5th pin meets VEE, and the 7th draws Foot connects operational amplifier U2 the 13rd pin by resistance Rz1, and the 8th pin meets VCC;
1st pin of described operational amplifier U6 is connected by the 1st pin of resistance R13 and selector U7, operation amplifier 1st pin of device U6 by resistance R13 and resistance R14 with connect, the 3rd pin of operational amplifier U6, the 5th draw Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC, and the 11st pin meets VEE, operational amplifier U6 6 pins, the 7th pin, the 8th pin, the 9th pin, the 12nd pin, the 13rd pin, the 14th pin are unsettled;
2nd pin of described selector U7 and the 14th pin connect the 3rd pin of VCC, selector U7 and meet VEE, selector U7 The 15th pin and the 16th pin ground connection, the 8th pin of selector U7 by resistance Rw1 and operational amplifier U2 the 2 pins connect, the 6th pin of selector U7, the 7th pin, the 9th pin, the 10th pin, the 11st pin, the 12nd Pin, the 13rd pin are unsettled.
CN201510279462.6A 2015-05-27 2015-05-27 A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated Expired - Fee Related CN104836658B (en)

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