CN105471574B - It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation - Google Patents
It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation Download PDFInfo
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Abstract
The present invention provides a kind of feedback the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation, addition and integral operation are realized using operational amplifier U1, operational amplifier U2 and resistance, capacitance, reverse phase computing is realized using operational amplifier U3 and resistance, multiplying in multiplier U4 and multiplier U5 realization systems, described operational amplifier U1, U2, U3 and U6 use LF347BN, the multiplier U4 and U5 uses AD633JN, and the selector uses DG409；The present invention is on the basis of Lorenz type chaos systems, it designs a kind of one analog circuit of different Lorenz type hyperchaoses system's construction methods that ultimate boundary is convenient for estimate and circuit construction method and design that feeds back to carry out realizing this chaos system, new hyperchaotic system signal source is provided for the synchronization and control of chaos.
Description
Technical field
The present invention relates to a kind of chaos system and circuit, more particularly to it is a kind of feed back it is different convenient for ultimate boundary estimation
Lorenz type hyperchaotic system circuits.
Background technology
The border estimation of hyperchaotic system has great importance in terms of the engineer applications such as the controlling of chaos, synchronous, when
Before, the method for four dimension ultra-chaos of construction increases by four dimension ultra-chaos systems of one-dimensional composition mainly on the basis of three-dimensional chaotic system
System, but the hyperchaotic system formed is not easy to carry out ultimate boundary estimation, can carry out the hyperchaos system of ultimate boundary estimation
System has the characteristic that：The all negative values of characteristic element of Jacobian matrix leading diagonal, the hyperchaotic system that the present invention constructs
There is all negative values of characteristic element of Jacobian matrix leading diagonal, ultimate boundary estimation can be carried out, this for
The controlling of hyperchaos, synchronous etc. have important job applications prospect.
The content of the invention
The different Lorenz types convenient for ultimate boundary estimation are fed back the technical problem to be solved in the present invention is to provide a kind of
Hyperchaotic system circuit：
1. a kind of feed back the different Lorenz type hyperchaotic system construction methods convenient for ultimate boundary estimation, feature exists
In comprising the following steps：
(1) Lorenz types chaos system i is：
X in formula, y, z are state variable, and a, b, c, d are systematic parameter；
(2) one-dimensional variable w is increased on chaos system i：
Dw/dt=-ky-rw k=5, r=0.1 ii
W is state variable in formula, and k, r are systematic parameter；
(3) using variable i i as unidimensional system variable, it is added on the first equation of Lorenz type chaos systems i, obtains one
Planting the Lorenz type hyperchaotic systems iii estimated convenient for ultimate boundary is：
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1；
(4) using variable i i as unidimensional system variable, it is added in the second equation of Lorenz type chaos systems i, obtains one
Planting the Lorenz type hyperchaotic systems iv estimated convenient for ultimate boundary is：
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1；
(5) a selection function v and vi is constructed to cut a kind of Lorenz types convenient for ultimate boundary estimation of iii and iv compositions
Changing hyperchaotic system vii is：
X in formula, y, z, w are state variable, and f (x), f (- x) are switching functions, and a, b, c, d, k, r are systematic parameter；
(6) circuit based on system vii constructions is realized using operational amplifier U1, operational amplifier U2 and resistance, capacitance
Addition and integral operation realize reverse phase computing using operational amplifier U3 and resistance, and multiplier U4 and multiplier U5 realize system
In multiplying, the operational amplifier U1 concatenation operation amplifiers U3, operational amplifier U6 and multiplier U5, the computing
Amplifier U2 connection multiplier U4 and operational amplifier U3, the operational amplifier U3 concatenation operation amplifiers U1, operation amplifier
Device U2, operational amplifier U6 and multiplier U4, the multiplier U4 concatenation operation amplifiers U1, the multiplier U5 concatenation operations
Amplifier U2；The operational amplifier U6 connection selectors U7, the selector U7 concatenation operation amplifiers U1, the computing are put
For big device U1, U2, U3 and U6 using LF347BN, the multiplier U4 and U5 uses AD633JN, and the selector uses ADG409；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and computing is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected by resistance Rx2 with the 13rd pin of operational amplifier U1, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, computing
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, computing
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and computing is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected by capacitance Cw with the 7th pin of operational amplifier U2, the 7th pin of operational amplifier U2 draws with the 4th of selector U7
Foot and the 12nd pin connect, the 13rd pin phase that the 7th pin of operational amplifier U2 passes through resistance R11 and operational amplifier U3
It connects, the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operational amplifier U2
The 9th pin connect, the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, the 8th of operational amplifier U2 the
Pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 meets output z, and computing is put
The 13rd pin of big device U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, the 14th pin of operational amplifier U2
Connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, computing
The 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance R6 and fortune
The 1st pin for calculating amplifier U3 connects, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection,
4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U3 passes through the 7th of resistance R8 and operational amplifier U3
Pin connects, and the 7th pin of operational amplifier U3 is connected by resistance Ry2 with the 2nd pin of operational amplifier U1, operation amplifier
The 7th pin of device U3 is connected by resistance Rw1 with the 2nd pin of operational amplifier U2, and the 8th pin of operational amplifier U3 passes through
Resistance R10 connects with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U3 passes through resistance Rz2 and operation amplifier
The 13rd pin of device U2 connects, and the 13rd pin of operational amplifier U3 passes through the 14th pin of resistance R12 and operational amplifier U3
Connect, the 14th pin of operational amplifier U3 is connected by resistance Rw2 with the 2nd pin of operational amplifier U2；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 13rd pin, the 14th pin are hanging；
The 1st pin of the selector U7 connects the 1st pin of operational amplifier U6 by resistance R13, and the 1st of selector U7 the
Pin is grounded by resistance R14, and the 2nd pin of selector U7 and the 14th pin meet VCC, and the 3rd pin of selector U7 meets VEE,
The 4th pin of selector U7 and the 12nd pin connect the 7th pin of operational amplifier U2, and the 5th pin of selector U7, the 13rd are drawn
Foot, the 15th pin and the 16th pin ground connection, the 8th pin output w1 of selector U7, pass through resistance Rx3's and operational amplifier U1
13rd pin connects, and the 9th pin output w2 of selector U7 is connected by resistance Ry4 with the 2nd pin of operational amplifier U1,
The 6th pin, the 7th pin, the 10th pin, the 11st pin of selector U7 is hanging.
2. a kind of feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation, which is characterized in that
Realize addition and integral operation using operational amplifier U1, operational amplifier U2 and resistance, capacitance, using operational amplifier U3 and
Resistance realizes reverse phase computing, the multiplying in multiplier U4 and multiplier U5 realization systems, the operational amplifier U1 connections
Operational amplifier U3, operational amplifier U6 and multiplier U5, the operational amplifier U2 connection multiplier U4 and operational amplifier
U3, the operational amplifier U3 concatenation operation amplifiers U1, operational amplifier U2, operational amplifier U6 and multiplier U4, it is described
Multiplier U4 concatenation operation amplifiers U1, the multiplier U5 concatenation operation amplifiers U2；The operational amplifier U6 connections choosing
Device U7, the selector U7 concatenation operation amplifiers U1 are selected, described operational amplifier U1, U2, U3 and U6 use LF347BN, institute
Multiplier U4 and U5 are stated using AD633JN, the selector uses ADG409；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and computing is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected by resistance Rx2 with the 13rd pin of operational amplifier U1, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, computing
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, computing
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and computing is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected by capacitance Cw with the 7th pin of operational amplifier U2, the 7th pin of operational amplifier U2 draws with the 4th of selector U7
Foot and the 12nd pin connect, the 13rd pin phase that the 7th pin of operational amplifier U2 passes through resistance R11 and operational amplifier U3
It connects, the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operational amplifier U2
The 9th pin connect, the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, the 8th of operational amplifier U2 the
Pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 meets output z, and computing is put
The 13rd pin of big device U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, the 14th pin of operational amplifier U2
Connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, computing
The 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance R6 and fortune
The 1st pin for calculating amplifier U3 connects, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection,
4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U3 passes through the 7th of resistance R8 and operational amplifier U3
Pin connects, and the 7th pin of operational amplifier U3 is connected by resistance Ry2 with the 2nd pin of operational amplifier U1, operation amplifier
The 7th pin of device U3 is connected by resistance Rw1 with the 2nd pin of operational amplifier U2, and the 8th pin of operational amplifier U3 passes through
Resistance R10 connects with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U3 passes through resistance Rz2 and operation amplifier
The 13rd pin of device U2 connects, and the 13rd pin of operational amplifier U3 passes through the 14th pin of resistance R12 and operational amplifier U3
Connect, the 14th pin of operational amplifier U3 is connected by resistance Rw2 with the 2nd pin of operational amplifier U2；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 13rd pin, the 14th pin are hanging；
The 1st pin of the selector U7 connects the 1st pin of operational amplifier U6 by resistance R13, and the 1st of selector U7 the
Pin is grounded by resistance R14, and the 2nd pin of selector U7 and the 14th pin meet VCC, and the 3rd pin of selector U7 meets VEE,
The 4th pin of selector U7 and the 12nd pin connect the 7th pin of operational amplifier U2, and the 5th pin of selector U7, the 13rd are drawn
Foot, the 15th pin and the 16th pin ground connection, the 8th pin output w1 of selector U7, pass through resistance Rx3's and operational amplifier U1
13rd pin connects, and the 9th pin output w2 of selector U7 is connected by resistance Ry4 with the 2nd pin of operational amplifier U1,
The 6th pin, the 7th pin, the 10th pin, the 11st pin of selector U7 is hanging.
Advantageous effect：The present invention on the basis of Lorenz type chaos systems, devise it is a kind of feed back it is different convenient for eventually
One analog circuit of Lorenz type hyperchaotic system construction methods and design of pole border estimation carries out realizing this chaos system, is
The synchronization and control of chaos provide new hyperchaotic system signal source.
Description of the drawings
Fig. 1 is the schematic diagram of circuit connection structure of the preferred embodiment of the present invention.
Fig. 2 is the actual connection figure of circuit of multiplier U4 and operational amplifier U1.
Fig. 3 is the actual connection figure of circuit of operational amplifier U3.
Fig. 4 is the actual connection figure of circuit of multiplier U5 and operational amplifier U2.
Fig. 5 is the actual connection figure of circuit of selector U7 and operational amplifier U6.
Specific embodiment
The present invention is further described in detail with preferred embodiment below in conjunction with the accompanying drawings, referring to Fig. 1-Fig. 5.
1. a kind of feed back the different Lorenz type hyperchaotic system construction methods convenient for ultimate boundary estimation, feature exists
In comprising the following steps：
(1) Lorenz types chaos system i is：
X in formula, y, z are state variable, and a, b, c, d are systematic parameter；
(2) one-dimensional variable w is increased on chaos system i：
Dw/dt=-ky-rw k=5, r=0.1 ii
W is state variable in formula, and k, r are systematic parameter；
(3) using variable i i as unidimensional system variable, it is added on the first equation of Lorenz type chaos systems i, obtains one
Planting the Lorenz type hyperchaotic systems iii estimated convenient for ultimate boundary is：
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1；
(4) using variable i i as unidimensional system variable, it is added in the second equation of Lorenz type chaos systems i, obtains one
Planting the Lorenz type hyperchaotic systems iv estimated convenient for ultimate boundary is：
X in formula, y, z, w are state variable, parameter value a=12, b=23, c=1, d=2.1, k=5, r=0.1；
(5) a selection function v and vi is constructed to cut a kind of Lorenz types convenient for ultimate boundary estimation of iii and iv compositions
Changing hyperchaotic system vii is：
X in formula, y, z, w are state variable, and f (x), f (- x) are switching functions, and a, b, c, d, k, r are systematic parameter；
(6) circuit based on system vii constructions is realized using operational amplifier U1, operational amplifier U2 and resistance, capacitance
Addition and integral operation realize reverse phase computing using operational amplifier U3 and resistance, and multiplier U4 and multiplier U5 realize system
In multiplying, the operational amplifier U1 concatenation operation amplifiers U3, operational amplifier U6 and multiplier U5, the computing
Amplifier U2 connection multiplier U4 and operational amplifier U3, the operational amplifier U3 concatenation operation amplifiers U1, operation amplifier
Device U2, operational amplifier U6 and multiplier U4, the multiplier U4 concatenation operation amplifiers U1, the multiplier U5 concatenation operations
Amplifier U2；The operational amplifier U6 connection selectors U7, the selector U7 concatenation operation amplifiers U1, the computing are put
For big device U1, U2, U3 and U6 using LF347BN, the multiplier U4 and U5 uses AD633JN, and the selector uses ADG409；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and computing is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected by resistance Rx2 with the 13rd pin of operational amplifier U1, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, computing
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, computing
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and computing is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected by capacitance Cw with the 7th pin of operational amplifier U2, the 7th pin of operational amplifier U2 draws with the 4th of selector U7
Foot and the 12nd pin connect, the 13rd pin phase that the 7th pin of operational amplifier U2 passes through resistance R11 and operational amplifier U3
It connects, the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operational amplifier U2
The 9th pin connect, the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, the 8th of operational amplifier U2 the
Pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 meets output z, and computing is put
The 13rd pin of big device U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, the 14th pin of operational amplifier U2
Connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, computing
The 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance R6 and fortune
The 1st pin for calculating amplifier U3 connects, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection,
4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U3 passes through the 7th of resistance R8 and operational amplifier U3
Pin connects, and the 7th pin of operational amplifier U3 is connected by resistance Ry2 with the 2nd pin of operational amplifier U1, operation amplifier
The 7th pin of device U3 is connected by resistance Rw1 with the 2nd pin of operational amplifier U2, and the 8th pin of operational amplifier U3 passes through
Resistance R10 connects with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U3 passes through resistance Rz2 and operation amplifier
The 13rd pin of device U2 connects, and the 13rd pin of operational amplifier U3 passes through the 14th pin of resistance R12 and operational amplifier U3
Connect, the 14th pin of operational amplifier U3 is connected by resistance Rw2 with the 2nd pin of operational amplifier U2；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 13rd pin, the 14th pin are hanging；
The 1st pin of the selector U7 connects the 1st pin of operational amplifier U6 by resistance R13, and the 1st of selector U7 the
Pin is grounded by resistance R14, and the 2nd pin of selector U7 and the 14th pin meet VCC, and the 3rd pin of selector U7 meets VEE,
The 4th pin of selector U7 and the 12nd pin connect the 7th pin of operational amplifier U2, and the 5th pin of selector U7, the 13rd are drawn
Foot, the 15th pin and the 16th pin ground connection, the 8th pin output w1 of selector U7, pass through resistance Rx3's and operational amplifier U1
13rd pin connects, and the 9th pin output w2 of selector U7 is connected by resistance Ry4 with the 2nd pin of operational amplifier U1,
The 6th pin, the 7th pin, the 10th pin, the 11st pin of selector U7 is hanging.
2. a kind of feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation, which is characterized in that
Realize addition and integral operation using operational amplifier U1, operational amplifier U2 and resistance, capacitance, using operational amplifier U3 and
Resistance realizes reverse phase computing, the multiplying in multiplier U4 and multiplier U5 realization systems, the operational amplifier U1 connections
Operational amplifier U3, operational amplifier U6 and multiplier U5, the operational amplifier U2 connection multiplier U4 and operational amplifier
U3, the operational amplifier U3 concatenation operation amplifiers U1, operational amplifier U2, operational amplifier U6 and multiplier U4, it is described
Multiplier U4 concatenation operation amplifiers U1, the multiplier U5 concatenation operation amplifiers U2；The operational amplifier U6 connections choosing
Device U7, the selector U7 concatenation operation amplifiers U1 are selected, described operational amplifier U1, U2, U3 and U6 use LF347BN, institute
Multiplier U4 and U5 are stated using AD633JN, the selector uses ADG409；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, and computing is put
The 2nd pin of big device U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, the 3rd pin of operational amplifier U1, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 connect VCC, the 11st pin of operational amplifier U1
VEE is met, the 6th pin of operational amplifier U1 is connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1
The 7th pin connected by resistance Rx2 with the 13rd pin of operational amplifier U1, the 7th pin and multiplication of operational amplifier U1
The 1st pin of device U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3,
The 8th pin that the 7th pin of operational amplifier U1 meets output y, operational amplifier U1 passes through capacitance Cx's and operational amplifier U1
9th pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, computing
The 8th pin of amplifier U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, the 8th pin of operational amplifier U1
Connect with the 3rd pin of multiplier U5, the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, computing
The 8th pin of amplifier U1 connects the 13rd pin of output x, operational amplifier U1 by the 14th of resistance Rx and operational amplifier U1
Pin connects, and the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, and computing is put
The 2nd pin of big device U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, the 3rd pin of operational amplifier U2, the
5 pins, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pin of operational amplifier U2
Connected by capacitance Cw with the 7th pin of operational amplifier U2, the 7th pin of operational amplifier U2 draws with the 4th of selector U7
Foot and the 12nd pin connect, the 13rd pin phase that the 7th pin of operational amplifier U2 passes through resistance R11 and operational amplifier U3
It connects, the 7th pin of operational amplifier U2 meets output w, and the 8th pin of operational amplifier U2 passes through capacitance Cz and operational amplifier U2
The 9th pin connect, the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, the 8th of operational amplifier U2 the
Pin is connected by resistance R9 with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U2 meets output z, and computing is put
The 13rd pin of big device U2 is connected by resistance Rz with the 14th pin of operational amplifier U2, the 14th pin of operational amplifier U2
Connected by resistance R3 with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, computing
The 1st pin of amplifier U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 passes through resistance R6 and fortune
The 1st pin for calculating amplifier U3 connects, the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection,
4th pin meets VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U3 passes through the 7th of resistance R8 and operational amplifier U3
Pin connects, and the 7th pin of operational amplifier U3 is connected by resistance Ry2 with the 2nd pin of operational amplifier U1, operation amplifier
The 7th pin of device U3 is connected by resistance Rw1 with the 2nd pin of operational amplifier U2, and the 8th pin of operational amplifier U3 passes through
Resistance R10 connects with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U3 passes through resistance Rz2 and operation amplifier
The 13rd pin of device U2 connects, and the 13rd pin of operational amplifier U3 passes through the 14th pin of resistance R12 and operational amplifier U3
Connect, the 14th pin of operational amplifier U3 is connected by resistance Rw2 with the 2nd pin of operational amplifier U2；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through
Resistance Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operation amplifier
The 1st pin of device U6 is connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th
Pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th
Pin, the 9th pin, the 13rd pin, the 14th pin are hanging；
The 1st pin of the selector U7 connects the 1st pin of operational amplifier U6 by resistance R13, and the 1st of selector U7 the
Pin is grounded by resistance R14, and the 2nd pin of selector U7 and the 14th pin meet VCC, and the 3rd pin of selector U7 meets VEE,
The 4th pin of selector U7 and the 12nd pin connect the 7th pin of operational amplifier U2, and the 5th pin of selector U7, the 13rd are drawn
Foot, the 15th pin and the 16th pin ground connection, the 8th pin output w1 of selector U7, pass through resistance Rx3's and operational amplifier U1
13rd pin connects, and the 9th pin output w2 of selector U7 is connected by resistance Ry4 with the 2nd pin of operational amplifier U1,
The 6th pin, the 7th pin, the 10th pin, the 11st pin of selector U7 is hanging.
Certainly, above description is not limitation to invention, and the present invention is also not limited to the example above, the art it is general
The variations, modifications, additions or substitutions that logical technical staff is made in the essential scope of the present invention, fall within the protection of the present invention
Scope.
Claims (1)
1. a kind of feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation, which is characterized in that utilizes
Operational amplifier U1, operational amplifier U2 and resistance, capacitance realize addition and integral operation, utilize operational amplifier U3 and resistance
Realize reverse phase computing, the multiplying in multiplier U4 and multiplier U5 realization systems, the operational amplifier U1 concatenation operations
Amplifier U3, operational amplifier U6 and multiplier U5, the operational amplifier U2 connection multiplier U4 and operational amplifier U3, institute
State operational amplifier U3 concatenation operation amplifiers U1, operational amplifier U2, operational amplifier U6 and multiplier U4, the multiplier
U4 concatenation operation amplifiers U1, the multiplier U5 concatenation operation amplifiers U2；The operational amplifier U6 connections selector U7,
The selector U7 concatenation operation amplifiers U1, described operational amplifier U1, U2, U3 and U6 use LF347BN, the multiplier
U4 and U5 uses AD633JN, and the selector uses ADG409；
The 1st pin of the operational amplifier U1 is connected by resistance R2 with the 6th pin of operational amplifier U1, operational amplifier
The 2nd pin of U1 is connected by resistance Ry with the 1st pin of operational amplifier U1, and the 3rd pin of operational amplifier U1, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin of operational amplifier U1 meet VCC, and the 11st pin of operational amplifier U1 connects
The 6th pin of VEE, operational amplifier U1 are connected by capacitance Cy with the 7th pin of operational amplifier U1, operational amplifier U1's
7th pin is connected by resistance Rx2 with the 13rd pin of operational amplifier U1, the 7th pin and multiplier of operational amplifier U1
The 1st pin of U5 connects, and the 7th pin of operational amplifier U1 is connected by resistance R7 with the 6th pin of operational amplifier U3, fortune
The 7th pin for calculating amplifier U1 connects the 8th pin of output y, operational amplifier U1 by the 9th of capacitance Cx and operational amplifier U1
Pin connects, and the 8th pin of operational amplifier U1 is connected by resistance Ry1 with the 2nd pin of operational amplifier U1, operation amplifier
The 8th pin of device U1 is connected by resistance R5 with the 2nd pin of operational amplifier U3, and the 8th pin of operational amplifier U1 is with multiplying
The 3rd pin of musical instruments used in a Buddhist or Taoist mass U5 connects, and the 8th pin of operational amplifier U1 connects with the 2nd pin of operational amplifier U6, operation amplifier
The 13rd pin that the 8th pin of device U1 meets output x, operational amplifier U1 passes through the 14th pin of resistance Rx and operational amplifier U1
Connect, the 14th pin of operational amplifier U1 is connected by resistance R1 with the 9th pin of operational amplifier U1；
The 1st pin of the operational amplifier U2 is connected by resistance R4 with the 6th pin of operational amplifier U2, operational amplifier
The 2nd pin of U2 is connected by resistance Rw with the 1st pin of operational amplifier U2, and the 3rd pin of operational amplifier U2, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U2 passes through
Capacitance Cw connects with the 7th pin of operational amplifier U2, the 7th pin of operational amplifier U2 and the 4th pin of selector U7 and
12nd pin connects, and the 7th pin of operational amplifier U2 is connected by resistance R11 with the 13rd pin of operational amplifier U3, fortune
The 7th pin for calculating amplifier U2 connects the 8th pin of output w, operational amplifier U2 by the 9th of capacitance Cz and operational amplifier U2
Pin connects, and the 8th pin of operational amplifier U2 connects with the 3rd pin of multiplier U4, and the 8th pin of operational amplifier U2 leads to
It crosses resistance R9 with the 9th pin of operational amplifier U3 to connect, the 8th pin of operational amplifier U2 meets output z, operational amplifier U2
The 13rd pin connected by resistance Rz with the 14th pin of operational amplifier U2, the 14th pin of operational amplifier U2 passes through electricity
Resistance R3 connects with the 9th pin of operational amplifier U2；
The 1st pin of the operational amplifier U3 is connected by resistance Rx1 with the 13rd pin of operational amplifier U1, operation amplifier
The 1st pin of device U3 connects with the 1st pin of multiplier U4, and the 2nd pin of operational amplifier U3 is put by resistance R6 with computing
The 1st pin of big device U3 connects, and the 3rd pin of operational amplifier U3, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th draws
Foot meets VCC, and the 11st pin meets VEE, and the 6th pin of operational amplifier U3 passes through the 7th pin of resistance R8 and operational amplifier U3
Connect, the 7th pin of operational amplifier U3 is connected by resistance Ry2 with the 2nd pin of operational amplifier U1, operational amplifier U3
The 7th pin connected by resistance Rw1 with the 2nd pin of operational amplifier U2, the 8th pin of operational amplifier U3 passes through resistance
R10 connects with the 9th pin of operational amplifier U3, and the 8th pin of operational amplifier U3 passes through resistance Rz2 and operational amplifier U2
The 13rd pin connect, the 13rd pin of operational amplifier U3 is connected by resistance R12 with the 14th pin of operational amplifier U3,
The 14th pin of operational amplifier U3 is connected by resistance Rw2 with the 2nd pin of operational amplifier U2；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U4 is grounded, and the 5th pin meets VEE, and the 7th pin passes through resistance
Ry3 connects the 2nd pin of operational amplifier U1, and the 8th pin meets VCC；
The 2nd pin, the 4th pin, the 6th pin of the multiplier U5 is grounded, and the 5th pin meets VEE, and the 7th pin passes through resistance
Rz1 connects the 13rd pins of operational amplifier U2, and the 8th pin meets VCC；
The 1st pin of the operational amplifier U6 is connected by resistance R13 with the 1st pin of selector U7, operational amplifier U6
The 1st pin connected by resistance R13 and resistance R14 with ground, the 3rd pin of operational amplifier U6, the 5th pin, the 10th pin,
12nd pin is grounded, and the 4th pin meets VCC, and the 11st pin meets VEE, the 6th pins of operational amplifier U6, the 7th pin, the 8th pin,
9th pin, the 13rd pin, the 14th pin are hanging；
The 1st pin of the selector U7 connects the 1st pin of operational amplifier U6, the 1st pin of selector U7 by resistance R13
It is grounded by resistance R14, the 2nd pin of selector U7 and the 14th pin meet VCC, and the 3rd pin of selector U7 meets VEE, selection
The 4th pin of device U7 and the 12nd pin connect the 7th pin of operational amplifier U2, the 5th pin of selector U7, the 13rd pin,
15 pins and the 16th pin ground connection, the 8th pin output w1 of selector U7, pass through the 13rd of resistance Rx3 and operational amplifier U1 the
Pin connects, and the 9th pin output w2 of selector U7 is connected with the 2nd pin of operational amplifier U1 by resistance Ry4, selected
The 6th pin, the 7th pin, the 10th pin, the 11st pin of device U7 is hanging.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610005319.2A CN105471574B (en) | 2015-05-27 | 2015-05-27 | It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation |
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| CN201610005319.2A CN105471574B (en) | 2015-05-27 | 2015-05-27 | It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation |
| CN201510279462.6A CN104836658B (en) | 2015-05-27 | 2015-05-27 | A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated |
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| CN201510279462.6A Division CN104836658B (en) | 2015-05-27 | 2015-05-27 | A kind of feedback different is easy to the Lorenz type hyperchaotic system construction method that ultimate boundary is estimated |
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| CN201610005319.2A Expired - Fee Related CN105471574B (en) | 2015-05-27 | 2015-05-27 | It is a kind of to feed back the different Lorenz type hyperchaotic system circuits convenient for ultimate boundary estimation |
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| CN105243257A (en) * | 2015-08-26 | 2016-01-13 | 韩敬伟 | Five-quasi-periodic spherical oscillator and circuit |
| CN105117600A (en) * | 2015-08-26 | 2015-12-02 | 王晓红 | Five-term spherical quasi-periodic oscillation system and circuit |
| CN105160167A (en) * | 2015-08-26 | 2015-12-16 | 王晓红 | Spherical quasi-periodic oscillator and circuit |
| CN105119710A (en) * | 2015-09-09 | 2015-12-02 | 王春梅 | Lorenz type hyper-chaotic system adaptive synchronization method and circuit beneficial to ultimate edge estimation |
| CN105119714A (en) * | 2015-09-09 | 2015-12-02 | 韩敬伟 | Self-adaptive synchronization method and circuit for Lorenz type hyper-chaotic system convenient for ultimate boundary estimation |
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| CN103856317A (en) * | 2014-02-22 | 2014-06-11 | 滨州学院 | Method and circuit for switching classic Lorenz type chaotic system with different fractional orders |
| CN104283670A (en) * | 2014-08-30 | 2015-01-14 | 李敏 | Four-system automatic switching hyperchaotic system construction method based on Lu system and analog circuit |
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| US5680462A (en) * | 1995-08-07 | 1997-10-21 | Sandia Corporation | Information encoder/decoder using chaotic systems |
| CN102332976B (en) * | 2011-09-15 | 2013-11-06 | 江西理工大学 | Different-dimensional switchable chaotic system design method and circuit |
| CN103217901A (en) * | 2013-01-31 | 2013-07-24 | 王少夫 | Chaotic system tracking control method |
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2015
- 2015-05-27 CN CN201510279462.6A patent/CN104836658B/en not_active Expired - Fee Related
- 2015-05-27 CN CN201610005319.2A patent/CN105471574B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856317A (en) * | 2014-02-22 | 2014-06-11 | 滨州学院 | Method and circuit for switching classic Lorenz type chaotic system with different fractional orders |
| CN104283670A (en) * | 2014-08-30 | 2015-01-14 | 李敏 | Four-system automatic switching hyperchaotic system construction method based on Lu system and analog circuit |
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| 《一个新的超混沌系统》;刘明华，冯久超;《物理学报》;20090715;第58卷(第7期);全文 * |
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| WO2016187739A1 (en) | 2016-12-01 |
| CN104836658B (en) | 2016-10-12 |
| CN105471574A (en) | 2016-04-06 |
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