CN105577358B - The construction method of the Lu type hyperchaotic system containing the side y based on memristor - Google Patents
The construction method of the Lu type hyperchaotic system containing the side y based on memristor Download PDFInfo
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Abstract
The construction method for the Lu type hyperchaotic system containing the side y based on memristor that the present invention relates to a kind of, utilize operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance, capacitor realizes addition, reverse phase and integral operation, utilize multiplier U4, with the multiplying in multiplier U5 realization system, the memristor model in the present invention is realized using operational amplifier U6 and multiplier U7 and multiplier U8, operational amplifier U1 connection operational amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier U8, operational amplifier U2 connection operational amplifier U3 and multiplier U4, operational amplifier U3 connection multiplier U5, operational amplifier U6 connection multiplier U7 and multiplier U8, multiplier U7 connection multiplier U8, the present invention is containing the side y Lu type chaos system on the basis of, increase the four-dimensional hyperchaotic system of one-dimensional compositions using memristor element, propose new method of the memristor applied to hyperchaotic system.
Description
Technical field
The present invention relates to a kind of chaos systems and circuit to realize, in particular to a kind of Lu type containing the side y based on memristor
The construction method of hyperchaotic system.
Background technique
Currently, the method for constructing four dimension ultra-chaos is mainly to increase one-dimensional composition four on the basis of three-dimensional chaotic system
Dimension ultra-chaos system, memristor can replace in cai's circuit as the newfound physical component of HP Lab in 2008
Cai Shi diode constitutes four dimensional chaos system, and hyperchaos are constituted in cai's circuit and then need 2 memristor elements, it is therefore desirable to
Systems more than five dimensions or five dimensions, realizes that the circuit system of hyperchaos is also fewer in the four-dimensional system with memristor element,
The method that memristor is applied to four-dimensional hyperchaotic system is suggested not yet, this is the deficiencies in the prior art place.
Summary of the invention
The structure for the Lu type hyperchaotic system containing the side y based on memristor that the technical problem to be solved in the present invention is to provide a kind of
Construction method:
1. the construction method of the Lu type hyperchaotic system containing the side y based on memristor, which is characterized in that including following step
It is rapid:
(1) the Lu type chaos system i containing the side y are as follows:
X in formula, y, z are state variable；
(2) memristor that the present invention uses is magnetic control memristor model ii are as follows:
WhereinIndicate magnetic control memristor,Indicate magnetic flux, m, n are greater than zero parameter；
(3) the magnetic control memristor model derivation of ii must be recalled and leads device model iii are as follows:
It indicates that magnetic control is recalled to lead, m, n are greater than zero parameter；
(4) magnetic control is recalled and leads device model iii as unidimensional system variable, be added in second of the Lu type chaos system containing the side y
On equation, a kind of Lu type hyperchaotic system iv containing the side y based on memristor is obtained:
X in formula, y, z, u are state variable, parameter value a=36, b=3, c=20, m=6, n=0.004, k=2；
(5) based on system iv construction circuit, using operational amplifier U1, operational amplifier U2, operational amplifier U3 and
Resistance, capacitor realize addition, reverse phase and integral operation, using the multiplying in multiplier U4 and multiplier U5 realization system,
The memristor model in the present invention is realized using operational amplifier U6 and multiplier U7, multiplier U8 and capacitor, and the operation is put
Big device U6 connection operational amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connection multiplier U8, multiplier U8 connection
Operational amplifier U2, described operational amplifier U1, U2 and U3 use LF347BN, and described multiplier U4, U5, U7 and U8 are used
AD633JN, the operational amplifier U6 use LF353N；
The 1st pin of the operational amplifier U1 is by the 2nd pin of capacitor Cx connection, by the 6th pin of resistance R2 connection,
3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 8th pin, the 9th
Pin floating, the 6th pin pass through memristor by the 13rd pin of resistance Rx1 connection by the 7th pin of resistance R3 connection, the 7th pin
Device Ry1 connects the 13rd pin of operational amplifier U2, and the 7th pin is directly connected to the 1st pin of multiplier U4, and the 13rd pin passes through electricity
The 14th pin of Rx connection is hindered, the 14th pin passes through the 2nd pin of resistance R1 connection；
The 1st pin, the 2nd pin, the 6th pin, the 7th pin floating of the operational amplifier U2, the 3rd pin, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 8th pin connects the 13rd by resistance Ry2
Pin connects the 13rd pin of operational amplifier U1 by resistance Rx2, connects the 9th pin by capacitor Cy, the 8th pin is directly connected to
The 1st pin of multiplier U5 and the 3rd pin, the 13rd pin connect the 14th pin by resistance Ry, and the 14th pin is connect by resistance R4
9th pin；
The 1st pin of the operational amplifier U3 connects the 2nd pin by capacitor Cz, connects the 6th pin by resistance R6, and the 1st
Pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin connects
VCC, the 11st pin meet VEE, the 8th pin, the 9th pin floating, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin passes through
Resistance Rz2 connects the 13rd pin, and the 13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
The 7th pin of the 1st pin connection operational amplifier U1 of the multiplier U4, the 2nd pin, the 4th pin, the 6th are drawn
Foot ground connection, the 3rd pin connect the 1st pin of operational amplifier U3, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin passes through
Resistance Ry3 connects the 13rd pin of operational amplifier U2；
1st pin of the 1st pin of the multiplier U5 and the 3rd pin connection operational amplifier U1, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 8th pin meets VCC, and the 7th pin connects the of operational amplifier U3 by resistance Rz1
13 pins；
The 1st pin, the 2nd pin, the 3rd pin floating of the operational amplifier U6, the 4th pin meet VEE, and the 5th pin connects
Ground, the 6th pin connect the 7th pin by capacitor C4, and by the 7th pin of resistance R8 connection operational amplifier U1, the 7th pin is direct
The 1st pin and the 3rd pin of multiplier U7 are connected, the 8th pin meets VCC；
7th pin of the 1st pin of the multiplier U7 and the 3rd pin connection operational amplifier U6, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
The 1st pin of the multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by resistance R10 and
The 7th pin of series connection of resistance R9, the 1st pin are directly connected to the 7th pin of operational amplifier U1, the 2nd pin, the 4th pin,
6 pins ground connection, the 5th pin meet VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin connects
VCC。
2. the Lu type hyperchaotic system circuit containing the side y based on memristor, it is characterised in that utilize operational amplifier U1, fortune
Amplifier U2, operational amplifier U3 and resistance, capacitor realization addition, reverse phase and integral operation are calculated, multiplier U4 and multiplication are utilized
Multiplying in device U5 realization system realizes recalling in the present invention using operational amplifier U6 and multiplier U7 and multiplier U8
Hinder device model, operational amplifier U1 connection operational amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplier
U8, operational amplifier U2 connection operational amplifier U3 and multiplier U4, operational amplifier U3 connection multiplier U5, operational amplifier
U6 connection multiplier U7 and multiplier U8, multiplier U7 connection multiplier U8, described operational amplifier U1, U2 and U3 are used
LF347BN, described multiplier U4, U5, U7 and U8 use AD633JN, the operational amplifier U6 to use LF353N；
The 1st pin of the operational amplifier U1 is by the 2nd pin of capacitor Cx connection, by the 6th pin of resistance R2 connection,
3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 8th pin, the 9th
Pin floating, the 6th pin pass through memristor by the 13rd pin of resistance Rx1 connection by the 7th pin of resistance R3 connection, the 7th pin
Device Ry1 connects the 13rd pin of operational amplifier U2, and the 7th pin is directly connected to the 1st pin of multiplier U4, and the 13rd pin passes through electricity
The 14th pin of Rx connection is hindered, the 14th pin passes through the 2nd pin of resistance R1 connection；
The 1st pin, the 2nd pin, the 6th pin, the 7th pin floating of the operational amplifier U2, the 3rd pin, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 8th pin connects the 13rd by resistance Ry2
Pin connects the 13rd pin of operational amplifier U1 by resistance Rx2, connects the 9th pin by capacitor Cy, the 8th pin is directly connected to
The 1st pin of multiplier U5 and the 3rd pin, the 13rd pin pass through resistance RyThe 14th pin is connect, the 14th pin is connect by resistance R4
9th pin；
The 1st pin of the operational amplifier U3 connects the 2nd pin by capacitor Cz, connects the 6th pin by resistance R6, and the 1st
Pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin connects
VCC, the 11st pin meet VEE, the 8th pin, the 9th pin floating, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin passes through
Resistance Rz2 connects the 13rd pin, and the 13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
The 7th pin of the 1st pin connection operational amplifier U1 of the multiplier U4, the 2nd pin, the 4th pin, the 6th are drawn
Foot ground connection, the 3rd pin connect the 1st pin of operational amplifier U3, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin passes through
Resistance Ry3 connects the 13rd pin of operational amplifier U2；
1st pin of the 1st pin of the multiplier U5 and the 3rd pin connection operational amplifier U1, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 8th pin meets VCC, and the 7th pin connects the of operational amplifier U3 by resistance Rz1
13 pins；
The 1st pin, the 2nd pin, the 3rd pin floating of the operational amplifier U6, the 4th pin meet VEE, and the 5th pin connects
Ground, the 6th pin connect the 7th pin by capacitor C4, and by the 7th pin of resistance R8 connection operational amplifier U1, the 7th pin is direct
The 1st pin and the 3rd pin of multiplier U7 are connected, the 8th pin meets VCC；
7th pin of the 1st pin of the multiplier U7 and the 3rd pin connection operational amplifier U6, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
The 1st pin of the multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by resistance R10 and
The 7th pin of series connection of resistance R9, the 1st pin are directly connected to the 7th pin of operational amplifier U1, the 2nd pin, the 4th pin,
6 pins ground connection, the 5th pin meet VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin connects
VCC。
The utility model has the advantages that the present invention on the basis of Lu type chaos system containing the side y, is increased one-dimensional using a memristor element
Four-dimensional hyperchaotic system is constituted, the new method that memristor is applied to hyperchaotic system is proposed.
Detailed description of the invention
Fig. 1 is the schematic diagram of circuit connection structure of the preferred embodiment of the present invention.
Fig. 2 is to realize to recall the practical connection figure of circuit for leading device in the present invention.
Fig. 3 is the practical connection figure of circuit of operational amplifier U1.
Fig. 4 is the practical connection figure of circuit of multiplier U4 and operational amplifier U2.
Fig. 5 is the practical connection figure of circuit of multiplier U5 and operational amplifier U3.
Specific embodiment
The present invention is further described in detail with preferred embodiment with reference to the accompanying drawing, referring to Fig. 1-Fig. 5.
1. the construction method of the Lu type hyperchaotic system containing the side y based on memristor, which is characterized in that including following step
It is rapid:
(1) the Lu type chaos system i containing the side y are as follows:
X in formula, y, z are state variable；
(2) memristor that the present invention uses is magnetic control memristor model ii are as follows:
WhereinIndicate magnetic control memristor,Indicate magnetic flux, m, n are greater than zero parameter；
(3) the magnetic control memristor model derivation of ii must be recalled and leads device model iii are as follows:
It indicates that magnetic control is recalled to lead, m, n are greater than zero parameter；
(4) magnetic control is recalled and leads device model iii as unidimensional system variable, be added in second of the Lu type chaos system containing the side y
On equation, a kind of Lu type hyperchaotic system iv containing the side y based on memristor is obtained:
X in formula, y, z, u are state variable, parameter value a=36, b=3, c=20, m=6, n=0.004, k=2；
(5) based on system iv construction circuit, using operational amplifier U1, operational amplifier U2, operational amplifier U3 and
Resistance, capacitor realize addition, reverse phase and integral operation, using the multiplying in multiplier U4 and multiplier U5 realization system,
The memristor model in the present invention is realized using operational amplifier U6 and multiplier U7, multiplier U8 and capacitor, and the operation is put
Big device U6 connection operational amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connection multiplier U8, multiplier U8 connection
Operational amplifier U2, described operational amplifier U1, U2 and U3 use LF347BN, and described multiplier U4, U5, U7 and U8 are used
AD633JN, the operational amplifier U6 use LF353N；
The 1st pin of the operational amplifier U1 is by the 2nd pin of capacitor Cx connection, by the 6th pin of resistance R2 connection,
3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 8th pin, the 9th
Pin floating, the 6th pin pass through memristor by the 13rd pin of resistance Rx1 connection by the 7th pin of resistance R3 connection, the 7th pin
Device Ry1 connects the 13rd pin of operational amplifier U2, and the 7th pin is directly connected to the 1st pin of multiplier U4, and the 13rd pin passes through electricity
The 14th pin of Rx connection is hindered, the 14th pin passes through the 2nd pin of resistance R1 connection；
The 1st pin, the 2nd pin, the 6th pin, the 7th pin floating of the operational amplifier U2, the 3rd pin, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 8th pin connects the 13rd by resistance Ry2
Pin connects the 13rd pin of operational amplifier U1 by resistance Rx2, connects the 9th pin by capacitor Cy, the 8th pin is directly connected to
The 1st pin of multiplier U5 and the 3rd pin, the 13rd pin connect the 14th pin by resistance Ry, and the 14th pin is connect by resistance R4
9th pin；
The 1st pin of the operational amplifier U3 connects the 2nd pin by capacitor Cz, connects the 6th pin by resistance R6, and the 1st
Pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin connects
VCC, the 11st pin meet VEE, the 8th pin, the 9th pin floating, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin passes through
Resistance Rz2 connects the 13rd pin, and the 13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
The 7th pin of the 1st pin connection operational amplifier U1 of the multiplier U4, the 2nd pin, the 4th pin, the 6th are drawn
Foot ground connection, the 3rd pin connect the 1st pin of operational amplifier U3, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin passes through
Resistance Ry3 connects the 13rd pin of operational amplifier U2；
1st pin of the 1st pin of the multiplier U5 and the 3rd pin connection operational amplifier U1, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 8th pin meets VCC, and the 7th pin connects the of operational amplifier U3 by resistance Rz1
13 pins；
The 1st pin, the 2nd pin, the 3rd pin floating of the operational amplifier U6, the 4th pin meet VEE, and the 5th pin connects
Ground, the 6th pin connect the 7th pin by capacitor C4, and by the 7th pin of resistance R8 connection operational amplifier U1, the 7th pin is direct
The 1st pin and the 3rd pin of multiplier U7 are connected, the 8th pin meets VCC；
7th pin of the 1st pin of the multiplier U7 and the 3rd pin connection operational amplifier U6, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
The 1st pin of the multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by resistance R10 and
The 7th pin of series connection of resistance R9, the 1st pin are directly connected to the 7th pin of operational amplifier U1, the 2nd pin, the 4th pin,
6 pins ground connection, the 5th pin meet VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin connects
VCC。
2. the Lu type hyperchaotic system circuit containing the side y based on memristor, which is characterized in that using operational amplifier U1,
Operational amplifier U2, operational amplifier U3 and resistance, capacitor realize addition, reverse phase and integral operation, using multiplier U4 and multiply
Multiplying in musical instruments used in a Buddhist or Taoist mass U5 realization system is realized in the present invention using operational amplifier U6 and multiplier U7 and multiplier U8
Memristor model, operational amplifier U1 connection operational amplifier U2, operational amplifier U6 and multiplier U4, multiplier U5, multiplication
Device U8, operational amplifier U2 connection operational amplifier U3 and multiplier U4, operational amplifier U3 connection multiplier U5, operation amplifier
Device U6 connection multiplier U7 and multiplier U8, multiplier U7 connection multiplier U8, described operational amplifier U1, U2 and U3 are used
LF347BN, described multiplier U4, U5, U7 and U8 use AD633JN, the operational amplifier U6 to use LF353N；
The 1st pin of the operational amplifier U1 is by the 2nd pin of capacitor Cx connection, by the 6th pin of resistance R2 connection,
3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 8th pin, the 9th
Pin floating, the 6th pin pass through memristor by the 13rd pin of resistance Rx1 connection by the 7th pin of resistance R3 connection, the 7th pin
Device Ry1 connects the 13rd pin of operational amplifier U2, and the 7th pin is directly connected to the 1st pin of multiplier U4, and the 13rd pin passes through electricity
The 14th pin of Rx connection is hindered, the 14th pin passes through the 2nd pin of resistance R1 connection；
The 1st pin, the 2nd pin, the 6th pin, the 7th pin floating of the operational amplifier U2, the 3rd pin, the 5th are drawn
Foot, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 8th pin connects the 13rd by resistance Ry2
Pin connects the 13rd pin of operational amplifier U1 by resistance Rx2, connects the 9th pin by capacitor Cy, the 8th pin is directly connected to
The 1st pin of multiplier U5 and the 3rd pin, the 13rd pin connect the 14th pin by resistance Ry, and the 14th pin is connect by resistance R4
9th pin；
The 1st pin of the operational amplifier U3 connects the 2nd pin by capacitor Cz, connects the 6th pin by resistance R6, and the 1st
Pin is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, and the 4th pin connects
VCC, the 11st pin meet VEE, the 8th pin, the 9th pin floating, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin passes through
Resistance Rz2 connects the 13rd pin, and the 13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
The 7th pin of the 1st pin connection operational amplifier U1 of the multiplier U4, the 2nd pin, the 4th pin, the 6th are drawn
Foot ground connection, the 3rd pin connect the 1st pin of operational amplifier U3, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin passes through
Resistance Ry3 connects the 13rd pin of operational amplifier U2；
1st pin of the 1st pin of the multiplier U5 and the 3rd pin connection operational amplifier U1, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 8th pin meets VCC, and the 7th pin connects the of operational amplifier U3 by resistance Rz1
13 pins；
The 1st pin, the 2nd pin, the 3rd pin floating of the operational amplifier U6, the 4th pin meet VEE, and the 5th pin connects
Ground, the 6th pin connect the 7th pin by capacitor C4, and by the 7th pin of resistance R8 connection operational amplifier U1, the 7th pin is direct
The 1st pin and the 3rd pin of multiplier U7 are connected, the 8th pin meets VCC；
7th pin of the 1st pin of the multiplier U7 and the 3rd pin connection operational amplifier U6, the 2nd pin, the 4th are drawn
Foot, the 6th pin ground connection, the 5th pin meet VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
The 1st pin of the multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, by resistance R10 and
The 7th pin of series connection of resistance R9, the 1st pin are directly connected to the 7th pin of operational amplifier U1, the 2nd pin, the 4th pin,
6 pins ground connection, the 5th pin meet VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin connects
VCC。
Certainly, above description is not limitation to invention, and the present invention is also not limited to the example above, the art it is general
The variations, modifications, additions or substitutions that logical technical staff is made within the essential scope of the present invention also belong to protection of the invention
Range.
Claims (1)
1. the construction method of the Lu type hyperchaotic system containing the side y based on memristor, which comprises the following steps:
(1) the Lu type chaos system i containing the side y are as follows:
X in formula, y, z are state variable；
(2) memristor that the present invention uses is magnetic control memristor model ii are as follows:
WhereinIndicate magnetic control memristor,Indicate magnetic flux, m, n are greater than zero parameter；
(3) the magnetic control memristor model derivation of ii must be recalled and leads device model iii are as follows:
It indicates that magnetic control is recalled to lead, m, n are greater than zero parameter；
(4) magnetic control is recalled and leads device model iii as unidimensional system variable, be added in the second equation of the Lu type chaos system containing the side y
On, obtain a kind of Lu type hyperchaotic system iv containing the side y based on memristor:
X in formula, y, z, u are state variable, parameter value a=36, b=3, c=20, m=6, n=0.004, k=2；
(5) based on system iv construction circuit, using operational amplifier U1, operational amplifier U2, operational amplifier U3 and resistance,
Capacitor realizes that addition, reverse phase and integral operation utilize fortune using the multiplying in multiplier U4 and multiplier U5 realization system
Calculate the memristor model in amplifier U6 and multiplier U7, multiplier U8 and the capacitor realization present invention, the operational amplifier U6
Operational amplifier U1 and multiplier U7 and multiplier U8, multiplier U7 connection multiplier U8 are connected, multiplier U8 connection operation is put
Big device U2, described operational amplifier U1, U2 and U3 use LF347BN, and described multiplier U4, U5, U7 and U8 use AD633JN,
The operational amplifier U6 uses LF353N；
The 1st pin of the operational amplifier U1 is by the 2nd pin of capacitor Cx connection, by the 6th pin of resistance R2 connection, the 3rd
Pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin connects VEE, the 8th pin, the 9th pin
Vacantly, the 6th pin passes through memristor by the 13rd pin of resistance Rx1 connection by the 7th pin of resistance R3 connection, the 7th pin
Ry1 connects the 13rd pin of operational amplifier U2, and the 7th pin is directly connected to the 1st pin of multiplier U4, and the 13rd pin passes through resistance
The 14th pin of Rx connection, the 14th pin pass through the 2nd pin of resistance R1 connection；
The 1st pin, the 2nd pin, the 6th pin, the 7th pin floating of the operational amplifier U2, the 3rd pin, the 5th pin,
10 pins, the 12nd pin ground connection, the 4th pin meet VCC, and the 11st pin meets VEE, and the 8th pin connects the 13rd pin by resistance Ry2,
The 13rd pin that operational amplifier U1 is met by resistance Rx2 connects the 9th pin by capacitor Cy, and the 8th pin is directly connected to multiplier
The 1st pin of U5 and the 3rd pin, the 13rd pin connect the 14th pin by resistance Ry, and the 14th pin connects the 9th by resistance R4 and draws
Foot；
The 1st pin of the operational amplifier U3 connects the 2nd pin by capacitor Cz, connects the 6th pin, the 1st pin by resistance R6
It is directly connected to the 3rd pin of multiplier U4, the 3rd pin, the 5th pin, the 10th pin, the 12nd pin ground connection, the 4th pin meets VCC,
11st pin meets VEE, the 8th pin, the 9th pin floating, and the 6th pin connects the 7th pin by resistance R7, and the 7th pin passes through resistance
Rz2 connects the 13rd pin, and the 13rd pin connects the 14th pin by resistance Rz, and the 14th pin connects the 2nd pin by resistance R5；
The 7th pin of the 1st pin connection operational amplifier U1 of the multiplier U4, the 2nd pin, the 4th pin, the 6th pin connect
Ground, the 3rd pin connect the 1st pin of operational amplifier U3, and the 5th pin meets VEE, and the 8th pin meets VCC, and the 7th pin passes through resistance
Ry3 connects the 13rd pin of operational amplifier U2；
The 1st pin of the multiplier U5 and the 3rd pin connection operational amplifier U1 the 1st pin, the 2nd pin, the 4th pin,
6th pin ground connection, the 5th pin meet VEE, and the 8th pin meets VCC, and the 7th pin connects the 13rd of operational amplifier U3 by resistance Rz1
Pin,
The 1st pin, the 2nd pin, the 3rd pin floating of the operational amplifier U6, the 4th pin meet VEE, and the 5th pin is grounded, the
6 pins connect the 7th pin by capacitor C4, and by the 7th pin of resistance R8 connection operational amplifier U1, the 7th pin is directly connected to
The 1st pin of multiplier U7 and the 3rd pin, the 8th pin meet VCC；
The 1st pin of the multiplier U7 and the 3rd pin connection operational amplifier U6 the 7th pin, the 2nd pin, the 4th pin,
6th pin ground connection, the 5th pin meet VEE, and the 7th pin connects the 3rd pin of multiplier U8, and the 8th pin meets VCC；
The 1st pin of the multiplier U8 connects the 6th pin of operational amplifier U6 by resistance R8, passes through resistance R10 and resistance
The 7th pin of series connection of R9, the 1st pin are directly connected to the 7th pin of operational amplifier U1, and the 2nd pin, the 4th pin, the 6th are drawn
Foot ground connection, the 5th pin meet VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R9, and the 8th pin meets VCC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN111162769B (en) * | 2019-12-03 | 2023-07-25 | 湘潭大学 | Hyperbolic tangent memristor Duffing chaotic model and circuit |
| CN112134680B (en) * | 2020-08-14 | 2021-10-29 | 中国地质大学（武汉） | Chaotic circuit based on magnetic control memristor |
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| CN202998051U (en) * | 2012-12-27 | 2013-06-12 | 西南大学 | Memristor-based hyperchaotic-system realization circuit |
| CN104009748A (en) * | 2014-06-13 | 2014-08-27 | 西南大学 | Memristor hyperchaos system and circuit with abundant dynamic behaviors |
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| CN203872185U (en) * | 2014-03-17 | 2014-10-08 | 邢台学院 | Lorenz-type chaotic switching system circuit with square of y and different fractional orders |
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| CN202998051U (en) * | 2012-12-27 | 2013-06-12 | 西南大学 | Memristor-based hyperchaotic-system realization circuit |
| CN104009748A (en) * | 2014-06-13 | 2014-08-27 | 西南大学 | Memristor hyperchaos system and circuit with abundant dynamic behaviors |
Non-Patent Citations (1)
| Title |
|---|
| Memristor Based Chaotic Circuits;Bharathwaj Muthuswamy等;《IETF technical review》;20091130;第26卷(第6期);全文 |
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| CN105577358A (en) | 2016-05-11 |
| CN104468081B (en) | 2016-05-04 |
| CN104468081B8 (en) | 2016-06-08 |
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