CN202043091U - Artificial circuit capable of realizing automatic switching of chaos systems - Google Patents
Artificial circuit capable of realizing automatic switching of chaos systems Download PDFInfo
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- CN202043091U CN202043091U CN 201120116237 CN201120116237U CN202043091U CN 202043091 U CN202043091 U CN 202043091U CN 201120116237 CN201120116237 CN 201120116237 CN 201120116237 U CN201120116237 U CN 201120116237U CN 202043091 U CN202043091 U CN 202043091U
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Abstract
The utility model relates to a circuit capable of switching chaos systems, in particular to a circuit utilizing an artificial circuit to realize the automatic switching of the chaos systems, which comprises an automatic switching system formed by two chaos systems. The artificial circuit is utilized to realize the automatic switching of the chaos systems, thereby proving the existence of the switching chaos system more effectively. The switching system can be applied in confidential communications based on chaos synchronization, thereby enhancing the safety of the chaos synchronization confidential communications. Furthermore, the switching system can be further applied in chaos communications based on keying technologies, thereby leading the switch between systems to be more flexible and convenient. Therefore, the artificial circuit capable of realizing the automatic switching of the chaos systems has a wider application prospect.
Description
Technical field
The utility model relates to a kind of analog circuit that chaos system is realized, particularly a kind of analog circuit of realizing automatically switched chaotic system of switching.
Background technology
Realize in the chaos system circuit document more report being arranged with analog circuit, realize in the switching chaos system circuit document report being arranged also with digital circuit (as FPGA), but realize that with analog circuit the automatically switched chaotic system circuit does not appear in the newspapers, because analog circuit more can effectively prove the existence of chaos system than digital circuit, therefore, circuit with analog circuit realization automatically switched chaotic system of design seems particularly necessary.
Summary of the invention
Problem to be solved in the utility model provides a circuit that utilizes analog circuit to realize automatically switched chaotic system.The technical solution of the utility model is as follows:
The analog circuit of the automatically switched chaotic system that the utility model relates to, comprise operational amplifier U1, described operational amplifier U1 connects output interface P1, operational amplifier U3, analog multiplexer U6, described analog multiplexer U6 concatenation operation amplifier U3, comparator U7, multiplier U4, described operational amplifier U3 connects output interface P3, multiplier U5, operational amplifier U2, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connects output interface P2.
As further qualification to the technical program, the pin 1 of described operational amplifier U1 connects the pin 13 of described operational amplifier U1 by resistance R 4, described pin 1 is also by resistance R 3 simultaneously, deflection machine R1 is connected to the pin 8 of described operational amplifier U1, described resistance R 3 also is connected to output interface P3 by deflection machine R2, described resistance R 3 one ends connect the pin 2 of described operational amplifier U1, described operational amplifier pin 3 ground connection, described operational amplifier U1 pin 4 connects positive supply, described operational amplifier U1 pin 5,6,7 put sky, pin 8 connects pin 9 by resistance R 6, pin 9 connects output interface P1 by resistance R 5, pin 10,12 ground connection, pin 11 connects negative supply, and pin 13 connects output interface P1 by capacitor C 1, and pin 14 connects output interface P1.
As further qualification to the technical program, the pin 1 of described operational amplifier U2 connects pin 13 by resistance R 10, pin 1 also connects pin 2 by resistance R 9, the other end of resistance R 9 connects pin 7 by deflection machine R7, simultaneously, resistance R 9 also connects output interface P1 by deflection machine R8, pin 3,5,10,12 ground connection, pin 4 connects positive supply, and pin 11 connects negative supply, pin 6 connects multiplier U4 pin 7 by resistance R 20, pin 7 connects resistance R 20 by resistance R 21, and pin 8 connects pin 9 by resistance R 12, and pin 9 connects output interface P2 by resistance R 11, pin 13 connects output interface P2 by capacitor C 2, and pin 14 connects output interface P2.
As further qualification to the technical program, described operational amplifier U3 pin 1 connects pin 13 by resistance R 17, pin 1 connects pin 2 by resistance R 16, resistance R 16 connects the pin 7 of multiplier U5 by transformer R13, resistance R 16 also connects pin 8 by deflection machine R14, resistance R 16 also connects the pin 8 of described operational amplifier U2 by deflection machine 15, pin 3,10,12 ground connection, pin 4 connects positive supply, and pin 11 connects negative supply, pin 5,6,7 put sky, pin 8 connects pin 9 by resistance R 19, pin 9 connects output interface P3 by resistance R 18, and pin 13 connects output interface P3 by capacitor C 3, and pin 14 connects output interface P3.
As the further qualification to the technical program, described multiplier U4 pin 1 is connected the pin 8 of analog multiplexer U6 with 3, pin 2,4,6 ground connection, and pin 5 connects negative supply, and pin 8 connects positive supply.
As the further qualification to the technical program, described multiplier U5 pin 1 connects output interface P1, pin 2,4,6 ground connection, and pin 3 connects output interface P2, and pin 5 connects negative supply, and pin 8 connects positive supply.
As further qualification to the technical program, described analog multiplexer U6 pin 1 connects the pin 1 of comparator U7, pin 2 connects positive supply, pin 3 connects negative supply, and pin 4 connects output interface P1, and pin 5 connects output interface P3, pin 6,7,9,10,11,12,13 is put sky, pin 8 connects the pin 1 of described multiplier U4, and described pin 14 connects positive supply, pin 15,16 ground connection.
As further qualification to the technical program, described comparator U7 pin 1 connects the pin 1 of described plan multiplexer U6, pin 2 is by diode D1, resistance R 23 ground connection, pin 1 also connects positive supply by resistance 22, pin 3 connects power supply VCC, pin 4,12 ground connection, pin 5 connects described transformer R2, and pin 6,7,8,9,10,11,13,14 is put sky.
Compared with prior art, advantage of the present utility model and good effect are: the utility model utilizes analog circuit to realize the automatic switchover of two chaos systems, proved the existence of chaos system more accurately, this automatic switchover system is used for based on the synchronous secure communication of chaos, can strengthen the fail safe of the synchronous secure communication of chaos, be used for chaotic communication based on key control technology, can make the switching between system more flexible, therefore, this automatically switched chaotic system has wider application prospect.
Description of drawings
Fig. 1 is the circuit connection structure schematic diagram of the utility model preferred embodiment.
Fig. 2 is an operational amplifier U1 peripheral circuit structural representation.
Fig. 3 is an operational amplifier U2 peripheral circuit structural representation.
Fig. 4 is an operational amplifier U3 peripheral circuit structural representation.
Fig. 5 is a multiplier U4 peripheral circuit structural representation.
Fig. 6 is a multiplier U5 peripheral circuit structural representation.
Fig. 7 is an analog multiplexer U6 peripheral circuit structural representation.
Fig. 8 is a comparator U7 peripheral circuit structural representation.
Embodiment
Below in conjunction with accompanying drawing and preferred embodiment the utility model is done further to describe in detail.
At first construct automatically switched chaotic system, the chaos system (a) that this preferred embodiment is selected is:
The another one chaos system of selecting (b) is:
Construct a choice function system (c) with chaos system (a) with (b) form one and switch chaos system (d):
Under the parameter condition identical, as Z with system (a) and (b) 〉=0 the time, system (d) operational system (a), when Z＜0, system (d) operational system (b).
Utilize above-mentioned formula (C), (d) constructing analog circuit, comprise operational amplifier U1, described operational amplifier U1 connects output interface P1, operational amplifier U3, analog multiplexer U6, described analog multiplexer U6 concatenation operation amplifier U3, comparator U7, multiplier U4, described operational amplifier U3 connects output interface P3, multiplier U5, operational amplifier U2, described multiplier U4 concatenation operation amplifier U2, described operational amplifier U2 connects output interface P2.
The pin 1 of described operational amplifier U1 connects the pin 13 of described operational amplifier U1 by resistance R 4, described pin 1 is also by resistance R 3 simultaneously, deflection machine R1 is connected to the pin 8 of described operational amplifier U1, described resistance R 3 also is connected to output interface P3 by deflection machine R2, described resistance R 3 one ends connect the pin 2 of described operational amplifier U1, described operational amplifier pin 3 ground connection, described operational amplifier U1 pin 4 connects positive supply, described operational amplifier U1 pin 5,6,7 put sky, pin 8 connects pin 9 by resistance R 6, pin 9 connects output interface P1 by resistance R 5, pin 10,12 ground connection, pin 11 connects negative supply, pin 13 connects output interface P1 by capacitor C 1, and pin 14 connects output interface P1.
The pin 1 of described operational amplifier U2 connects pin 13 by resistance R 10, pin 1 also connects pin 2 by resistance R 9, the other end of resistance R 9 connects pin 7 by deflection machine R7, simultaneously, resistance R 9 also connects output interface P1 by deflection machine R8, pin 3,5,10,12 ground connection, pin 4 connects positive supply, pin 11 connects negative supply, and pin 6 connects multiplier U4 pin 7 by resistance R 20, and pin 7 connects resistance R 20 by resistance R 21, pin 8 connects pin 9 by resistance R 12, pin 9 connects output interface P2 by resistance R 11, and pin 13 connects output interface P2 by capacitor C 2, and pin 14 connects output interface P2.
Described operational amplifier U3 pin 1 connects pin 13 by resistance R 17, pin 1 connects pin 2 by resistance R 16, resistance R 16 connects the pin 7 of multiplier U5 by transformer R13, resistance R 16 also connects pin 8 by deflection machine R14, resistance R 16 also connects the pin 8 of described operational amplifier U2 by deflection machine 15, pin 3,10,12 ground connection, pin 4 connects positive supply, pin 11 connects negative supply, pin 5,6,7 put sky, and pin 8 connects pin 9 by resistance R 19, and pin 9 connects output interface P3 by resistance R 18, pin 13 connects output interface P3 by capacitor C 3, and pin 14 connects output interface P3.
Operational amplifier U1, U2, U3 adopt LF347, and each contains four identical integrated operational amplifier circuits, and each contains-,+two inputs and out output are used for forming addition, anti-phase (negate) and integral operation in this circuit.
Described multiplier U4 pin 1 is connected the pin 8 of analog multiplexer U6 with 3, pin 2,4,6 ground connection, and pin 5 connects negative supply, and pin 8 connects positive supply.
Described multiplier U5 pin 1 connects output interface P1, pin 2,4,6 ground connection, and pin 3 connects output interface P2, and pin 5 connects negative supply, and pin 8 connects positive supply.
Multiplier U4, U5 adopt AD633JN, are used for realizing multiplying in this circuit, have only used input pin 1,4 and output pin 7.
Described analog multiplexer U6 pin 1 connects the pin 1 of comparator U7, pin 2 connects positive supply, pin 3 connects negative supply, pin 4 connects output interface P1, pin 5 connects output interface P3, and pin 6,7,9,10,11,12,13 is put sky, and pin 8 connects the pin 1 of described multiplier U4, described pin 14 connects positive supply, pin 15,16 ground connection.
Described comparator U7 pin 1 connects the pin 1 of described plan multiplexer U6, pin 2 is by diode D1, resistance R 23 ground connection, pin 1 also connects positive supply by resistance 22, pin 3 connects power supply VCC, pin 4,12 ground connection, pin 5 connects described transformer R2, and pin 6,7,8,9,10,11,13,14 is put sky.Comparator U7 adopts LM139, and according to input signal, the decision output signal is high level or low level, as pin 5 input signal Zout〉0 the time, pin 2 is output as high level; When the input signal Zout of pin 5＜0, the output signal of pin 2 is a low level.
Certainly; above-mentioned explanation is not to restriction of the present utility model; the utility model also is not limited only to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present utility model also belong to protection range of the present utility model.
Claims (8)
1. the analog circuit of an automatically switched chaotic system, it is characterized in that, comprise operational amplifier U1, described operational amplifier U1 connects output interface P1, operational amplifier U3, analog multiplexer U6, described analog multiplexer U6 concatenation operation amplifier U3, comparator U7, multiplier U4, described operational amplifier U3 connects output interface P3, multiplier U5, operational amplifier U2, described multiplier U4 concatenation operation amplifier U2, and described operational amplifier U2 connects output interface P2.
2. the analog circuit of realization automatically switched chaotic system according to claim 1, it is characterized in that, the pin 1 of described operational amplifier U1 connects the pin 13 of described operational amplifier U1 by resistance R 4, described pin 1 is also by resistance R 3 simultaneously, deflection machine R1 is connected to the pin 8 of described operational amplifier U1, described resistance R 3 also is connected to output interface P3 by deflection machine R2, described resistance R 3 one ends connect the pin 2 of described operational amplifier U1, described operational amplifier pin 3 ground connection, described operational amplifier U1 pin 4 connects positive supply, described operational amplifier U1 pin 5,6,7 put sky, pin 8 connects pin 9 by resistance R 6, pin 9 connects output interface P1, pin 10 by resistance R 5,12 ground connection, pin 11 connects negative supply, pin 13 connects output interface P1 by capacitor C 1, and pin 14 connects output interface P1.
3. the analog circuit of realization automatically switched chaotic system according to claim 1, it is characterized in that, the pin 1 of described operational amplifier U2 connects pin 13 by resistance R 10, pin 1 also connects pin 2 by resistance R 9, the other end of resistance R 9 connects pin 7 by deflection machine R7, simultaneously, resistance R 9 also connects output interface P1 by deflection machine R8, pin 3,5,10,12 ground connection, pin 4 connects positive supply, pin 11 connects negative supply, and pin 6 connects multiplier U4 pin 7 by resistance R 20, and pin 7 connects resistance R 20 by resistance R 21, pin 8 connects pin 9 by resistance R 12, pin 9 connects output interface P2 by resistance R 11, and pin 13 connects output interface P2 by capacitor C 2, and pin 14 connects output interface P2.
4. the analog circuit of realization automatically switched chaotic system according to claim 1, it is characterized in that, described operational amplifier U3 pin 1 connects pin 13 by resistance R 17, pin 1 connects pin 2 by resistance R 16, resistance R 16 connects the pin 7 of multiplier U5 by transformer R13, resistance R 16 also connects pin 8 by deflection machine R14, resistance R 16 also connects the pin 8 of described operational amplifier U2 by deflection machine 15, pin 3,10,12 ground connection, pin 4 connects positive supply, pin 11 connects negative supply, pin 5,6,7 put sky, and pin 8 connects pin 9 by resistance R 19, and pin 9 connects output interface P3 by resistance R 18, pin 13 connects output interface P3 by capacitor C 3, and pin 14 connects output interface P3.
5. the analog circuit of realization automatically switched chaotic system according to claim 1 is characterized in that, described multiplier U4 pin 1 is connected the pin 8 of analog multiplexer U6 with 3, pin 2,4,6 ground connection, and pin 5 connects negative supply, and pin 8 connects positive supply.
6. the analog circuit of realization automatically switched chaotic system according to claim 1 is characterized in that, described multiplier U5 pin 1 connects output interface P1, pin 2,4,6 ground connection, pin 3 connects output interface P2, and pin 5 connects negative supply, and pin 8 connects positive supply.
7. the analog circuit of realization automatically switched chaotic system according to claim 1, it is characterized in that, described analog multiplexer U6 pin 1 connects the pin 1 of comparator U7, and pin 2 connects positive supply, and pin 3 connects negative supply, pin 4 connects output interface P1, pin 5 connects output interface P3, and pin 6,7,9,10,11,12,13 is put sky, and pin 8 connects the pin 1 of described multiplier U4, described pin 14 connects positive supply, pin 15,16 ground connection.
8. the analog circuit of realization automatically switched chaotic system according to claim 1, it is characterized in that, described comparator U7 pin 1 connects the pin 1 of described plan multiplexer U6, pin 2 is by diode D1, resistance R 23 ground connection, pin 1 also connects positive supply by resistance 22, and pin 3 connects power supply VCC, pin 4,12 ground connection, pin 5 connects described transformer R2, and pin 6,7,8,9,10,11,13,14 is put sky.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120116237 CN202043091U (en) | 2011-04-19 | 2011-04-19 | Artificial circuit capable of realizing automatic switching of chaos systems |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201120116237 CN202043091U (en) | 2011-04-19 | 2011-04-19 | Artificial circuit capable of realizing automatic switching of chaos systems |
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| CN202043091U true CN202043091U (en) | 2011-11-16 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385659A (en) * | 2011-12-13 | 2012-03-21 | 滨州学院 | Method for realizing fractional-order three-system automatic-switchover chaotic system and analog circuit |
| CN102497263A (en) * | 2011-11-18 | 2012-06-13 | 滨州学院 | Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit |
| CN102904708A (en) * | 2012-09-27 | 2013-01-30 | 滨州学院 | Method for automatically switching fractional-order chaotic system by four systems based on Lu-type system and analog circuit |
| CN102916802A (en) * | 2012-09-27 | 2013-02-06 | 滨州学院 | Fractional-order automatic switching chaotic system method for four Lorenz type systems and analog circuit |
-
2011
- 2011-04-19 CN CN 201120116237 patent/CN202043091U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497263A (en) * | 2011-11-18 | 2012-06-13 | 滨州学院 | Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit |
| WO2013071689A1 (en) * | 2011-11-18 | 2013-05-23 | Wang Zhonglin | Method and analog circuit for implementing automatic switching of chaotic systems of integer order and fractional order |
| CN102497263B (en) * | 2011-11-18 | 2014-06-04 | 滨州学院 | Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit |
| CN102385659A (en) * | 2011-12-13 | 2012-03-21 | 滨州学院 | Method for realizing fractional-order three-system automatic-switchover chaotic system and analog circuit |
| CN102385659B (en) * | 2011-12-13 | 2012-11-28 | 滨州学院 | Method for realizing fractional-order three-system automatic-switchover chaotic system and analog circuit |
| WO2013086777A1 (en) * | 2011-12-13 | 2013-06-20 | Wang Zhonglin | Method for implementing fractional three-system automatic switching chaotic system, and analog circuit |
| CN102904708A (en) * | 2012-09-27 | 2013-01-30 | 滨州学院 | Method for automatically switching fractional-order chaotic system by four systems based on Lu-type system and analog circuit |
| CN102916802A (en) * | 2012-09-27 | 2013-02-06 | 滨州学院 | Fractional-order automatic switching chaotic system method for four Lorenz type systems and analog circuit |
| WO2014048053A1 (en) * | 2012-09-27 | 2014-04-03 | Wang Zhonglin | Analog circuit and method for fractional-order four-system automatic switching chaotic system based on lorenz type system |
| CN102904708B (en) * | 2012-09-27 | 2014-09-10 | 滨州学院 | Method for automatically switching fractional-order chaotic system by four systems based on Lu-type system and analog circuit |
| CN102916802B (en) * | 2012-09-27 | 2014-12-17 | 滨州学院 | Fractional-order automatic switching chaotic system method for four Lorenz type systems and analog circuit |
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| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111116 Termination date: 20120419 |