CN102497263A - Method for realizing integer order and fractional order automatic switching chaotic system and analog circuit - Google Patents

Abstract

The invention discloses a construction of an integer order and fractional order automatic switching chaotic system and an analog circuit realization method. The construction comprises an automatic switching system which is formed by an integer order chaotic system and a fractional order chaotic system, and the automatic switching system is realized by utilizing an analog circuit. According to the invention, automatic switching of the integer order chaotic system and the fractional order chaotic system is realized by utilizing the analog circuit, the integer order and fractional order automatic switching chaotic system is more complex than the integer order chaotic system, the fractional order chaotic system and the automatic switching system, and superiority of the above three systems are concentrated. The system provided by the invention has an important meaning in secret communication based on chaos and signal detection and has good application prospect.

Description

A kind of method and analog circuit of realizing integer rank and fractional order automatically switched chaotic system

Technical field

The present invention relates to a kind of method of utilizing Realization of Analog Circuit integer rank and fractional order automatically switched chaotic system, specifically, relate to a kind of method and analog circuit of realizing integer rank and fractional order automatically switched chaotic system.

Background technology

In the method document with Realization of Analog Circuit integer rank chaos system more report is arranged; In the method document with Realization of Analog Circuit fractional order chaos system report is arranged also; Method and the circuit document of realizing automatically switched chaotic system also have report; But automatically switched chaotic system method and circuit with Realization of Analog Circuit integer rank and fractional order do not appear in the newspapers, because the integer rank are all more complicated than integer rank chaos system, fractional order chaos system and automatic switchover system with the chaos system that fractional order automaticallyes switch, have concentrated three's superiority; Therefore; Propose the method for designing of a kind of integer rank and fractional order automatically switched chaotic system, and with this chaos system of Realization of Analog Circuit, have great importance for the application of this chaos system.

Summary of the invention

The technical problem that the present invention will solve provides the method and the analog circuit of a kind of integer rank and fractional order automatically switched chaotic system.

The present invention adopts following technological means to realize goal of the invention:

1, a kind of method that realizes integer rank and fractional order automatically switched chaotic system is characterized in that being, may further comprise the steps:

(1) according to integer rank chaos system i be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dx}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dx}/\mathrm{dt}=x^2-\mathrm{hz}\end{array}\right.$ i a＝20，b＝14，c＝10.6，h＝2.8

(2) according to fractional order chaos system ii be:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=x^2-\mathrm{hz}\end{array}\right.$ ii 0＜q＜1，a＝20，b＝14，c＝10.6，h＝2.8

(3) iii of choice function system of structure forms new integer rank and fractional order automatically switched chaotic system iv with chaos system i and ii:

$f\left(x\right)=\left\{\begin{array}{cc}q=1& x\&GreaterEqual;0\\ q=0.9& x<0\end{array}\right.$ iii

$\left\{\begin{array}{c}{d}^{f\left(x\right)}x/{\mathrm{dt}}^{f\left(x\right)}=a(y-x)\\ d^{f\left(x\right)}y/{\mathrm{dt}}^{f\left(x\right)}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{f\left(x\right)}z/{\mathrm{dt}}^{f\left(x\right)}=x^2-\mathrm{hz}\end{array}\right.$ iv

(4) according to chaos system iii and iv constructing analog Circuits System; Utilize voltage comparator U6 to obtain the high-low level of simulation; X＞=0 and x＜0; As the input of choice function, utilize analog switch U7 and U8 to realize the alternately output of integer rank integration and fractional order integration, utilize operational amplifier U1, U2, U3 and multiplier U4, U5 to obtain the analog circuit of integer rank and mark automatically switched chaotic system.Said operational amplifier U1, U2, U3 adopt LF347, and multiplier U4, U5 adopt AD633JN,, voltage comparator U6 adopts LM339, and analog switch U7, U8 adopt CD4052;

Said operational amplifier U1 connects voltage comparator U6; Analog switch U7, U8, multiplier U4, U5, said voltage comparator U6 connects analog switch U7, U8; Said multiplier U4 concatenation operation amplifier U2; Said operational amplifier U2 connects analog switch U7, said multiplier U5 concatenation operation amplifier U3, and said operational amplifier U3 connects analog switch U8;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, joins through the 6th pin of resistance R 1 with U1, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc11 of the 6th pin elder generation and capacitor C 11 parallelly connected, connects the parallelly connected of Rc12 and capacitor C 12 again, connect Rc13 and capacitor C 13 parallelly connected again after; Join with U7 the 4th pin, join through the 5th pin of capacitor C 10 with U7, the 9th pin of the 7th pin and U6 joins; Join with the 1st pin of U4, join with the 9th pin of U7, with the 1st of U5; 3 pins join, and join through resistance R 22 and U2 the 2nd pin, and the 8th pin joins through resistance R 25 and U1 the 9th pin; The 9th pin joins with potentiometer R12 and U1 the 2nd pin through resistance R 24, joins with potentiometer R23 and U2 the 2nd pin through resistance R 24, joins through resistance R 24 and U7 the 10th pin; The 13rd pin joins through resistance R 13 and U1 the 7th pin, joins through resistance R 14 and U1 the 14th pin, joins with the 1st pin of U4; Join with the 8th pin of U7, join with the 1st pin, the 3rd pin of U5, the 14th pin joins through potentiometer R11 and U1 the 2nd pin;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins through the 6th pin of resistance R 2 with U2, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc21 of the 6th pin elder generation and capacitor C 21 parallelly connected, connects the parallelly connected of Rc22 and capacitor C 22 again, connect Rc23 and capacitor C 23 parallelly connected again after; Join with U7 the 13rd pin,, join through the 12nd pin of capacitor C 20 with U7, the 7th pin and U7 the 9th pin join; The 8th pin of the 8th pin and U8 joins, and the connecting resistance Rc33 of the 9th pin elder generation is parallelly connected with capacitor C 33, connects the parallelly connected of Rc32 and capacitor C 32 again; After connecing Rc31 and capacitor C 31 parallelly connected again, join with U8 the 4th pin; Join through the 5th pin of capacitor C 30 with U8, the 13rd pin joins through resistance R 33 and U4 the 3rd pin, joins through resistance R 33 and U8 the 8th pin; Join through resistance R 34 and U2 the 14th pin, the 14th pin connects the 3rd pin of U4, joins through potentiometer R32 and U3 the 2nd pin;

Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 31 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st, 3 pins of said multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st, 2,4,5,6,7,9,10,11,12,13 pins of said voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins through resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, the 14th pin through diode D1 with join with the 1st pin of U7, the 1st pin of U8, meet VCC through resistance R 01;

The 1st pin of said analog switch U7 connects the 8th pin of U6 through resistance R 02, and the 2nd pin meets VCC, and the 3rd pin meets VEE; The 4th pin connects 6 pins of U1 through the fractional order integration unit, and the 5th pin connects 6 pins of U1 through capacitor C 10, and the 8th pin connects 7 pins of U1; The 9th pin connects 7 pins of U2, and the 12nd pin connects 6 pins of U2 through C20, and the 13rd pin connects 6 pins of U2 through the fractional order integration unit; The 14th pin meets VCC, the 15th, 16 pin ground connection;

The 1st pin of said analog switch U8 connects the 8th pin of U6 through resistance R 02; The 2nd pin meets VCC, and the 3rd pin meets VEE, and the 4th pin connects 9 pins of U2 through the fractional order integration unit; The 5th pin connects 9 pins of U2 through capacitor C 30; The 8th pin connects 8 pins of U2, and the 14th pin meets VCC, the 15th, 16 pin ground connection.

2, a kind of circuit of realizing integer rank and fractional order automatically switched chaotic system is characterized in that being, comprises that operational amplifier U1, U2, U3 and multiplier U4, U5 and voltage comparator U6 and analog switch U7, U8 form; Said operational amplifier U1 connects voltage comparator U6; Analog switch U7, U8, multiplier U4, U5, said voltage comparator U6 connects analog switch U7, U8; Said multiplier U4 concatenation operation amplifier U2; Said operational amplifier U2 connects analog switch U7, said multiplier U5 concatenation operation amplifier U3, and said operational amplifier U3 connects analog switch U8;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, joins through the 6th pin of resistance R 1 with U1, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc11 of the 6th pin elder generation and capacitor C 11 parallelly connected, connects the parallelly connected of Rc12 and capacitor C 12 again, connect Rc13 and capacitor C 13 parallelly connected again after; Join with U7 the 4th pin, join through the 5th pin of capacitor C 10 with U7, the 9th pin of the 7th pin and U6 joins; Join with the 1st pin of U4, join with the 9th pin of U7, with the 1st of U5; 3 pins join, and join through resistance R 22 and U2 the 2nd pin, and the 8th pin joins through resistance R 25 and U1 the 9th pin; The 9th pin joins with potentiometer R12 and U1 the 2nd pin through resistance R 24, joins with potentiometer R23 and U2 the 2nd pin through resistance R 24, joins through resistance R 24 and U7 the 10th pin; The 13rd pin joins through resistance R 13 and U1 the 7th pin, joins through resistance R 14 and U1 the 14th pin, joins with the 1st pin of U4; Join with the 8th pin of U7, join with the 1st pin, the 3rd pin of U5, the 14th pin joins through potentiometer R11 and U1 the 2nd pin;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins through the 6th pin of resistance R 2 with U2, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc21 of the 6th pin elder generation and capacitor C 21 parallelly connected, connects the parallelly connected of Rc22 and capacitor C 22 again, connect Rc23 and capacitor C 23 parallelly connected again after; Join with U7 the 13rd pin,, join through the 12nd pin of capacitor C 20 with U7, the 7th pin and U7 the 9th pin join; The 8th pin of the 8th pin and U8 joins, and the connecting resistance Rc33 of the 9th pin elder generation is parallelly connected with capacitor C 33, connects the parallelly connected of Rc32 and capacitor C 32 again; After connecing Rc31 and capacitor C 31 parallelly connected again, join with U8 the 4th pin; Join through the 5th pin of capacitor C 30 with U8, the 13rd pin joins through resistance R 33 and U4 the 3rd pin, joins through resistance R 33 and U8 the 8th pin; Join through resistance R 34 and U2 the 14th pin, the 14th pin connects the 3rd pin of U4, joins through potentiometer R32 and U3 the 2nd pin;

Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 31 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st, 3 pins of said multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st, 2,4,5,6,7,9,10,11,12,13 pins of said voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins through resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, the 14th pin through diode D1 with join with the 1st pin of U7, the 1st pin of U8, meet VCC through resistance R 01;

The 1st pin of said analog switch U7 connects the 8th pin of U6 through resistance R 02, and the 2nd pin meets VCC, and the 3rd pin meets VEE; The 4th pin connects 6 pins of U1 through the fractional order integration unit, and the 5th pin connects 6 pins of U1 through capacitor C 10, and the 8th pin connects 7 pins of U1; The 9th pin connects 7 pins of U2, and the 12nd pin connects 6 pins of U2 through C20, and the 13rd pin connects 6 pins of U2 through the fractional order integration unit; The 14th pin meets VCC, the 15th, 16 pin ground connection;

The 1st pin of said analog switch U8 connects the 8th pin of U6 through resistance R 02; The 2nd pin meets VCC, and the 3rd pin meets VEE, and the 4th pin connects 9 pins of U2 through the fractional order integration unit; The 5th pin connects 9 pins of U2 through capacitor C 30; The 8th pin connects 8 pins of U2, and the 14th pin meets VCC, the 15th, 16 pin ground connection.

Description of drawings

Fig. 1 is the circuit connection structure sketch map of the preferred embodiment of the present invention.

Fig. 2 is an operational amplifier U1 peripheral circuit structural representation.

Fig. 3 is operational amplifier U2 and multiplier U4 peripheral circuit structural representation.

Fig. 4 is operational amplifier U3 and multiplier U5 peripheral circuit structural representation.

Fig. 5 is a voltage comparator U6 peripheral circuit structural representation.

Fig. 6 is the peripheral circuit structural representation of analog switch U7.

Fig. 7 is an analog switch U8 peripheral circuit structural representation.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment the present invention is made detailed description further.

Referring to Fig. 1-Fig. 7, at first construct integer rank and fractional order automatically switched chaotic system, the integer rank chaos system i that this preferred embodiment is selected is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dx}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dx}/\mathrm{dt}=x^2-\mathrm{hz}\end{array}\right.$ a＝20，b＝14，c＝10.6，h＝2.8

The fractional order chaos system ii that selects is:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=x^2-\mathrm{hz}\end{array}\right.$ ii?0＜q＜1，a＝20，b＝14，c＝10.6，h＝2.8

Construct an iii of choice function system, chaos system i and ii formed new integer rank and fractional order automatically switched chaotic system iv:

$f\left(x\right)=\left\{\begin{array}{cc}q=1& x\&GreaterEqual;0\\ q=0.9& x<0\end{array}\right.$ iii

$\left\{\begin{array}{c}{d}^{f\left(x\right)}x/{\mathrm{dt}}^{f\left(x\right)}=a(y-x)\\ d^{f\left(x\right)}y/{\mathrm{dt}}^{f\left(x\right)}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{f\left(x\right)}z/{\mathrm{dt}}^{f\left(x\right)}=x^2-\mathrm{hz}\end{array}\right.$ iv

According to the iii of system and integer rank and fractional order automatically switched chaotic system iv constructing analog circuit; Utilize voltage comparator U6 to obtain the high-low level of simulation; X＞=0 and x＜0; As the input of choice function, utilize analog switch U7 and U8 to realize the alternately output of integer rank integration and fractional order integration, utilize operational amplifier U1, U2, U3 and multiplier U4, U5 to obtain the analog circuit of integer rank and mark automatically switched chaotic system.Said operational amplifier U1, U2, U3 adopt LF347, and multiplier U4, U5 adopt AD633JN,, voltage comparator U6 adopts LM339, and analog switch U7, U8 adopt CD4052;

Said operational amplifier U1 connects voltage comparator U6; Analog switch U7, U8, multiplier U4, U5, said voltage comparator U6 connects analog switch U7, U8; Said multiplier U4 concatenation operation amplifier U2; Said operational amplifier U2 connects analog switch U7, said multiplier U5 concatenation operation amplifier U3, and said operational amplifier U3 connects analog switch U8;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, joins through the 6th pin of resistance R 1 with U1, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc11 of the 6th pin elder generation and capacitor C 11 parallelly connected, connects the parallelly connected of Rc12 and capacitor C 12 again, connect Rc13 and capacitor C 13 parallelly connected again after; Join with U7 the 4th pin, join through the 5th pin of capacitor C 10 with U7, the 9th pin of the 7th pin and U6 joins; Join with the 1st pin of U4, join with the 9th pin of U7, with the 1st of U5; 3 pins join, and join through resistance R 22 and U2 the 2nd pin, and the 8th pin joins through resistance R 25 and U1 the 9th pin; The 9th pin joins with potentiometer R12 and U1 the 2nd pin through resistance R 24, joins with potentiometer R23 and U2 the 2nd pin through resistance R 24, joins through resistance R 24 and U7 the 10th pin; The 13rd pin joins through resistance R 13 and U1 the 7th pin, joins through resistance R 14 and U1 the 14th pin, joins with the 1st pin of U4; Join with the 8th pin of U7, join with the 1st pin, the 3rd pin of U5, the 14th pin joins through potentiometer R11 and U1 the 2nd pin;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins through the 6th pin of resistance R 2 with U2, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc21 of the 6th pin elder generation and capacitor C 21 parallelly connected, connects the parallelly connected of Rc22 and capacitor C 22 again, connect Rc23 and capacitor C 23 parallelly connected again after; Join with U7 the 13rd pin,, join through the 12nd pin of capacitor C 20 with U7, the 7th pin and U7 the 9th pin join; The 8th pin of the 8th pin and U8 joins, and the connecting resistance Rc33 of the 9th pin elder generation is parallelly connected with capacitor C 33, connects the parallelly connected of Rc32 and capacitor C 32 again; After connecing Rc31 and capacitor C 31 parallelly connected again, join with U8 the 4th pin; Join through the 5th pin of capacitor C 30 with U8, the 13rd pin joins through resistance R 33 and U4 the 3rd pin, joins through resistance R 33 and U8 the 8th pin; Join through resistance R 34 and U2 the 14th pin, the 14th pin connects the 3rd pin of U4, joins through potentiometer R32 and U3 the 2nd pin;

Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 31 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st, 3 pins of said multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st, 2,4,5,6,7,9,10,11,12,13 pins of said voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins through resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, the 14th pin through diode D1 with join with the 1st pin of U7, the 1st pin of U8, meet VCC through resistance R 01;

The 1st pin of said analog switch U7 connects the 8th pin of U6 through resistance R 02, and the 2nd pin meets VCC, and the 3rd pin meets VEE; The 4th pin connects 6 pins of U1 through the fractional order integration unit, and the 5th pin connects 6 pins of U1 through capacitor C 10, and the 8th pin connects 7 pins of U1; The 9th pin connects 7 pins of U2, and the 12nd pin connects 6 pins of U2 through C20, and the 13rd pin connects 6 pins of U2 through the fractional order integration unit; The 14th pin meets VCC, the 15th, 16 pin ground connection;

The 1st pin of said analog switch U8 connects the 8th pin of U6 through resistance R 02; The 2nd pin meets VCC, and the 3rd pin meets VEE, and the 4th pin connects 9 pins of U2 through the fractional order integration unit; The 5th pin connects 9 pins of U2 through capacitor C 30; The 8th pin connects 8 pins of U2, and the 14th pin meets VCC, the 15th, 16 pin ground connection.

Certainly, above-mentioned explanation is not the restriction to invention, and the present invention also is not limited only to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art are made in essential scope of the present invention also belong to protection scope of the present invention.

Claims (2)

1. a method that realizes integer rank and fractional order automatically switched chaotic system is characterized in that being, may further comprise the steps:

(1) according to integer rank chaos system i be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dx}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dx}/\mathrm{dt}=x^2-\mathrm{hz}\end{array}\right.$ i?a＝20，b＝14，c＝10.6，h＝2.8

(2) according to fractional order chaos system ii be:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=x^2-\mathrm{hz}\end{array}\right.$ ii?0＜q＜1，a＝20，b＝14，c＝10.6，h＝2.8

(3) iii of choice function system of structure forms new integer rank and fractional order automatically switched chaotic system iv with chaos system i and ii:

$f\left(x\right)=\left\{\begin{array}{cc}q=1& x\&GreaterEqual;0\\ q=0.9& x<0\end{array}\right.$ iii

$\left\{\begin{array}{c}{d}^{f\left(x\right)}x/{\mathrm{dt}}^{f\left(x\right)}=a(y-x)\\ d^{f\left(x\right)}y/{\mathrm{dt}}^{f\left(x\right)}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{f\left(x\right)}z/{\mathrm{dt}}^{f\left(x\right)}=x^2-\mathrm{hz}\end{array}\right.$ iv

(4) according to chaos system iii and iv constructing analog Circuits System; Utilize voltage comparator U6 to obtain the high-low level of simulation; X＞=0 and x＜0; As the input of choice function, utilize analog switch U7 and U8 to realize the alternately output of integer rank integration and fractional order integration, utilize operational amplifier U1, U2, U3 and multiplier U4, U5 to obtain the analog circuit of integer rank and mark automatically switched chaotic system.Said operational amplifier U1, U2, U3 adopt LF347, and multiplier U4, U5 adopt AD633JN,, voltage comparator U6 adopts LM339, and analog switch U7, U8 adopt CD4052;

Said operational amplifier U1 connects voltage comparator U6; Analog switch U7, U8, multiplier U4, U5, said voltage comparator U6 connects analog switch U7, U8; Said multiplier U4 concatenation operation amplifier U2; Said operational amplifier U2 connects analog switch U7, said multiplier U5 concatenation operation amplifier U3, and said operational amplifier U3 connects analog switch U8;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, joins through the 6th pin of resistance R 1 with U1, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc11 of the 6th pin elder generation and capacitor C 11 parallelly connected, connects the parallelly connected of Rc12 and capacitor C 12 again, connect Rc13 and capacitor C 13 parallelly connected again after; Join with U7 the 4th pin, join through the 5th pin of capacitor C 10 with U7, the 9th pin of the 7th pin and U6 joins; Join with the 1st pin of U4, join with the 9th pin of U7, with the 1st of U5; 3 pins join, and join through resistance R 22 and U2 the 2nd pin, and the 8th pin joins through resistance R 25 and U1 the 9th pin; The 9th pin joins with potentiometer R12 and U1 the 2nd pin through resistance R 24, joins with potentiometer R23 and U2 the 2nd pin through resistance R 24, joins through resistance R 24 and U7 the 10th pin; The 13rd pin joins through resistance R 13 and U1 the 7th pin, joins through resistance R 14 and U1 the 14th pin, joins with the 1st pin of U4; Join with the 8th pin of U7, join with the 1st pin, the 3rd pin of U5, the 14th pin joins through potentiometer R11 and U1 the 2nd pin;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins through the 6th pin of resistance R 2 with U2, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc21 of the 6th pin elder generation and capacitor C 21 parallelly connected, connects the parallelly connected of Rc22 and capacitor C 22 again, connect Rc23 and capacitor C 23 parallelly connected again after; Join with U7 the 13rd pin,, join through the 12nd pin of capacitor C 20 with U7, the 7th pin and U7 the 9th pin join; The 8th pin of the 8th pin and U8 joins, and the connecting resistance Rc33 of the 9th pin elder generation is parallelly connected with capacitor C 33, connects the parallelly connected of Rc32 and capacitor C 32 again; After connecing Rc31 and capacitor C 31 parallelly connected again, join with U8 the 4th pin; Join through the 5th pin of capacitor C 30 with U8, the 13rd pin joins through resistance R 33 and U4 the 3rd pin, joins through resistance R 33 and U8 the 8th pin; Join through resistance R 34 and U2 the 14th pin, the 14th pin connects the 3rd pin of U4, joins through potentiometer R32 and U3 the 2nd pin;

Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 31 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st, 3 pins of said multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st, 2,4,5,6,7,9,10,11,12,13 pins of said voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins through resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, the 14th pin through diode D1 with join with the 1st pin of U7, the 1st pin of U8, meet VCC through resistance R 01;

The 1st pin of said analog switch U7 connects the 8th pin of U6 through resistance R 02, and the 2nd pin meets VCC, and the 3rd pin meets VEE; The 4th pin connects 6 pins of U1 through the fractional order integration unit, and the 5th pin connects 6 pins of U1 through capacitor C 10, and the 8th pin connects 7 pins of U1; The 9th pin connects 7 pins of U2, and the 12nd pin connects 6 pins of U2 through C20, and the 13rd pin connects 6 pins of U2 through the fractional order integration unit; The 14th pin meets VCC, the 15th, 16 pin ground connection;

The 1st pin of said analog switch U8 connects the 8th pin of U6 through resistance R 02; The 2nd pin meets VCC, and the 3rd pin meets VEE, and the 4th pin connects 9 pins of U2 through the fractional order integration unit; The 5th pin connects 9 pins of U2 through capacitor C 30; The 8th pin connects 8 pins of U2, and the 14th pin meets VCC, the 15th, 16 pin ground connection.

2. a circuit of realizing integer rank and fractional order automatically switched chaotic system is characterized in that being, comprises that operational amplifier U1, U2, U3 and multiplier U4, U5 and voltage comparator U6 and analog switch U7, U8 form; Said operational amplifier U1 connects voltage comparator U6; Analog switch U7, U8, multiplier U4, U5, said voltage comparator U6 connects analog switch U7, U8; Said multiplier U4 concatenation operation amplifier U2; Said operational amplifier U2 connects analog switch U7, said multiplier U5 concatenation operation amplifier U3, and said operational amplifier U3 connects analog switch U8;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, joins through the 6th pin of resistance R 1 with U1, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc11 of the 6th pin elder generation and capacitor C 11 parallelly connected, connects the parallelly connected of Rc12 and capacitor C 12 again, connect Rc13 and capacitor C 13 parallelly connected again after; Join with U7 the 4th pin, join through the 5th pin of capacitor C 10 with U7, the 9th pin of the 7th pin and U6 joins; Join with the 1st pin of U4, join with the 9th pin of U7, with the 1st of U5; 3 pins join, and join through resistance R 22 and U2 the 2nd pin, and the 8th pin joins through resistance R 25 and U1 the 9th pin; The 9th pin joins with potentiometer R12 and U1 the 2nd pin through resistance R 24, joins with potentiometer R23 and U2 the 2nd pin through resistance R 24, joins through resistance R 24 and U7 the 10th pin; The 13rd pin joins through resistance R 13 and U1 the 7th pin, joins through resistance R 14 and U1 the 14th pin, joins with the 1st pin of U4; Join with the 8th pin of U7, join with the 1st pin, the 3rd pin of U5, the 14th pin joins through potentiometer R11 and U1 the 2nd pin;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins through the 6th pin of resistance R 2 with U2, and the 3rd, 5,10,12 pin ground connection, the 4th pin meets VCC; The 11st pin meets VEE, behind the connecting resistance Rc21 of the 6th pin elder generation and capacitor C 21 parallelly connected, connects the parallelly connected of Rc22 and capacitor C 22 again, connect Rc23 and capacitor C 23 parallelly connected again after; Join with U7 the 13rd pin,, join through the 12nd pin of capacitor C 20 with U7, the 7th pin and U7 the 9th pin join; The 8th pin of the 8th pin and U8 joins, and the connecting resistance Rc33 of the 9th pin elder generation is parallelly connected with capacitor C 33, connects the parallelly connected of Rc32 and capacitor C 32 again; After connecing Rc31 and capacitor C 31 parallelly connected again, join with U8 the 4th pin; Join through the 5th pin of capacitor C 30 with U8, the 13rd pin joins through resistance R 33 and U4 the 3rd pin, joins through resistance R 33 and U8 the 8th pin; Join through resistance R 34 and U2 the 14th pin, the 14th pin connects the 3rd pin of U4, joins through potentiometer R32 and U3 the 2nd pin;

Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 31 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st, 3 pins of said multiplier U5 connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st, 2,4,5,6,7,9,10,11,12,13 pins of said voltage comparator U6 are unsettled, and the 3rd pin meets VCC; The 8th pin joins through resistance R 02 and the 1st pin of U7, the 1st pin of U8, and the 12nd pin meets VEE, the 14th pin through diode D1 with join with the 1st pin of U7, the 1st pin of U8, meet VCC through resistance R 01;

The 1st pin of said analog switch U7 connects the 8th pin of U6 through resistance R 02, and the 2nd pin meets VCC, and the 3rd pin meets VEE; The 4th pin connects 6 pins of U1 through the fractional order integration unit, and the 5th pin connects 6 pins of U1 through capacitor C 10, and the 8th pin connects 7 pins of U1; The 9th pin connects 7 pins of U2, and the 12nd pin connects 6 pins of U2 through C20, and the 13rd pin connects 6 pins of U2 through the fractional order integration unit; The 14th pin meets VCC, the 15th, 16 pin ground connection;

The 1st pin of said analog switch U8 connects the 8th pin of U6 through resistance R 02; The 2nd pin meets VCC, and the 3rd pin meets VEE, and the 4th pin connects 9 pins of U2 through the fractional order integration unit; The 5th pin connects 9 pins of U2 through capacitor C 30; The 8th pin connects 8 pins of U2, and the 14th pin meets VCC, the 15th, 16 pin ground connection.

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