CN202334551U - Circuit for implementing a fractional order chaotic system for automatically switching three systems - Google Patents

Abstract

The utility model discloses a circuit for implementing a fractional order chaotic system for automatically switching three systems. A fractional order automatic switching system consists of three chaotic subsystems and the fractional order automatic switching chaotic system is implemented by utilizing an analog circuit; operational amplifiers U1, U2 and U3 adopt LF347; multipliers U4 and U5 adopt AD633JN; a voltage comparator U6 adopts LM339; an analog switch U7 adopts CD4052; the operational amplifier U1 is connected with the voltage comparator U6, the analog switch U7, the multiplier U4 and the operational amplifier U2; the operational amplifier U2 is connected with the voltage comparator U6 and the analog switch U7; the operational amplifier U3 is connected with the operational amplifier U2 and the multiplier U4; the analog switch U7 is connected with the multiplier U5; and the multiplier U5 is connected with the operational amplifier U3. According to the utility model, the fractional order chaotic system for automatically switching the three subsystems is implemented by utilizing the analog circuit; and compared with an automatic switching chaotic system consisting of two chaotic subsystems and a non-switching fractional order chaotic system, the fractional order chaotic system is more complex and has stronger randomness, can become a new selection of a secure communication signal source and has wider application prospect in the secure communication.

Description

Realize the circuit of three system's automatically switched chaotic systems of fractional order

Technical field

The utility model relates to a kind of method of utilizing three system's automatically switched chaotic systems of Realization of Analog Circuit fractional order, specifically, relates to a kind of method and analog circuit of realizing integer rank and fractional order automatically switched chaotic system.

Background technology

Oneself has more report with the method for Realization of Analog Circuit integer rank and fractional order chaos system and circuit; Method and the circuit of realizing automatically switched chaotic system with digital circuit also have report; But the chaos circuit report with Realization of Analog Circuit automaticallyes switch is less; And the automatically switched chaotic system of oneself report and circuit are that 2 the sub-chaos systems in integer rank switch, and also do not have the method for 3 sub-chaos systems automatic switchovers and the report of circuit, the report that does not also have the fractional order automatically switched chaotic system to automatically switch; The invention provides the method and the analog circuit of the chaos system of three systems' automatic switchovers of a kind of fractional order; Enriched the quantity and the type of automatically switched chaotic system, a kind of selection of new secure communication signal source is provided, good application prospects has been arranged.

Summary of the invention

The technical problem that the utility model will solve provides a kind of circuit of realizing three system's automatically switched chaotic systems of fractional order.

The utility model adopts following technological means to realize goal of the invention: the circuit of three system's automatically switched chaotic systems of a kind of fractional order, it is characterized in that being, and comprise that operational amplifier U1, U2, U3 and multiplier U4, U5 and voltage comparator U6 and analog switch U7 form; Said operational amplifier U1 connects voltage comparator U6, analog switch U7, multiplier U4; Operational amplifier U2; Said operational amplifier U2 connects voltage comparator U6, analog switch U7, said operational amplifier U3 concatenation operation amplifier U2, multiplier U4; Said analog switch U7 connects multiplier U5, said multiplier U5 concatenation operation amplifier U3;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, and the 6th pin through resistance R 1 and U1 joins the 3rd, 5,10,12 pin ground connection; The 4th pin meets VCC, and the 11st pin meets VEE, and the connecting resistance Rc11 of the 6th pin elder generation is parallelly connected with capacitor C 11; Connecting resistance Rc12 and capacitor C 12 is parallelly connected again, connects the 7th pin behind connecting resistance Rc13 and capacitor C 13 parallelly connected again, and the 7th pin connects the 13rd pin through resistance R 13; Connect the 2nd pin of U2 through potentiometer R22, connect the 1st pin of U4, connect the 9th pin of U6; Connect the 4th, 5,11,13 pins of U7; The 8th pin connects the 9th pin through resistance R 25, and the 13rd pin connects the 14th pin through resistance R 14, and the 14th pin connects the 2nd pin through potentiometer R11;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins the 3rd, 5,10,12 pin ground connection through resistance R 2 and the 6th pin; The 4th pin meets VCC, and the 11st pin meets VEE, and the connecting resistance Rc21 of the 6th pin elder generation is parallelly connected with capacitor C 21; Connect the parallelly connected of Rc22 and capacitor C 22 again, connect the 7th pin after connecing Rc23 and capacitor C 23 parallelly connected again, the 7th pin links to each other with the 2nd pin through potentiometer R23; Connect the 9th pin of U1 through the R24 of resistance; Connect the 2nd pin of U1 through potentiometer R12, connect the 6th pin of U6, connect 6,7,10,12 pins of U7.The 8th pin connects the 13rd pin through resistance R 33; What connect Rc31 and capacitor C 31 earlier parallelly connectedly connects the parallelly connected of Rc32 and capacitor C 32 again; Connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 parallelly connected again; The 13rd pin connects the 14th pin through resistance R 34, and the 14th pin connects the 2nd pin of U3 through potentiometer R32, connects the 3rd pin of U4;

Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 3 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of said multiplier U5 connects the 8th pin of U7, and the 3rd pin connects the equal ground connection of the 9th pin the 2nd, 4,6 pins of U7, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st pin of said voltage comparator U6 meets VCC through resistance R 03, and the 16th pin through diode D2 meets U7 connects the 7th pin through diode D2 and resistance R 04; The 14th pin meets VCC through resistance R 03; Connect the 16th pin of U7 through diode D2, connect the 7th pin through diode D2 and resistance R 04, the 2nd, 4,5,10,11,13 pins are unsettled; The 3rd pin meets VCC, and the 12nd pin meets VEE;

The 2nd, 14 pins of said analog switch U7 meet VCC, and the 3rd pin meets VEE, and the 8th pin connects 1 pin of U5, and the 9th pin connects the 3rd pin of U5, the 15th pin ground connection.

Description of drawings

Fig. 1 is the circuit connection structure sketch map of the utility model preferred embodiment.

Fig. 2 is an operational amplifier U1 peripheral circuit structural representation.

Fig. 3 is operational amplifier U2 and multiplier U4 peripheral circuit structural representation.

Fig. 4 is operational amplifier U3 and multiplier U5 peripheral circuit structural representation.

Fig. 5 is a voltage comparator U6 peripheral circuit structural representation.

Fig. 6 is the peripheral circuit structural representation of analog switch U7.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment the utility model is made detailed description further.

Referring to Fig. 1-Fig. 6, at first construct three system's automatically switched chaotic systems of fractional order, the system that this preferred embodiment is selected

(1) according to chaos system i be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=x^2-\mathrm{hz}\end{array}\right.---i,a=20,b=14,c=10.6,h=2.8$

(2) according to chaos system ii be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{hz}\end{array}\right.---\mathrm{ii},a=20,b=14,c=10.6,h=2.8$

(3) according to chaos system iii be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=y^2-\mathrm{hz}\end{array}\right.---\mathrm{iii},a=20,b=14,c=10.6,h=2.8$

(4) according to iv of choice function system of chaos system structure and v chaos system i, ii and iii are formed one three the automatically switched chaotic system vi of system:

$f\left(x\right)=\left\{\begin{array}{cc}x& x\&GreaterEqual;0\\ y& x<0\end{array}\right.---\mathrm{iv}$

$f\left(y\right)=\left\{\begin{array}{cc}x& y\&GreaterEqual;0\\ y& y<0\end{array}\right.---v$

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=f\left(x\right)f\left(y\right)-\mathrm{hz}\end{array}\right.---\mathrm{vi}$

(5) according to a fractional order of the vi of the system structure automatically switched chaotic system vii of three systems

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}+\mathrm{cy}-\mathrm{xz}\\ d^{q}z/{\mathrm{dt}}^q=f\left(x\right)f\left(y\right)-\mathrm{hz}\end{array}\right.---\mathrm{vii},0<q<1,a=20,b=14,c=10.6,h=2.8$

(6) according to chaos system vii constructing analog Circuits System; Utilize voltage comparator U6 to obtain the high-low level of two simulations, x＞=0 and x＜0 and y＞=0 and y＜0 is as the control input of analog switch U7; Realize the alternately output of variable x, y, U5 obtains x through multiplier ², xy, y ²Automatic switchover output; Thereby realize the chaos system vi that three systems automatically switch; Realize chaos system vii through fractional order integration again, said operational amplifier U1, U2, U3 adopt LF347, and multiplier U4, U5 adopt AD633JN; Voltage comparator U6 adopts LM339, and analog switch U7 adopts CD4052;

Said operational amplifier U1 connects voltage comparator U6, analog switch U7, multiplier U4; Operational amplifier U2; Said operational amplifier U2 connects voltage comparator U6, analog switch U7, said operational amplifier U3 concatenation operation amplifier U2, multiplier U4; Said analog switch U7 connects multiplier U5, said multiplier U5 concatenation operation amplifier U3;

The 1st pin of said operational amplifier U1 joins through resistance R x and the 2nd pin, and the 6th pin through resistance R 1 and U1 joins the 3rd, 5,10,12 pin ground connection; The 4th pin meets VCC, and the 11st pin meets VEE, and the connecting resistance Rc11 of the 6th pin elder generation is parallelly connected with capacitor C 11; Connecting resistance Rc12 and capacitor C 12 is parallelly connected again, connects the 7th pin behind connecting resistance Rc13 and capacitor C 13 parallelly connected again, and the 7th pin connects the 13rd pin through resistance R 13; Connect the 2nd pin of U2 through potentiometer R22, connect the 1st pin of U4, connect the 9th pin of U6; Connect the 4th, 5,11,13 pins of U7; The 8th pin connects the 9th pin through resistance R 25, and the 13rd pin connects the 14th pin through resistance R 14, and the 14th pin connects the 2nd pin through potentiometer R11;

The 1st pin of said operational amplifier U2 joins through resistance R y and the 2nd pin, joins the 3rd, 5,10,12 pin ground connection through resistance R 2 and the 6th pin; The 4th pin meets VCC, and the 11st pin meets VEE, and the connecting resistance Rc21 of the 6th pin elder generation is parallelly connected with capacitor C 21; Connect the parallelly connected of Rc22 and capacitor C 22 again, connect the 7th pin after connecing Rc23 and capacitor C 23 parallelly connected again, the 7th pin links to each other with the 2nd pin through potentiometer R23; Connect the 9th pin of U1 through the R24 of resistance; Connect the 2nd pin of U1 through potentiometer R12, connect the 6th pin of U6, connect 6,7,10,12 pins of U7.The 8th pin connects the 13rd pin through resistance R 33; What connect Rc31 and capacitor C 31 earlier parallelly connectedly connects the parallelly connected of Rc32 and capacitor C 32 again; Connect the 9th pin behind connecting resistance Rc33 and capacitor C 33 parallelly connected again; The 13rd pin connects the 14th pin through resistance R 34, and the 14th pin connects the 2nd pin of U3 through potentiometer R32, connects the 3rd pin of U4; Said operational amplifier U3 the 1st pin joins through resistance R z and the 2nd pin; Join through the 9th pin of resistance R 3 with U2; U3 the 2nd pin connects 14 pins of U2 through R32, the 3rd pin ground connection, and the 4th pin meets VCC; 5th, 6,7,8,9,10,12,13,14 is all unsettled, and the 11st pin meets VEE;

The 1st pin of said multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 14th pin of U2, the equal ground connection of the 2nd, 4,6 pins, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 21 meets U2, and the 8th pin meets VCC;

The 1st pin of said multiplier U5 connects the 8th pin of U7, and the 3rd pin connects the equal ground connection of the 9th pin the 2nd, 4,6 pins of U7, and the 5th pin meets VEE, and the 7th pin was connected the 2nd pin that resistance R 31 meets U3, and the 8th pin meets VCC;

The 1st pin of said voltage comparator U6 meets VCC through resistance R 03, and the 16th pin through diode D2 meets U7 connects the 7th pin through diode D2 and resistance R 04; The 14th pin meets VCC through resistance R 03; Connect the 16th pin of U7 through diode D2, connect the 7th pin through diode D2 and resistance R 04, the 2nd, 4,5,10,11,13 pins are unsettled; The 3rd pin meets VCC, and the 12nd pin meets VEE;

The 2nd, 14 pins of said analog switch U7 meet VCC, and the 3rd pin meets VEE, and the 8th pin connects 1 pin of U5, and the 9th pin connects the 3rd pin of U5, the 15th pin ground connection.

Claims (5)

1. health index analyzer circuit comprises micro control system and signal acquiring system, it is characterized in that: said micro control system connects display screen, keyboard circuit and serial port circuit respectively by microcontroller and forms; Said signal acquiring system is by indoor temperature measurement circuit and the blood pressure measuring circuit, measured body weight circuit, measurement of bldy temperature circuit, the heart rate hear sounds measuring circuit that are connected respectively with the A/D change-over circuit.

2. according to the said health index analyzer of claim 1 circuit, it is characterized in that: said blood pressure measuring circuit comprises annular oscillation circuit U1, inflation motor circuit M1 and pressure-releasing electromagnetic valve circuit M2.

3. according to the said health index analyzer of claim 1 circuit; It is characterized in that: said measured body weight circuit comprises rheostat pressure sensor BR1; Said rheostat pressure sensor BR1 connects instrument amplifier one U2; Said instrument amplifier one U2 connects precision amplifier one U5, and said rheostat pressure sensor BR1 is connected precision amplifier two U3 with instrument amplifier one U2, and said precision amplifier two U3 connect source of stable pressure circuit one U4.

4. according to the said health index analyzer of claim 1 circuit, it is characterized in that: said heart rate hear sounds measuring circuit comprises pick-up head L1, and said pick-up head L1 connects instrument amplifier two U6, and said instrument amplifier two U6 connect precision amplifier three U7.

5. according to the said health index analyzer of claim 1 circuit; It is characterized in that: said measurement of bldy temperature circuit comprises resistance temperature detector Rt1; Said resistance temperature detector Rt1 connects instrument amplifier three U8; Said instrument amplifier three U8 connect precision amplifier four U9, and said precision amplifier four U9 connect source of stable pressure circuit two U10.

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