CN104184576A - Circuit design for general chaotic system - Google Patents

Abstract

The invention provides circuit design for a general chaotic system. Strip holes are welded to connecting ends, connecting wires can be inserted in the strip holes, reuse is achieved, operational amplifiers U1, operational amplifiers U2, resistors and capacitors are used for forming four phase-inverse summators and four phase-inverse integrators, each phase-inverse summator is provided with four input ends, four input signals are led out through each input end, operational amplifiers U3, resistors and capacitors are used for forming four phase inverters, multiplications are achieved through a multiplying unit U4, a multiplying unit U5, a multiplying unit U6 and a multiplying unit U7, a positive output signal and a negative output signal are led out by output of each multiplying unit, five output ends are led out by each output signal, LF347N is adopted in the operational amplifiers U1, the operational amplifiers U2 and the operational amplifiers U3, and AD633JN is adopted in the multiplying unit U4 and the multiplying unit U5. A circuit designed for the general chaotic system has the flexibility of a breadboard and the reliability of a PCB, meanwhile, the defect that elements are frequently replaced due to the fact that each system corresponds to a circuit in an existing general chaotic circuit is overcome, and the circuit designed for the general chaotic system is high in universality and reliability.

Description

A kind of circuit design of generically chaotic system

Technical field

The present invention relates to a kind of circuit design, particularly a kind of circuit design of generically chaotic system.

Background technology

Current chaos system circuit generally adopts bread board to carry out circuit design, with bread board carry out the time-consuming expense of circuit design and error rate higher, make mistakes and be not easy to check, as adopt PCB printed circuit board to design, corresponding each chaos system will once design, flexibility ratio is lower, design cycle is long, the generically chaotic circuit system that oneself has adopts welding manner, every circuit board can design a chaos system circuit, but exist greatlyr by plate amount, frequently change element, easily cause the damage of element.

Summary of the invention

For the deficiencies in the prior art, the present invention proposes a kind of circuit design of generically chaotic system, each link welding round, connecting line can insert round, Reusability, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form four groups of anti-phase adders and four groups of inverting integrators, every group of anti-phase adder You Si road input, every road input is drawn four input signals, utilize operational amplifier U3 and resistance and electric capacity to form four groups of inverters, utilize multiplier U4, U5, U6 and U7 realize respectively multiplying, positive signal and negative signal 2 tunnel outputs are drawn in every group of output, every road output signal is drawn 5 outputs, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and U5 adopt AD633JN.

Described operational amplifier U1 the 1st pin connects the 2nd pin by potentiometer U1_Y_F_R, connect the 6th pin by potentiometer U1_Y_C_R, the 2nd pin Jie Si road input Y_I_1R, Y_I_2R, Y_I_3R, Y_I_4R, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C y, the 7th connect+Y of pin, by resistance, Y_OUT_R meets Y, the 8th connect+X of pin, by resistance, X_OUT_R meets X, connect the 9th pin by capacitor C x, the 13rd pin Jie Si road input X_I_1R, X_I_2R, X_I_3R, X_I_4R, the 14th pin connects the 13rd pin by potentiometer U1_X_F_R, connect the 9th pin by potentiometer U1_X_C_R.

Described operational amplifier U2 the 1st pin connects the 2nd pin by potentiometer U2_U_F_R, connect the 6th pin by potentiometer U2_U_C_R, the 2nd pin Jie Si road input U_I_1R, U_I_2R, U_I_3R, U_I_4R, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C u, the 7th connect+U of pin, by resistance, U_OUT_R meets U, the 8th connect+Z of pin, by resistance, Z_OUT_R meets Z, connect the 9th pin by capacitor C z, the 13rd pin Jie Si road input Z_I_1R, Z_I_2R, Z_I_3R, Z_I_4R, the 14th pin connects the 13rd pin by potentiometer U2_Z_F_R, connect the 9th pin by potentiometer U2_Z_C_R.

Described operational amplifier U3 the 1st pin connection-X, connect the 2nd pin by potentiometer U3_X_F_R, the 2nd pin is by potentiometer U3_X_IN_R connection+X, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin is by connect-Y of potentiometer U3_Y_F_R, by connect+Y of potentiometer U3_Y_IN_R, the 7th connect-Y of pin, the 8th connect-Z of pin, connect the 9th pin by potentiometer U3_Z_F_R, the 9th pin is by connect+Z of U3_Z_IN_R, the 13rd pin connects the 14th pin by potentiometer U3_U_F_R, the 14th pin is by connect+U of potentiometer U3_U_IN_R.

Described multiplier U4 the 1st pin meets X_A, the 2nd, 4,6 pin ground connection, and the 3rd pin meets X_B, and the 5th pin connects negative supply VEE, and the 7th pin meets output X_AB, and the 8th pin connects positive supply VCC.

Described multiplier U5 the 1st pin meets Y_A, the 2nd, 4,6 pin ground connection, and the 3rd pin meets Y_B, and the 5th pin connects negative supply VEE, and the 7th pin meets output Y_AB, and the 8th pin connects positive supply VCC.

Described multiplier U6 the 1st pin meets Z_A, the 2nd, 4,6 pin ground connection, and the 3rd pin meets Z_B, and the 5th pin connects negative supply VEE, and the 7th pin meets output Z_AB, and the 8th pin connects positive supply VCC.

Described multiplier U7 the 1st pin meets U_A, the 2nd, 4,6 pin ground connection, and the 3rd pin meets U_B, and the 5th pin connects negative supply VEE, and the 7th pin meets output U_AB, and the 8th pin connects positive supply VCC.

Beneficial effect

The generically chaotic circuit system of the present invention's design, the flexibility of existing bread board, has again the reliability of printing PCB circuit board, and overcome oneself has generically chaotic circuit simultaneously, corresponding circuit of each system and the weakness of the frequent replacing element that causes has stronger versatility and reliability.

Brief description of the drawings

Fig. 1 is structure chart of the present invention.

Fig. 2 is the external circuit figure of integrated operational amplifier U1 of the present invention.

Fig. 3 is the external circuit figure of integrated operational amplifier U2 of the present invention.

Fig. 4 is the external circuit figure of integrated operational amplifier U3 of the present invention.

Fig. 5 is the external circuit figure of multiplier U4 of the present invention.

Fig. 6 is the external circuit figure of multiplier U5 of the present invention.

Fig. 7 is the external circuit figure of multiplier U6 of the present invention.

Fig. 8 is the external circuit figure of multiplier U7 of the present invention.

Embodiment

Below in conjunction with accompanying drawing, the present invention is further described in detail.

(1) using method of explanation the present invention in three-dimensional chaotic system as an example of Yang-Chen system example, referring to Fig. 1-Fig. 8, the Mathematical Modeling of Yang-Chen system is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\end{array}\right.a=35,b=3,c=35$

Described operational amplifier U1 the 1st pin connects the 2nd pin by potentiometer U1_Y_F_R, connects the 6th pin by potentiometer U1_Y_C_R, and the 2nd pin connects the 7th pin of U1 by input Y_I_1R, connects the 1st pin of U2, the 3rd by input Y_I_2R, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C y, the 7th connect+Y of pin, by resistance, Y_OUT_R meets Y, the 8th connect+X of pin, by resistance, X_OUT_R meets X, connects the 9th pin by capacitor C x, and the 13rd pin connects the 8th pin of U1 by input X_I_1R, connect the 7th pin of U4 by input X_I_2R, the 14th pin connects the 13rd pin by potentiometer U1_X_F_R, meets the 9th pin, wherein potentiometer Y_I_1R by potentiometer U1_X_C_R, Y_I_2R, X_I_1R is 2.85K Ω, and potentiometer X_I_2R is 1K Ω, potentiometer X_I_3R, X_I_4R, Y_I_3R, Y_I_4R is all unsettled, potentiometer U1_X_F_R, U1_X_C_R, U1_Y_F_R, U1_Y_C_R is 10K Ω, capacitor C x, Cy is 10nF.

Described operational amplifier U2 the 1st pin connects the 2nd pin by potentiometer U2_U_F_R, connects the 6th pin by potentiometer U2_U_C_R, the 2nd pin Jie Si road input U_I_1R, U_I_2R, U_I_3R, U_I_4R, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C u, the 7th connect+U of pin, by resistance, U_OUT_R meets U, the 8th connect+Z of pin, and by resistance, Z_OUT_R meets Z, connect the 9th pin by capacitor C z, the 13rd pin connects the 8th pin of U2 by input Z_I_1R, connect the 7th pin of U5 by input Z_I_2R, and the 14th pin connects the 13rd pin by potentiometer U2_Z_F_R, connect the 9th pin by potentiometer U2_Z_C_R, wherein potentiometer Z_I_1R is 33.4K Ω, and potentiometer Z_I_2R is 1K Ω, potentiometer Z_I_3R, Z_I_4R, U_I_1R, U_I_2R, U_I_3R, U_I_4R is all unsettled, potentiometer U2_Z_F_R, U2_Z_C_R is 10K Ω, potentiometer U2_U_F_R, U2_U_C_R is all unsettled, and capacitor C z is 10nF, and capacitor C u is unsettled.

Described operational amplifier U3 the 1st pin connection-X, connect the 2nd pin by potentiometer U3_X_F_R, the 2nd pin is by potentiometer U3_X_IN_R connection+X, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin is by connect-Y of potentiometer U3_Y_F_R, by connect+Y of potentiometer U3_Y_IN_R, the 7th connect-Y of pin, the 8th connect-Z of pin, connect the 9th pin by potentiometer U3_Z_F_R, the 9th pin is by connect+Z of U3_Z_IN_R, the 13rd pin connects the 14th pin by potentiometer U3_U_F_R, the 14th pin is by connect+U of potentiometer U3_U_IN_R, wherein potentiometer U3_X_F_R, U3_X_IN_R, U3_Y_F_R, U3_Y_IN_R, U3_Z_IN_R, U3_Z_F_R is 10K Ω, U3_U_F_R, U3_U_IN_R is unsettled.

Described multiplier U4 the 1st pin connects the 8th pin of U1, the 2nd, 4,6 pin ground connection, and the 3rd pin connects the 8th pin of U3, and the 5th pin connects negative supply VEE, and the 7th pin connects the 13rd pin of U1 by potentiometer X_I_2R, and the 8th pin connects positive supply VCC.

Described multiplier U5 the 1st pin connects the 8th pin of U1, the 2nd, 4,6 pin ground connection, and the 3rd pin connects the 7th pin of U1, and the 5th pin connects negative supply VEE, and the 7th pin connects the 13rd pin of U2 by potentiometer Z_I_2R, and the 8th pin connects positive supply VCC.

Described multiplier U6 the 1st pin is unsettled, the 2nd, 4,6 pin ground connection, and the 3rd pin is unsettled, and the 5th pin connects negative supply VEE, and the 7th pin is unsettled, and the 8th pin connects positive supply VCC.

Described multiplier U7 the 1st pin is unsettled, the 2nd, 4,6 pin ground connection, and the 3rd pin is unsettled, and the 5th pin connects negative supply VEE, and the 7th pin is unsettled, and the 8th pin connects positive supply VCC.

(2) using method of explanation the present invention in four-dimensional hyperchaotic system as an example of the Yang-Chen system of system example, referring to Fig. 1-Fig. 8, the Mathematical Modeling of Yang-Chen hyperchaotic system is:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{cx}-\mathrm{xz}+u\\ \mathrm{dz}/\mathrm{dt}=\mathrm{xy}-\mathrm{bz}\\ \mathrm{du}/\mathrm{dt}=-\mathrm{kx}\end{array}\right.a=35,b=3,c=35,k=8$

Described operational amplifier U1 the 1st pin connects the 2nd pin by potentiometer U1_Y_F_R, connect the 6th pin by potentiometer U1_Y_C_R, the 2nd pin connects the 7th pin of U1 by input Y_I_1R, connect the 1st pin of U2 by input Y_I_2R, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C y, the 7th connect+Y of pin, by resistance, Y_OUT_R meets Y, the 8th connect+X of pin, by resistance, X_OUT_R meets X, connect the 9th pin by capacitor C x, the 13rd pin connects the 8th pin of U1 by input X_I_1R, connect the 7th pin of U4 by input X_I_2R, connect the 7th pin of U2 by input X_I_3R, the 14th pin connects the 13rd pin by potentiometer U1_X_F_R, connect the 9th pin by potentiometer U1_X_C_R, wherein potentiometer Y_I_1R, Y_I_2R, X_I_1R is 2.85K Ω, potentiometer X_I_2R is 1K Ω, potentiometer X_I_3R is 100K Ω, potentiometer X_I_4R, Y_I_3R, Y_I_4R is all unsettled, potentiometer U1_X_F_R, U1_X_C_R, U1_Y_F_R, U1_Y_C_R is 10K Ω, capacitor C x, Cy is 10nF, .

Described operational amplifier U2 the 1st pin connects the 2nd pin by potentiometer U2_U_F_R, connects the 6th pin by potentiometer U2_U_C_R, and the 2nd pin connects the 1st pin of U3, the 3rd by input U_I_1R, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C u, the 7th connect+U of pin, by resistance, U_OUT_R meets U, the 8th connect+Z of pin, by resistance, Z_OUT_R meets Z, connect the 9th pin by capacitor C z, the 13rd pin connects the 8th pin of U2 by input Z_I_1R, connects the 7th pin of U5 by input Z_I_2R, the 14th pin connects the 13rd pin by potentiometer U2_Z_F_R, connect the 9th pin by potentiometer U2_Z_C_R, wherein potentiometer Z_I_1R is 33.4K Ω, and potentiometer Z_I_2R is 1K Ω, potentiometer U_I_1R is 12.5K Ω, potentiometer Z_I_3R, Z_I_4R, U_I_2R, U_I_3R, U_I_4R is all unsettled, potentiometer U2_Z_F_R, U2_Z_C_R, U2_U_F_R, U2_U_C_R is 10K Ω, capacitor C z, Cu is 10nF.

Described operational amplifier U3 the 1st pin connection-X, connect the 2nd pin by potentiometer U3_X_F_R, the 2nd pin is by potentiometer U3_X_IN_R connection+X, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin is by connect-Y of potentiometer U3_Y_F_R, by connect+Y of potentiometer U3_Y_IN_R, the 7th connect-Y of pin, the 8th connect-Z of pin, connect the 9th pin by potentiometer U3_Z_F_R, the 9th pin is by connect+Z of U3_Z_IN_R, the 13rd pin connects the 14th pin by potentiometer U3_U_F_R, the 14th pin is by connect+U of potentiometer U3_U_IN_R, wherein potentiometer U3_X_F_R, U3_X_IN_R, U3_Y_F_R, U3_Y_IN_R, U3_Z_IN_R, U3_Z_F_R is 10K Ω, U3_U_F_R, U3_U_IN_R is unsettled.

Described multiplier U4 the 1st pin connects the 8th pin of U1, the 2nd, 4,6 pin ground connection, and the 3rd pin connects the 8th pin of U3, and the 5th pin connects negative supply VEE, and the 7th pin connects the 13rd pin of U1 by potentiometer X_I_2R, and the 8th pin connects positive supply VCC.

Described multiplier U5 the 1st pin connects the 8th pin of U1, the 2nd, 4,6 pin ground connection, and the 3rd pin connects the 7th pin of U1, and the 5th pin connects negative supply VEE, and the 7th pin connects the 13rd pin of U2 by potentiometer Z_I_2R, and the 8th pin connects positive supply VCC.

Described multiplier U6 the 1st pin is unsettled, the 2nd, 4,6 pin ground connection, and the 3rd pin is unsettled, and the 5th pin connects negative supply VEE, and the 7th pin is unsettled, and the 8th pin connects positive supply VCC.

Described multiplier U7 the 1st pin is unsettled, the 2nd, 4,6 pin ground connection, and the 3rd pin is unsettled, and the 5th pin connects negative supply VEE, and the 7th pin is unsettled, and the 8th pin connects positive supply VCC.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art make in essential scope of the present invention, also belong to protection scope of the present invention.

Claims (8)

1. the circuit design of a generically chaotic system, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form four groups of anti-phase adders and four groups of inverting integrators, every group of anti-phase adder You Si road input, every road input is drawn four input signals, utilize operational amplifier U3 and resistance and electric capacity to form four groups of inverters, utilize multiplier U4, U5, U6 and U7 realize respectively multiplying, positive signal and negative signal 2 tunnel outputs are drawn in every group of output, every road output signal is drawn 5 outputs, described operational amplifier U1, operational amplifier U2 and operational amplifier U3 adopt LF347N, described multiplier U4 and U5 adopt AD633JN.

2. a kind of circuit design of generically chaotic system according to claim 1, described operational amplifier U1 the 1st pin connects the 2nd pin by potentiometer U1_Y_F_R, connect the 6th pin by potentiometer U1_Y_C_R, the 2nd pin Jie Si road input Y_I_1R, Y_I_2R, Y_I_3R, Y_I_4R, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C y, the 7th connect+Y of pin, by resistance, Y_OUT_R meets Y, the 8th connect+X of pin, by resistance, X_OUT_R meets X, connect the 9th pin by capacitor C x, the 13rd pin Jie Si road input X_I_1R, X_I_2R, X_I_3R, X_I_4R, the 14th pin connects the 13rd pin by potentiometer U1_X_F_R, connect the 9th pin by potentiometer U1_X_C_R.

3. a kind of circuit design of generically chaotic system according to claim 1, described operational amplifier U2 the 1st pin connects the 2nd pin by potentiometer U2_U_F_R, connect the 6th pin by potentiometer U2_U_C_R, the 2nd pin Jie Si road input U_I_1R, U_I_2R, U_I_3R, U_I_4R, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin connects the 7th pin by capacitor C u, the 7th connect+U of pin, by resistance, U_OUT_R meets U, the 8th connect+Z of pin, by resistance, Z_OUT_R meets Z, connect the 9th pin by capacitor C z, the 13rd pin Jie Si road input Z_I_1R, Z_I_2R, Z_I_3R, Z_I_4R, the 14th pin connects the 13rd pin by potentiometer U2_Z_F_R, connect the 9th pin by potentiometer U2_Z_C_R.

4. a kind of circuit design of generically chaotic system according to claim 1, described operational amplifier U3 the 1st pin connection-X, connect the 2nd pin by potentiometer U3_X_F_R, the 2nd pin is by potentiometer U3_X_IN_R connection+X, the 3rd, 5, 10, 12 pin ground connection, the 4th pin meets positive supply VCC, the 11st pin meets negative electricity VEE, the 6th pin is by connect-Y of potentiometer U3_Y_F_R, by connect+Y of potentiometer U3_Y_IN_R, the 7th connect-Y of pin, the 8th connect-Z of pin, connect the 9th pin by potentiometer U3_Z_F_R, the 9th pin is by connect+Z of U3_Z_IN_R, the 13rd pin connects the 14th pin by potentiometer U3_U_F_R, the 14th pin is by connect+U of potentiometer U3_U_IN_R.

5. a kind of circuit design of generically chaotic system according to claim 1, described multiplier U4 the 1st pin meets X_A, the 2nd, 4,6 pin ground connection, the 3rd pin meets X_B, the 5th pin connects negative supply VEE, and the 7th pin meets output X_AB, and the 8th pin connects positive supply VCC.

6. a kind of circuit design of generically chaotic system according to claim 1, described multiplier U5 the 1st pin meets Y_A, the 2nd, 4,6 pin ground connection, the 3rd pin meets Y_B, the 5th pin connects negative supply VEE, and the 7th pin meets output Y_AB, and the 8th pin connects positive supply VCC.

7. a kind of circuit design of generically chaotic system according to claim 1, described multiplier U6 the 1st pin meets Z_A, the 2nd, 4,6 pin ground connection, the 3rd pin meets Z_B, the 5th pin connects negative supply VEE, and the 7th pin meets output Z_AB, and the 8th pin connects positive supply VCC.

8. a kind of circuit design of generically chaotic system according to claim 1, described multiplier U7 the 1st pin meets U_A, the 2nd, 4,6 pin ground connection, the 3rd pin meets U_B, the 5th pin connects negative supply VEE, and the 7th pin meets output U_AB, and the 8th pin connects positive supply VCC.