CN104468075A - 0.3-order x-power-contained Lu chaotic system circuit realizing method based on mixed type fractional order integral circuit module - Google Patents

Abstract

The invention provides a 0.3-order x-power-contained Lu chaotic system circuit based on a mixed type fractional order integral circuit module. The mixed type fractional order integral circuit module is composed of six parts. A resistor of each part is formed by connecting four resistor bodies and one potentiometer in series. A capacitor of each part is formed by connecting four capacitor bodies in parallel. The first part is formed by connecting the resistor and the capacitor in parallel. The resistors of the latter parts are connected with an integral circuit of the former part in series and then connected with the capacitor of the part in parallel to form a fractional order integral module circuit. A mixed type structure is adopted, a PCB circuit is designed and manufactured, the 0.3-order fractional order integral circuit is formed by the five former parts, the resistance of the last part is zero, the capacitors are suspended in the midair, the method is adopted for realizing the 0.3-order chaotic system circuit, reliability is high and errors are not prone to occurring.

Description

0.3 rank based on mixed type fractional order integration circuit module contain x side L ü chaos system circuit realiration

Technical field

The present invention relates to a kind of general score rank integrating circuit module and 0.3 rank chaos system circuit realiration thereof, particularly a kind of 0.3 rank based on mixed type fractional order integration circuit module are containing the L ü chaos system circuit of x side.

Background technology

Because the resistance and the electric capacity that realize the circuit of chaotic systems with fractional order are all non-conventional resistive and electric capacity, the method of general employing resistant series and Capacitance parallel connection realizes, at present, the main method realized is the method utilizing existing resistance and electric capacity to combine on bread board, this method reliability and stability are lower, and exist and easily make mistakes, the not problem such as easy-to-search after makeing mistakes, the present invention is for overcoming this problem, adopt hybrid architecture, design and produce PCB circuit, circuit is made up of six parts, every partial ohmic is composed in series by four resistance and a potentiometer, every partition capacitance is made up of four Capacitance parallel connections, Part I is the parallel connection of resistance and electric capacity, all connect with the integrated circuit of previous section with the resistance in rear section, then general score rank integration module circuit is composed in parallel with this partition capacitance, 0.3 rank fractional order integration circuit is made up of the first five part, latter part of resistance is zero, electric capacity is unsettled, adopt in this way realize 0.3 rank fractional order chaotic system circuit, reliability is high, not easily make mistakes.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of 0.3 rank L ü chaos system based on mixed type fractional order integration circuit module and analog circuit realizes, and the present invention adopts following technological means to realize goal of the invention:

1, a kind of mixed type fractional order integration circuit module, it is characterized in that being: resistance Rx is in parallel with electric capacity Cx, form Part I, Part I is in parallel with electric capacity Cy again after connecting with resistance Ry, form Part II, front two parts are in parallel with electric capacity Cz again after connecting with resistance Rz, form Part III, first three part is in parallel with electric capacity Cw again after connecting with resistance Rw, form Part IV, front four parts are in parallel with electric capacity Cu again after connecting with resistance Ru, form Part V, the first five part is in parallel with electric capacity Cv again after connecting with resistance Rv, form Part VI, output pin A connects Part I, output pin B connects Part VI.

2, a kind of mixed type fractional order integration circuit module according to claim 1, it is characterized in that: described resistance Rx is composed in series by potentiometer Rx1 and resistance Rx2, Rx3, Rx4, Rx5, described electric capacity Cx is composed in parallel by electric capacity Cx1, Cx2, Cx3, Cx4; Described resistance Ry is composed in series by potentiometer Ry1 and resistance Ry2, Ry3, Ry4, Ry5, and described electric capacity Cy, by electric capacity Cy1, Cy2, Cy3, Cy4, composes in parallel; Described resistance Rz is composed in series by potentiometer Rz1 and resistance Rz2, Rz3, Rz4, Rz5, and described electric capacity Cz is composed in parallel by electric capacity Cz1, Cz2, Cz3, Cz4; Described resistance Rw is composed in series by potentiometer Rw1 and resistance Rw2, Rw3, Rw4, Rw5, and described electric capacity Cw is composed in parallel by electric capacity Cw1, Cw2, Cw3, Cw4; Described resistance Ru is composed in series by potentiometer Ru1 and resistance Ru2, Ru3, Ru4, Ru5, and described electric capacity Cu is composed in parallel by electric capacity Cu1, Cu2, Cu3, Cu4; Described resistance Rv is composed in series by potentiometer Rv1 and resistance Rv2, Rv3, Rv4, Rv5, and described electric capacity Cv is composed in parallel by electric capacity Cv1, Cv2, Cv3, Cv4.

3, a kind of mixed type fractional order integration circuit module according to claim 1, described 0.3 rank integrating circuit module, it is characterized in that: described resistance Rx=1.5210M, described potentiometer Rx1=0K, described resistance Rx2=1M, Rx3=500K, Rx4=20K, Rx5=1K, described electric capacity Cx=24.100uF, described electric capacity Cx1=10uF, Cx2=10uF, Cx3=3.3uF, Cx4=680nF; Described resistance Ry=1.1580M, described potentiometer Ry1=7K, described resistance Ry2=1M, Ry3=100K, Ry4=51K, Ry5=0K, described electric capacity Cy=4.3490uF, described electric capacity Cy1=3.3uF, Cy2=1uF, Cy3=47nF, Cy4 are unsettled; Described resistance Rz=0.6317M, described potentiometer Rz1=1.7K and described resistance Rz2=500K, Rz3=100K, Rz4=20, Rz5=10K, described electric capacity Cz=0.9258uF, described electric capacity Cz1=680nF, Cz2=220nF, Cz3=22nF, Cz4=3.3nF; Described resistance Rw=0.3475M, described potentiometer Rw1=0.5K and described resistance Rw2=200K, Rw3=100K, Rw4=47K, Rw5=0K, described electric capacity Cw=0.2109uF, described electric capacity Cw1=100nF, Cw2=100nF, Cw3=10nF, Cw4=1nF; Described resistance Ru=0.3246M, described potentiometer Ru1=4.6K and described resistance Ru2=200K, Ru3=100K, Ru4=20K, Ru5=0K, described electric capacity Cu=25.12nF, described electric capacity Cu1=22nF, Cu2=2.2nF, Cu3=1nF, Cu4 are unsettled; Described resistance Rv is zero, and described electric capacity Cv is unsettled.

4, based on 0.3 rank of mixed type fractional order integration circuit module containing the L ü chaos system circuit of x side, it is characterized in that:

(1) the L ü chaos system i containing x side is:

$\left\{\begin{array}{c}\frac{\mathrm{dx}}{\mathrm{dt}}=a(y-x)\\ \frac{\mathrm{dy}}{\mathrm{dt}}=\mathrm{cy}-\mathrm{xz}\\ \frac{\mathrm{dz}}{\mathrm{dt}}=x^2-\mathrm{bz}\end{array}\right.\mathrm{i\; a}=36,b=3,c=20$

(2) the 0.3 rank L ü chaos system ii containing x side is:

$\left\{\begin{array}{c}\frac{d^{\mathrm{\α}}x}{d{t}^{\mathrm{\α}}}=a(y-x)\\ \frac{d^{\mathrm{\α}}y}{d{t}^{\mathrm{\α}}}=\mathrm{cy}-\mathrm{xz}\\ \frac{d^{\mathrm{\α}}z}{d{t}^{\mathrm{\α}}}=x^2-\mathrm{bz}\end{array}\right.\mathrm{ii\; a}=36,b=3,c=20,\mathrm{\α}=0.3$

(2) according to the 0.3 rank L ü chaos system ii constructing analog circuit containing x side, operational amplifier U1, operational amplifier U2 and resistance and 0.3 rank integrating circuit module U5,0.3 rank integrating circuit module U6,0.3 rank integrating circuit module U7 is utilized to form anti-phase adder and anti-phase 0.3 rank integrator, multiplier U3 and multiplier U4 is utilized to realize multiplying, described operational amplifier U1 and operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 to adopt AD633JN;

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U3, multiplier U4 and 0.3 rank integrating circuit module U5,0.3 rank integrating circuit module U6, described operational amplifier U2 connects multiplier U3 and 0.3 rank integrating circuit module U7, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2;

1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R8 and U1, 2nd pin is connected with the 1st pin by resistance R6, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin connects the A pin of mixed type fractional order integration circuit U 7, 7th pin connects and exports y, connected with the 13rd pin by resistance R1, connected with the 2nd pin by resistance R5, connect the B pin of mixed type fractional order integration circuit U 8, 8th pin connects and exports x, connected with the 9th pin by resistance R4, connect the 1st pin of multiplier U3, connect the 1st of multiplier U4 the, 3 pins, connect the B pin of mixed type fractional order integration circuit U 6, 9th pin connects the A pin of mixed type fractional order integration circuit U 5, 13rd pin is connected with the 14th pin by resistance R2, 14th pin is connected with the 9th pin by resistance R3,

Described operational amplifier U2 the 1st, 2,6,7 pins are unsettled, 3rd, 5,10,12 pin ground connection, 4th pin meets VCC, and the 11st pin meets VEE, and the 8th pin exports z, connected with the 9th pin by resistance R12, connect the 3rd pin of multiplier U3, connect the B pin of mixed type fractional order integration circuit U 10, the 9th pin connects the A pin of mixed type fractional order integration circuit U 9,13rd pin connects the 14th pin by resistance R9, and the 14th pin connects the 9th pin by resistance R11;

1st pin of described multiplier U3 connects the 8th pin of U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R7, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U2 the 13rd pin by resistance R10, and the 8th pin meets VCC.

The A pin of described 0.3 rank integrating circuit module U5 connects the 9th pin of operational amplifier U1, and B pin connects the 8th pin of operational amplifier U1;

The A pin of described 0.3 rank integrating circuit module U6 connects the 6th pin of operational amplifier U1, and B pin connects the 7th pin of operational amplifier U1;

The A pin of described 0.3 rank integrating circuit module U7 connects the 9th pin of operational amplifier U2, and B pin connects the 8th pin of operational amplifier U2.

The invention has the beneficial effects as follows: adopt hybrid architecture, design and produce PCB circuit, circuit is made up of six parts, every partial ohmic is composed in series by four resistance and a potentiometer, every partition capacitance is made up of four Capacitance parallel connections, Part I is the parallel connection of resistance and electric capacity, all connect with the integrated circuit of previous section with the resistance in rear section, then general score rank integration module circuit is composed in parallel with this partition capacitance, 0.3 rank fractional order integration circuit is made up of the first five part, latter part of resistance is zero, electric capacity is unsettled, adopt in this way realize 0.3 rank fractional order chaotic system circuit, reliability is high, not easily make mistakes.

Accompanying drawing explanation

Fig. 1 is chain type fractional order integration circuit module internal structure schematic diagram (a) of the present invention, inner actual connection layout (b) and 0.3 rank integrating circuit module map (c).

Fig. 2 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 3 and Fig. 4 is the actual connection layout of circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 4.

1, a kind of mixed type fractional order integration circuit module, it is characterized in that being: resistance Rx is in parallel with electric capacity Cx, form Part I, Part I is in parallel with electric capacity Cy again after connecting with resistance Ry, form Part II, front two parts are in parallel with electric capacity Cz again after connecting with resistance Rz, form Part III, first three part is in parallel with electric capacity Cw again after connecting with resistance Rw, form Part IV, front four parts are in parallel with electric capacity Cu again after connecting with resistance Ru, form Part V, the first five part is in parallel with electric capacity Cv again after connecting with resistance Rv, form Part VI, output pin A connects Part I, output pin B connects Part VI.

2, a kind of mixed type fractional order integration circuit module according to claim 1, it is characterized in that: described resistance Rx is composed in series by potentiometer Rx1 and resistance Rx2, Rx3, Rx4, Rx5, described electric capacity Cx is composed in parallel by electric capacity Cx1, Cx2, Cx3, Cx4; Described resistance Ry is composed in series by potentiometer Ry1 and resistance Ry2, Ry3, Ry4, Ry5, and described electric capacity Cy, by electric capacity Cy1, Cy2, Cy3, Cy4, composes in parallel; Described resistance Rz is composed in series by potentiometer Rz1 and resistance Rz2, Rz3, Rz4, Rz5, and described electric capacity Cz is composed in parallel by electric capacity Cz1, Cz2, Cz3, Cz4; Described resistance Rw is composed in series by potentiometer Rw1 and resistance Rw2, Rw3, Rw4, Rw5, and described electric capacity Cw is composed in parallel by electric capacity Cw1, Cw2, Cw3, Cw4; Described resistance Ru is composed in series by potentiometer Ru1 and resistance Ru2, Ru3, Ru4, Ru5, and described electric capacity Cu is composed in parallel by electric capacity Cu1, Cu2, Cu3, Cu4; Described resistance Rv is composed in series by potentiometer Rv1 and resistance Rv2, Rv3, Rv4, Rv5, and described electric capacity Cv is composed in parallel by electric capacity Cv1, Cv2, Cv3, Cv4.

3, a kind of mixed type fractional order integration circuit module according to claim 1, described 0.3 rank integrating circuit module, it is characterized in that: described resistance Rx=1.5210M, described potentiometer Rx1=0K, described resistance Rx2=1M, Rx3=500K, Rx4=20K, Rx5=1K, described electric capacity Cx=24.100uF, described electric capacity Cx1=10uF, Cx2=10uF, Cx3=3.3uF, Cx4=680nF; Described resistance Ry=1.1580M, described potentiometer Ry1=7K, described resistance Ry2=1M, Ry3=100K, Ry4=51K, Ry5=0K, described electric capacity Cy=4.3490uF, described electric capacity Cy1=3.3uF, Cy2=1uF, Cy3=47nF, Cy4 are unsettled; Described resistance Rz=0.6317M, described potentiometer Rz1=1.7K and described resistance Rz2=500K, Rz3=100K, Rz4=20, Rz5=10K, described electric capacity Cz=0.9258uF, described electric capacity Cz1=680nF, Cz2=220nF, Cz3=22nF, Cz4=3.3nF; Described resistance Rw=0.3475M, described potentiometer Rw1=0.5K and described resistance Rw2=200K, Rw3=100K, Rw4=47K, Rw5=0K, described electric capacity Cw=0.2109uF, described electric capacity Cw1=100nF, Cw2=100nF, Cw3=10nF, Cw4=1nF; Described resistance Ru=0.3246M, described potentiometer Ru1=4.6K and described resistance Ru2=200K, Ru3=100K, Ru4=20K, Ru5=0K, described electric capacity Cu=25.12nF, described electric capacity Cu1=22nF, Cu2=2.2nF, Cu3=1nF, Cu4 are unsettled; Described resistance Rv is zero, and described electric capacity Cv is unsettled.

4, based on 0.3 rank of mixed type fractional order integration circuit module containing the L ü chaos system circuit of x side, it is characterized in that:

(1) the L ü chaos system i containing x side is:

$\left\{\begin{array}{c}\frac{\mathrm{dx}}{\mathrm{dt}}=a(y-x)\\ \frac{\mathrm{dy}}{\mathrm{dt}}=\mathrm{cy}-\mathrm{xz}\\ \frac{\mathrm{dz}}{\mathrm{dt}}=x^2-\mathrm{bz}\end{array}\right.\mathrm{i\; a}=36,b=3,c=20$

(2) the 0.3 rank L ü chaos system ii containing x side is:

$\left\{\begin{array}{c}\frac{d^{\mathrm{\α}}x}{d{t}^{\mathrm{\α}}}=a(y-x)\\ \frac{d^{\mathrm{\α}}y}{d{t}^{\mathrm{\α}}}=\mathrm{cy}-\mathrm{xz}\\ \frac{d^{\mathrm{\α}}z}{d{t}^{\mathrm{\α}}}=x^2-\mathrm{bz}\end{array}\right.\mathrm{ii\; a}=36,b=3,c=20,\mathrm{\α}=0.3$

(2) according to the 0.3 rank L ü chaos system ii constructing analog circuit containing x side, operational amplifier U1, operational amplifier U2 and resistance and 0.3 rank integrating circuit module U5,0.3 rank integrating circuit module U6,0.3 rank integrating circuit module U7 is utilized to form anti-phase adder and anti-phase 0.3 rank integrator, multiplier U3 and multiplier U4 is utilized to realize multiplying, described operational amplifier U1 and operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 to adopt AD633JN;

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U3, multiplier U4 and 0.3 rank integrating circuit module U5,0.3 rank integrating circuit module U6, described operational amplifier U2 connects multiplier U3 and 0.3 rank integrating circuit module U7, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2;

1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R8 and U1, 2nd pin is connected with the 1st pin by resistance R6, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin connects the A pin of mixed type fractional order integration circuit U 7, 7th pin connects and exports y, connected with the 13rd pin by resistance R1, connected with the 2nd pin by resistance R5, connect the B pin of mixed type fractional order integration circuit U 8, 8th pin connects and exports x, connected with the 9th pin by resistance R4, connect the 1st pin of multiplier U3, connect the 1st of multiplier U4 the, 3 pins, connect the B pin of mixed type fractional order integration circuit U 6, 9th pin connects the A pin of mixed type fractional order integration circuit U 5, 13rd pin is connected with the 14th pin by resistance R2, 14th pin is connected with the 9th pin by resistance R3,

Described operational amplifier U2 the 1st, 2,6,7 pins are unsettled, 3rd, 5,10,12 pin ground connection, 4th pin meets VCC, and the 11st pin meets VEE, and the 8th pin exports z, connected with the 9th pin by resistance R12, connect the 3rd pin of multiplier U3, connect the B pin of mixed type fractional order integration circuit U 10, the 9th pin connects the A pin of mixed type fractional order integration circuit U 9,13rd pin connects the 14th pin by resistance R9, and the 14th pin connects the 9th pin by resistance R11;

1st pin of described multiplier U3 connects the 8th pin of U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R7, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U2 the 13rd pin by resistance R10, and the 8th pin meets VCC.

The A pin of described 0.3 rank integrating circuit module U5 connects the 9th pin of operational amplifier U1, and B pin connects the 8th pin of operational amplifier U1;

The A pin of described 0.3 rank integrating circuit module U6 connects the 6th pin of operational amplifier U1, and B pin connects the 7th pin of operational amplifier U1;

The A pin of described 0.3 rank integrating circuit module U7 connects the 9th pin of operational amplifier U2, and B pin connects the 8th pin of operational amplifier U2.

Resistance R1=R4=2.78k Ω in circuit, R2=R3=R6=R8=R9=R11=10k Ω, R5=5k Ω, R7=R10=1k Ω, R12=33.33k Ω.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (4)

1. a mixed type fractional order integration circuit module, it is characterized in that being: resistance Rx is in parallel with electric capacity Cx, form Part I, Part I is in parallel with electric capacity Cy again after connecting with resistance Ry, form Part II, front two parts are in parallel with electric capacity Cz again after connecting with resistance Rz, form Part III, first three part is in parallel with electric capacity Cw again after connecting with resistance Rw, form Part IV, front four parts are in parallel with electric capacity Cu again after connecting with resistance Ru, form Part V, the first five part is in parallel with electric capacity Cv again after connecting with resistance Rv, form Part VI, output pin A connects Part I, output pin B connects Part VI.

2. a kind of mixed type fractional order integration circuit module according to claim 1, it is characterized in that: described resistance Rx is composed in series by potentiometer Rx1 and resistance Rx2, Rx3, Rx4, Rx5, described electric capacity Cx is composed in parallel by electric capacity Cx1, Cx2, Cx3, Cx4; Described resistance Ry is composed in series by potentiometer Ry1 and resistance Ry2, Ry3, Ry4, Ry5, and described electric capacity Cy, by electric capacity Cy1, Cy2, Cy3, Cy4, composes in parallel; Described resistance Rz is composed in series by potentiometer Rz1 and resistance Rz2, Rz3, Rz4, Rz5, and described electric capacity Cz is composed in parallel by electric capacity Cz1, Cz2, Cz3, Cz4; Described resistance Rw is composed in series by potentiometer Rw1 and resistance Rw2, Rw3, Rw4, Rw5, and described electric capacity Cw is composed in parallel by electric capacity Cw1, Cw2, Cw3, Cw4; Described resistance Ru is composed in series by potentiometer Ru1 and resistance Ru2, Ru3, Ru4, Ru5, and described electric capacity Cu is composed in parallel by electric capacity Cu1, Cu2, Cu3, Cu4; Described resistance Rv is composed in series by potentiometer Rv1 and resistance Rv2, Rv3, Rv4, Rv5, and described electric capacity Cv is composed in parallel by electric capacity Cv1, Cv2, Cv3, Cv4.

3. a kind of mixed type fractional order integration circuit module according to claim 1, described 0.3 rank integrating circuit module, it is characterized in that: described resistance Rx=1.5210M, described potentiometer Rx1=0K, described resistance Rx2=1M, Rx3=500K, Rx4=20K, Rx5=1K, described electric capacity Cx=24.100uF, described electric capacity Cx1=10uF, Cx2=10uF, Cx3=3.3uF, Cx4=680nF; Described resistance Ry=1.1580M, described potentiometer Ry1=7K, described resistance Ry2=1M, Ry3=100K, Ry4=51K, Ry5=0K, described electric capacity Cy=4.3490uF, described electric capacity Cy1=3.3uF, Cy2=1uF, Cy3=47nF, Cy4 are unsettled; Described resistance Rz=0.6317M, described potentiometer Rz1=1.7K and described resistance Rz2=500K, Rz3=100K, Rz4=20, Rz5=10K, described electric capacity Cz=0.9258uF, described electric capacity Cz1=680nF, Cz2=220nF, Cz3=22nF, Cz4=3.3nF; Described resistance Rw=0.3475M, described potentiometer Rw1=0.5K and described resistance Rw2=200K, Rw3=100K, Rw4=47K, Rw5=0K, described electric capacity Cw=0.2109uF, described electric capacity Cw1=100nF, Cw2=100nF, Cw3=10nF, Cw4=1nF; Described resistance Ru=0.3246M, described potentiometer Ru1=4.6K and described resistance Ru2=200K, Ru3=100K, Ru4=20K, Ru5=0K, described electric capacity Cu=25.12nF, described electric capacity Cu1=22nF, Cu2=2.2nF, Cu3=1nF, Cu4 are unsettled; Described resistance Rv is zero, and described electric capacity Cv is unsettled.

4. based on 0.3 rank of mixed type fractional order integration circuit module containing the L ü chaos system circuit of x side, it is characterized in that:

(1) the L ü chaos system i containing x side is:

$\left\{\begin{array}{c}\frac{\mathrm{dx}}{\mathrm{dt}}=a(y-x)\\ \frac{\mathrm{dy}}{\mathrm{dt}}=\mathrm{cy}-\mathrm{xz}\\ \frac{\mathrm{dz}}{\mathrm{dt}}=x^2-\mathrm{bz}\end{array}\right.,i,a=36,b=3,c=20$

(2) the 0.3 rank L ü chaos system ii containing x side is:

$\left\{\begin{array}{c}\frac{d^{\mathrm{\α}}x}{{\mathrm{dt}}^{\mathrm{\α}}}=a(y-x)\\ \frac{d^{\mathrm{\α}}y}{{\mathrm{dt}}^{\mathrm{\α}}}=\mathrm{cy}-\mathrm{xz}\\ \frac{d^{\mathrm{\α}}z}{{\mathrm{dt}}^{\mathrm{\α}}}=x^2-\mathrm{bz}\end{array}\right.,\mathrm{ii},a=36,b=3,c=20,\mathrm{\α}=0.3$

(2) according to the 0.3 rank L ü chaos system ii constructing analog circuit containing x side, operational amplifier U1, operational amplifier U2 and resistance and 0.3 rank integrating circuit module U5,0.3 rank integrating circuit module U6,0.3 rank integrating circuit module U7 is utilized to form anti-phase adder and anti-phase 0.3 rank integrator, multiplier U3 and multiplier U4 is utilized to realize multiplying, described operational amplifier U1 and operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 to adopt AD633JN;

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U3, multiplier U4 and 0.3 rank integrating circuit module U5,0.3 rank integrating circuit module U6, described operational amplifier U2 connects multiplier U3 and 0.3 rank integrating circuit module U7, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2;

1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R8 and U1, 2nd pin is connected with the 1st pin by resistance R6, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin connects the A pin of mixed type fractional order integration circuit U 7, 7th pin connects and exports y, connected with the 13rd pin by resistance R1, connected with the 2nd pin by resistance R5, connect the B pin of mixed type fractional order integration circuit U 8, 8th pin connects and exports x, connected with the 9th pin by resistance R4, connect the 1st pin of multiplier U3, connect the 1st of multiplier U4 the, 3 pins, connect the B pin of mixed type fractional order integration circuit U 6, 9th pin connects the A pin of mixed type fractional order integration circuit U 5, 13rd pin is connected with the 14th pin by resistance R2, 14th pin is connected with the 9th pin by resistance R3,

Described operational amplifier U2 the 1st, 2,6,7 pins are unsettled, 3rd, 5,10,12 pin ground connection, 4th pin meets VCC, and the 11st pin meets VEE, and the 8th pin exports z, connected with the 9th pin by resistance R12, connect the 3rd pin of multiplier U3, connect the B pin of mixed type fractional order integration circuit U 10, the 9th pin connects the A pin of mixed type fractional order integration circuit U 9,13rd pin connects the 14th pin by resistance R9, and the 14th pin connects the 9th pin by resistance R11;

1st pin of described multiplier U3 connects the 8th pin of U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R7, and the 8th pin meets VCC;

1st pin of described multiplier U4 connects the 7th pin of U1, and the 3rd pin connects the 8th pin of U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U2 the 13rd pin by resistance R10, and the 8th pin meets VCC.

The A pin of described 0.3 rank integrating circuit module U5 connects the 9th pin of operational amplifier U1, and B pin connects the 8th pin of operational amplifier U1;

The A pin of described 0.3 rank integrating circuit module U6 connects the 6th pin of operational amplifier U1, and B pin connects the 7th pin of operational amplifier U1;

The A pin of described 0.3 rank integrating circuit module U7 connects the 9th pin of operational amplifier U2, and B pin connects the 8th pin of operational amplifier U2.