CN104506302A - Implementation of 0.9-order yth-power-containing Lu chaotic system circuit on basis of T-shaped fractional integration circuit module - Google Patents

Abstract

The invention provides a 0.9-order yth-power-containing Lu chaotic system circuit on the basis of a T-shaped fractional integration circuit module. The T-shaped fractional integration circuit module consists of six parts; a first part is formed in a manner that after being connected in series, four resistors and a potentiometer are connected in parallel with four capacitors; each of the next five parts is formed in a manner that after being connected in series, four resistors and a potentiometer are connected in series with a parallel part of four capacitors. According to the 0.9-order yth-power-containing Lu chaotic system circuit on the basis of the T-shaped fractional integration circuit module, a T-shaped structure is adopted; a PCB (Printed Circuit Board) circuit is designed and produced; the 0.9-order fractional integration circuit consists of first three parts and next three parts are not used and are suspended in the air; the 0.9-order fractional chaotic system circuit implemented by adopting the method has high reliability and is difficult to go wrong.

Description

0.9 rank based on T-shaped fractional order integration circuit module contain y side L ü chaos system circuit realiration

Technical field

The present invention relates to a kind of general score rank integrating circuit module and 0.9 rank chaos system circuit realiration thereof, particularly 0.9 rank based on the general score rank integrating circuit module of T-type structure realize containing y side's L ü chaos system and analog circuit.

Background technology

Because the resistance and the electric capacity that realize the circuit of chaotic systems with fractional order are all non-conventional resistive and electric capacity, the method of general employing resistant series and Capacitance parallel connection realizes, at present, the main method realized is the method utilizing existing resistance and electric capacity to combine on bread board, this method reliability and stability are lower, and exist and easily make mistakes, the not problem such as easy-to-search after makeing mistakes, the present invention is for overcoming this problem, adopt T-type structure, design and produce PCB circuit, whole circuit is made up of six parts, after Part I is connected by four resistance and a potentiometer, form with four Capacitance parallel connections, five parts next are by after four resistance and a potentiometer series connection, be in series with four Capacitance parallel connection parts and form, 0.9 rank fractional order integration circuit is made up of first three part, rear three parts are unsettled, adopt in this way realize 0.9 rank fractional order chaotic system circuit, reliability is high, not easily make mistakes.

Summary of the invention

0.9 rank that the technical problem to be solved in the present invention is to provide a kind of fractional order integration circuit module based on T-type structure realize containing y side's L ü chaos system and analog circuit, and the present invention adopts following technological means to realize goal of the invention:

1, a T-shaped general score rank integrating circuit module, is characterized in that being: resistance Rx is in parallel with electric capacity Cx, forms Part I, resistance Ry connects with electric capacity Cy, and form Part II, resistance Rz connects with electric capacity Cz, form Part III, resistance Rw connects with electric capacity Cw, and form Part IV, resistance Ru connects with electric capacity Cu, form Part V, resistance Rv connects with electric capacity Cv, forms Part VI, and Part I and below five parts are for being connected in parallel.

2, a kind of T-shaped general score rank integrating circuit module according to claim 1, it is characterized in that: described resistance Rx is composed in series by potentiometer Rx1 and resistance Rx2, Rx3, Rx4, Rx5, described electric capacity Cx is composed in parallel by electric capacity Cx1, Cx2, Cx3, Cx4; Described resistance Ry is composed in series by potentiometer Ry1 and resistance Ry2, Ry3, Ry4, Ry5, and described electric capacity Cy, by electric capacity Cy1, Cy2, Cy3, Cy4, composes in parallel; Described resistance Rz is composed in series by potentiometer Rz1 and resistance Rz2, Rz3, Rz4, Rz5, and described electric capacity Cz is composed in parallel by electric capacity Cz1, Cz2, Cz3, Cz4; Described resistance Rw is composed in series by potentiometer Rw1 and resistance Rw2, Rw3, Rw4, Rw5, and described electric capacity Cw is composed in parallel by electric capacity Cw1, Cw2, Cw3, Cw4; Described resistance Ru is composed in series by potentiometer Ru1 and resistance Ru2, Ru3, Ru4, Ru5, and described electric capacity Cu is composed in parallel by electric capacity Cu1, Cu2, Cu3, Cu4; Described resistance Rv is composed in series by potentiometer Rv1 and resistance Rv2, Rv3, Rv4, Rv5, and described electric capacity Cv is composed in parallel by electric capacity Cv1, Cv2, Cv3, Cv4.

3, a kind of T-shaped general score rank integrating circuit module according to claim 1, described 0.9 rank integrating circuit module, it is characterized in that: described resistance Rx=63.10M, described potentiometer Rx1=200K, described resistance Rx2=22M, Rx3=22M, Rx4=15M, Rx5=3.9M, described electric capacity Cx=0.4410uF, described electric capacity Cx1=330nF, Cx2=100nF, Cx3=10nF, Cx4=1nF; Described resistance Ry=1.598M, described potentiometer Ry1=1.9K, described resistance Ry2=1.5M, Ry3=91K, Ry4=5.1K, Ry5=0K, described electric capacity Cy=0.4870uF, described electric capacity Cy1=330nF, Cy2=100nF, Cy3=47nF, Cy4=10nF; Described resistance Rz=0.01581M, described potentiometer Rz1=0.71K and described resistance Rz2=10K, Rz3=51K, Rz4=5.1K, Rz5=0K, described electric capacity Cz=0.2937uF, described electric capacity Cz1=220nF, Cz2=68nF, Cz3=4.7nF, Cz4=1nF; Described resistance Rw, Ru, Rv are all unsettled, and described electric capacity Cw, Cu, Cv are all unsettled.

4,0.9 rank based on T-shaped fractional order integration circuit module contain y side L ü chaos system circuit, it is characterized in that:

(1) containing y side L ü chaos system i be:

$\begin{array}{ccc}\left\{\begin{array}{c}\frac{\mathrm{dx}}{\mathrm{dt}}=a(y-x)\\ \frac{\mathrm{dy}}{\mathrm{dt}}=\mathrm{cy}-\mathrm{xz}\\ \frac{\mathrm{dz}}{\mathrm{dt}}=y^2-\mathrm{bz}\end{array}\right.& i& a=36,b=3,c=20\end{array}$

(2) 0.9 rank containing y side L ü chaos system ii are:

$\begin{array}{ccc}\left\{\begin{array}{c}\frac{d^{\mathrm{\α}}x}{{\mathrm{dt}}^{\mathrm{\α}}}=a(y-x)\\ \frac{d^{\mathrm{\α}}y}{{\mathrm{dt}}^{\mathrm{\α}}}=\mathrm{cy}-\mathrm{xz}\\ \frac{d^{\mathrm{\α}}z}{{\mathrm{dt}}^{\mathrm{\α}}}=y^2-\mathrm{bz}\end{array}\right.& \mathrm{ii}& a=36,b=3,c=20,\mathrm{\α}=0.7\end{array}$

(2) x side L ü chaos system ii constructing analog circuit is contained according to 0.9 rank, operational amplifier U1, operational amplifier U2 and resistance and 0.9 rank integrating circuit module U5,0.9 rank integrating circuit module U6,0.9 rank integrating circuit module U7 is utilized to form anti-phase adder and anti-phase 0.9 rank integrator, multiplier U3 and multiplier U4 is utilized to realize multiplying, described operational amplifier U1 and operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 to adopt AD633JN;

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U3, multiplier U4 and 0.9 rank integrating circuit module U5,0.9 rank integrating circuit module U6, described operational amplifier U2 connects multiplier U3 and 0.9 rank integrating circuit module U7, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2;

1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R8 and U1, 2nd pin is connected with the 1st pin by resistance R6, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin connects the A pin of T-shaped fractional order integration circuit U 6, 7th pin connects and exports y, connected with the 13rd pin by resistance R1, connected with the 2nd pin by resistance R5, connect the B pin of T-shaped fractional order integration circuit U 6, connect the 1st of multiplier U4 the, 3 pins, 8th pin connects and exports x, connected with the 9th pin by resistance R4, connect the 1st pin of multiplier U3, connect the B pin of T-shaped fractional order integration circuit U 5, 9th pin connects the A pin of T-shaped fractional order integration circuit U 5, 13rd pin is connected with the 14th pin by resistance R2, 14th pin is connected with the 9th pin by resistance R3,

Described operational amplifier U2 the 1st, 2,6,7 pins are unsettled, 3rd, 5,10,12 pin ground connection, 4th pin meets VCC, and the 11st pin meets VEE, and the 8th pin exports z, connected with the 9th pin by resistance R12, connect the 3rd pin of multiplier U3, connect the B1 pin of T-shaped fractional order integration circuit U 7, the 9th pin connects the A pin of T-shaped fractional order integration circuit U 7,13rd pin connects the 14th pin by resistance R9, and the 14th pin connects the 9th pin by resistance R11;

1st pin of described multiplier U3 connects the 8th pin of U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R7, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects U2 the 13rd pin by resistance R10, and the 8th pin meets VCC.

The A pin of described 0.9 rank integrating circuit module U5 connects the 9th pin of operational amplifier U1, and the B pin of U5 connects the 8th pin of operational amplifier U1;

The A pin of described 0.9 rank integrating circuit module U6 connects the 6th pin of operational amplifier U1, and the B pin of U6 connects the 7th pin of operational amplifier U1;

The A pin of described 0.9 rank integrating circuit module U7 connects the 9th pin of operational amplifier U2, and the B pin of U7 connects the 8th pin of operational amplifier U2.

The invention has the beneficial effects as follows: adopt T-type structure, design and produce PCB circuit, circuit is made up of six parts, after Part I is connected by four resistance and a potentiometer, form with four Capacitance parallel connections, five parts next are by after four resistance and a potentiometer series connection, be in series with four Capacitance parallel connection parts and form, T-shaped 0.9 rank General integral circuit is made up of first three part, rear three parts are unsettled, adopt in this way realize 0.9 rank fractional order chaotic system circuit, reliability is high, not easily makes mistakes.

Accompanying drawing explanation

Fig. 1 is chain type fractional order integration circuit module internal structure schematic diagram (a) of the present invention, inner actual connection layout (b) and 0.9 rank integrating circuit module map (c).

Fig. 2 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 3 and Fig. 4 is the actual connection layout of circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, see Fig. 1-Fig. 4.

1, a T-shaped general score rank integrating circuit module, is characterized in that being: resistance Rx is in parallel with electric capacity Cx, forms Part I, resistance Ry connects with electric capacity Cy, and form Part II, resistance Rz connects with electric capacity Cz, form Part III, resistance Rw connects with electric capacity Cw, and form Part IV, resistance Ru connects with electric capacity Cu, form Part V, resistance Rv connects with electric capacity Cv, forms Part VI, and Part I and below five parts are for being connected in parallel.

2, a kind of T-shaped general score rank integrating circuit module according to claim 1, it is characterized in that: described resistance Rx is composed in series by potentiometer Rx1 and resistance Rx2, Rx3, Rx4, Rx5, described electric capacity Cx is composed in parallel by electric capacity Cx1, Cx2, Cx3, Cx4; Described resistance Ry is composed in series by potentiometer Ry1 and resistance Ry2, Ry3, Ry4, Ry5, and described electric capacity Cy, by electric capacity Cy1, Cy2, Cy3, Cy4, composes in parallel; Described resistance Rz is composed in series by potentiometer Rz1 and resistance Rz2, Rz3, Rz4, Rz5, and described electric capacity Cz is composed in parallel by electric capacity Cz1, Cz2, Cz3, Cz4; Described resistance Rw is composed in series by potentiometer Rw1 and resistance Rw2, Rw3, Rw4, Rw5, and described electric capacity Cw is composed in parallel by electric capacity Cw1, Cw2, Cw3, Cw4; Described resistance Ru is composed in series by potentiometer Ru1 and resistance Ru2, Ru3, Ru4, Ru5, and described electric capacity Cu is composed in parallel by electric capacity Cu1, Cu2, Cu3, Cu4; Described resistance Rv is composed in series by potentiometer Rv1 and resistance Rv2, Rv3, Rv4, Rv5, and described electric capacity Cv is composed in parallel by electric capacity Cv1, Cv2, Cv3, Cv4.

3, a kind of T-shaped general score rank integrating circuit module according to claim 1, described 0.9 rank integrating circuit module, it is characterized in that: described resistance Rx=63.10M, described potentiometer Rx1=200K, described resistance Rx2=22M, Rx3=22M, Rx4=15M, Rx5=3.9M, described electric capacity Cx=0.4410uF, described electric capacity Cx1=330nF, Cx2=100nF, Cx3=10nF, Cx4=1nF; Described resistance Ry=1.598M, described potentiometer Ry1=1.9K, described resistance Ry2=1.5M, Ry3=91K, Ry4=5.1K, Ry5=0K, described electric capacity Cy=0.4870uF, described electric capacity Cy1=330nF, Cy2=100nF, Cy3=47nF, Cy4=10nF; Described resistance Rz=0.01581M, described potentiometer Rz1=0.71K and described resistance Rz2=10K, Rz3=51K, Rz4=5.1K, Rz5=0K, described electric capacity Cz=0.2937uF, described electric capacity Cz1=220nF, Cz2=68nF, Cz3=4.7nF, Cz4=1nF; Described resistance Rw, Ru, Rv are all unsettled, and described electric capacity Cw, Cu, Cv are all unsettled.

4,0.9 rank based on T-shaped fractional order integration circuit module contain y side L ü chaos system circuit, it is characterized in that:

(1) containing y side L ü chaos system i be:

$\begin{array}{ccc}\left\{\begin{array}{c}\frac{\mathrm{dx}}{\mathrm{dt}}=a(y-x)\\ \frac{\mathrm{dy}}{\mathrm{dt}}=\mathrm{cy}-\mathrm{xz}\\ \frac{\mathrm{dz}}{\mathrm{dt}}=y^2-\mathrm{bz}\end{array}\right.& i& a=36,b=3,c=20\end{array}$

(2) 0.9 rank containing y side L ü chaos system ii are:

$\begin{array}{ccc}\left\{\begin{array}{c}\frac{d^{\mathrm{\α}}x}{{\mathrm{dt}}^{\mathrm{\α}}}=a(y-x)\\ \frac{d^{\mathrm{\α}}y}{{\mathrm{dt}}^{\mathrm{\α}}}=\mathrm{cy}-\mathrm{xz}\\ \frac{d^{\mathrm{\α}}z}{{\mathrm{dt}}^{\mathrm{\α}}}=y^2-\mathrm{bz}\end{array}\right.& \mathrm{ii}& a=36,b=3,c=20,\mathrm{\α}=0.7\end{array}$

(2) x side L ü chaos system i i constructing analog circuit is contained according to 0.9 rank, operational amplifier U1, operational amplifier U2 and resistance and 0.9 rank integrating circuit module U5,0.9 rank integrating circuit module U6,0.9 rank integrating circuit module U7 is utilized to form anti-phase adder and anti-phase 0.9 rank integrator, multiplier U3 and multiplier U4 is utilized to realize multiplying, described operational amplifier U1 and operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 to adopt AD633JN;

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U3, multiplier U4 and 0.9 rank integrating circuit module U5,0.9 rank integrating circuit module U6, described operational amplifier U2 connects multiplier U3 and 0.9 rank integrating circuit module U7, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2;

1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R8 and U1, 2nd pin is connected with the 1st pin by resistance R6, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin connects the A pin of T-shaped fractional order integration circuit U 6, 7th pin connects and exports y, connected with the 13rd pin by resistance R1, connected with the 2nd pin by resistance R5, connect the B pin of T-shaped fractional order integration circuit U 6, connect the 1st of multiplier U4 the, 3 pins, 8th pin connects and exports x, connected with the 9th pin by resistance R4, connect the 1st pin of multiplier U3, connect the B pin of T-shaped fractional order integration circuit U 5, 9th pin connects the A pin of T-shaped fractional order integration circuit U 5, 13rd pin is connected with the 14th pin by resistance R2, 14th pin is connected with the 9th pin by resistance R3,

Described operational amplifier U2 the 1st, 2,6,7 pins are unsettled, 3rd, 5,10,12 pin ground connection, 4th pin meets VCC, and the 11st pin meets VEE, and the 8th pin exports z, connected with the 9th pin by resistance R12, connect the 3rd pin of multiplier U3, connect the B1 pin of T-shaped fractional order integration circuit U 7, the 9th pin connects the A pin of T-shaped fractional order integration circuit U 7,13rd pin connects the 14th pin by resistance R9, and the 14th pin connects the 9th pin by resistance R11;

1st pin of described multiplier U3 connects the 8th pin of U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R7, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects U2 the 13rd pin by resistance R10, and the 8th pin meets VCC.

The A pin of described 0.9 rank integrating circuit module U5 connects the 9th pin of operational amplifier U1, and the B pin of U5 connects the 8th pin of operational amplifier U1;

The A pin of described 0.9 rank integrating circuit module U6 connects the 6th pin of operational amplifier U1, and the B pin of U6 connects the 7th pin of operational amplifier U1;

The A pin of described 0.9 rank integrating circuit module U7 connects the 9th pin of operational amplifier U2, and the B pin of U7 connects the 8th pin of operational amplifier U2.

Resistance R1=R4=2.7k8 Ω in circuit, R2=R3=R6=R8=R9=R11=10k Ω, R5=5k Ω, R7=R10=1k Ω, R12=33.33k Ω.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned citing, and the change that those skilled in the art make in essential scope of the present invention, remodeling, interpolation or replacement, also belong to protection scope of the present invention.

Claims (4)

1. a T-shaped general score rank integrating circuit module, is characterized in that being: resistance Rx is in parallel with electric capacity Cx, forms Part I, resistance Ry connects with electric capacity Cy, and form Part II, resistance Rz connects with electric capacity Cz, form Part III, resistance Rw connects with electric capacity Cw, and form Part IV, resistance Ru connects with electric capacity Cu, form Part V, resistance Rv connects with electric capacity Cv, forms Part VI, and Part I and below five parts are for being connected in parallel.

2. a kind of T-shaped general score rank integrating circuit module according to claim 1, it is characterized in that: described resistance Rx is composed in series by potentiometer Rx1 and resistance Rx2, Rx3, Rx4, Rx5, described electric capacity Cx is composed in parallel by electric capacity Cx1, Cx2, Cx3, Cx4; Described resistance Ry is composed in series by potentiometer Ry1 and resistance Ry2, Ry3, Ry4, Ry5, and described electric capacity Cy, by electric capacity Cy1, Cy2, Cy3, Cy4, composes in parallel; Described resistance Rz is composed in series by potentiometer Rz1 and resistance Rz2, Rz3, Rz4, Rz5, and described electric capacity Cz is composed in parallel by electric capacity Cz1, Cz2, Cz3, Cz4; Described resistance Rw is composed in series by potentiometer Rw1 and resistance Rw2, Rw3, Rw4, Rw5, and described electric capacity Cw is composed in parallel by electric capacity Cw1, Cw2, Cw3, Cw4; Described resistance Ru is composed in series by potentiometer Ru1 and resistance Ru2, Ru3, Ru4, Ru5, and described electric capacity Cu is composed in parallel by electric capacity Cu1, Cu2, Cu3, Cu4; Described resistance Rv is composed in series by potentiometer Rv1 and resistance Rv2, Rv3, Rv4, Rv5, and described electric capacity Cv is composed in parallel by electric capacity Cv1, Cv2, Cv3, Cv4.

3. a kind of T-shaped general score rank integrating circuit module according to claim 1, described 0.9 rank integrating circuit module, it is characterized in that: described resistance Rx=63.10M, described potentiometer Rx1=200K, described resistance Rx2=22M, Rx3=22M, Rx4=15M, Rx5=3.9M, described electric capacity Cx=0.4410uF, described electric capacity Cx1=330nF, Cx2=100nF, Cx3=10nF, Cx4=1nF; Described resistance Ry=1.598M, described potentiometer Ry1=1.9K, described resistance Ry2=1.5M, Ry3=91K, Ry4=5.1K, Ry5=0K, described electric capacity Cy=0.4870uF, described electric capacity Cy1=330nF, Cy2=100nF, Cy3=47nF, Cy4=10nF; Described resistance Rz=0.01581M, described potentiometer Rz1=0.71K and described resistance Rz2=10K, Rz3=51K, Rz4=5.1K, Rz5=0K, described electric capacity Cz=0.2937uF, described electric capacity Cz1=220nF, Cz2=68nF, Cz3=4.7nF, Cz4=1nF; Described resistance Rw, Ru, Rv are all unsettled, and described electric capacity Cw, Cu, Cv are all unsettled.

4. 0.9 rank based on T-shaped fractional order integration circuit module contain y side L ü chaos system circuit, it is characterized in that:

(1) containing y side L ü chaos system i be:

$\left\{\begin{array}{c}\frac{\mathrm{dx}}{\mathrm{dt}}=a(y-x)\\ \frac{\mathrm{dy}}{\mathrm{dt}}=\mathrm{cy}-\mathrm{xz}\\ \frac{\mathrm{dz}}{\mathrm{dt}}=y^2-\mathrm{bz}\end{array}\right.,i,a=36,b=3,c=20$

(2) 0.9 rank containing y side L ü chaos system ii are:

$\left\{\begin{array}{c}\frac{d^{\mathrm{\α}}x}{{\mathrm{dt}}^{\mathrm{\α}}}=a(y-x)\\ \frac{d^{\mathrm{\α}}y}{{\mathrm{dt}}^{\mathrm{\α}}}=\mathrm{cy}-\mathrm{xz}\\ \frac{d^{\mathrm{\α}}z}{{\mathrm{dt}}^{\mathrm{\α}}}=y^2-\mathrm{bz}\end{array}\right.,\mathrm{ii},a=36,b=3,c=20,\mathrm{\α}=0.7$

(2) x side L ü chaos system ii constructing analog circuit is contained according to 0.9 rank, operational amplifier U1, operational amplifier U2 and resistance and 0.9 rank integrating circuit module U5,0.9 rank integrating circuit module U6,0.9 rank integrating circuit module U7 is utilized to form anti-phase adder and anti-phase 0.9 rank integrator, multiplier U3 and multiplier U4 is utilized to realize multiplying, described operational amplifier U1 and operational amplifier U2 adopts LF347N, described multiplier U3 and multiplier U4 to adopt AD633JN;

Described operational amplifier U1 concatenation operation amplifier U2, multiplier U3, multiplier U4 and 0.9 rank integrating circuit module U5,0.9 rank integrating circuit module U6, described operational amplifier U2 connects multiplier U3 and 0.9 rank integrating circuit module U7, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2;

1st pin of described operational amplifier U1 is connected by the 6th pin of resistance R8 and U1, 2nd pin is connected with the 1st pin by resistance R6, 3rd, 5, 10, 12 pin ground connection, 4th pin meets VCC, 11st pin meets VEE, 6th pin connects the A pin of T-shaped fractional order integration circuit U 6, 7th pin connects and exports y, connected with the 13rd pin by resistance R1, connected with the 2nd pin by resistance R5, connect the B pin of T-shaped fractional order integration circuit U 6, connect the 1st of multiplier U4 the, 3 pins, 8th pin connects and exports x, connected with the 9th pin by resistance R4, connect the 1st pin of multiplier U3, connect the B pin of T-shaped fractional order integration circuit U 5, 9th pin connects the A pin of T-shaped fractional order integration circuit U 5, 13rd pin is connected with the 14th pin by resistance R2, 14th pin is connected with the 9th pin by resistance R3,

Described operational amplifier U2 the 1st, 2,6,7 pins are unsettled, 3rd, 5,10,12 pin ground connection, 4th pin meets VCC, and the 11st pin meets VEE, and the 8th pin exports z, connected with the 9th pin by resistance R12, connect the 3rd pin of multiplier U3, connect the B1 pin of T-shaped fractional order integration circuit U 7, the 9th pin connects the A pin of T-shaped fractional order integration circuit U 7,13rd pin connects the 14th pin by resistance R9, and the 14th pin connects the 9th pin by resistance R11;

1st pin of described multiplier U3 connects the 8th pin of U1, and the 3rd pin connects the 8th pin of U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects U1 the 6th pin by resistance R7, and the 8th pin meets VCC;

Described multiplier U4 the 1st, 3 pins connect the 7th pin of U1, the equal ground connection of the 2nd, 4,6 pin, the 5th pin meets VEE, and the 7th pin connects U2 the 13rd pin by resistance R10, and the 8th pin meets VCC.

The A pin of described 0.9 rank integrating circuit module U5 connects the 9th pin of operational amplifier U1, and the B pin of U5 connects the 8th pin of operational amplifier U1;

The A pin of described 0.9 rank integrating circuit module U6 connects the 6th pin of operational amplifier U1, and the B pin of U6 connects the 7th pin of operational amplifier U1;

The A pin of described 0.9 rank integrating circuit module U7 connects the 9th pin of operational amplifier U2, and the B pin of U7 connects the 8th pin of operational amplifier U2.