WO2015123797A1 - CLASSICAL Lü CHAOTIC SYSTEM SWITCHING METHOD AND CIRCUIT WITH DIFFERENTFRACTIONAL ORDERS - Google Patents

CLASSICAL Lü CHAOTIC SYSTEM SWITCHING METHOD AND CIRCUIT WITH DIFFERENTFRACTIONAL ORDERS Download PDF

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Publication number
WO2015123797A1
WO2015123797A1 PCT/CN2014/000404 CN2014000404W WO2015123797A1 WO 2015123797 A1 WO2015123797 A1 WO 2015123797A1 CN 2014000404 W CN2014000404 W CN 2014000404W WO 2015123797 A1 WO2015123797 A1 WO 2015123797A1
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pin
operational amplifier
resistor
capacitor
multiplier
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PCT/CN2014/000404
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French (fr)
Chinese (zh)
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梅增霞
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梅增霞
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09C—CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
    • G09C1/00—Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system

Definitions

  • the invention relates to a chaotic system and a circuit implementation, in particular to a classical Lii chaotic switching system method and circuit with different fractional orders.
  • the methods and circuits for switching chaotic systems mainly include switching between different linear or nonlinear terms in chaotic systems, and fractional order based on the two switching modes.
  • the system switching method and circuit have not been proposed yet.
  • the present invention proposes a novel Lii chaotic switching system method and circuit with different fractional orders.
  • the present invention proposes a novel switching method and circuit for a novel chaotic system, which adds The type of chaotic system switching and the application of this chaotic system to engineering practice provide a new idea.
  • the technical problem to be solved by the present invention is to provide a classical Lii chaotic switching system method and circuit with different fractional orders.
  • the present invention adopts the following technical means to achieve the object of the invention:
  • a classical Li chaotic switching system method with different fractional orders characterized in that it comprises the following steps: (1) The equation of the Lii chaotic system i is:
  • the operational amplifier U2 is connected to a multiplier U3 and an analog switch U5.
  • the multiplier U3 is connected to an operational amplifier U1, the multiplier U4 Connecting an operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1.
  • 12-pin ground the 4th pin is connected to VCC
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyll through the resistor Ryll, the parallel connection of the resistor Ryl2 and the capacitor Cyl2, and then the resistor Ryl3 In parallel with the capacitor Cyl3, connect the 7th pin of the analog switch U5, connect the resistor Ry21 and the capacitor Cy21 in parallel, connect the resistor Ry22 and the capacitor Cy22 in parallel, and then connect the resistor Ry23 and the capacitor Cy23 in parallel, then connect the analog
  • the fifth pin of the switch U5, the seventh pin of the operational amplifier U1 is connected to the thirteenth pin of the operational amplifier U1 via the resistor R2, the second pin of the operational amplifier U1
  • the 8th pin of the operational amplifier U1 is connected to the ninth pin of the operational amplifier U1 via the resistor R5, to the second pin of the operational amplifier U2, to the first pin of the multiplier U3, and to the first pin of the multiplier U4. lead The 9th pin of the operational amplifier U1 is connected in parallel with the capacitor Cx11 through the resistor Rx11, and the parallel connection between the resistor Rxl2 and the capacitor Cxl2, and then connected in parallel with the resistor Rxl3 and the capacitor Cxl3, and then connected to the second pin of the analog switch U5.
  • resistor Rx21 and the capacitor Cx21 In parallel with the resistor Rx21 and the capacitor Cx21, connect the resistor Rx22 and the capacitor Cx22 in parallel, and then connect the resistor Rx23 and the capacitor Cx23 in parallel, then connect to the fourth pin of the analog switch U5, and the 14th pin of the operational amplifier U1 passes.
  • the resistor R1 is connected to the 13th pin of the operational amplifier U1, and is connected to the 9th pin of the operational amplifier U1 through the resistor R6;
  • the sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12 pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of the resistors R13 and R14, connected to the 8th and 9th pins of the analog switch U5 through R13, and the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R11.
  • the third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czll through the resistor Rzll, and the parallel connection between the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the capacitor Rzl3 and the capacitor Czl3, and then connected to the analog switch U5.
  • the 10th pin, in parallel with the capacitor R Z21 and the capacitor C Z 21 is connected in parallel with the capacitor Rz22 and the capacitor Cz22, and then connected in parallel with the resistor Rz23 and the capacitor Cz23, and then connected to the analog switch U5.
  • 12-pin, the 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
  • the first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the seventh pin of the operational amplifier U1.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
  • the first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are floating, the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier.
  • the 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2.
  • a Lii chaotic switching system circuit with different fractional orders characterized in that an operational amplifier III, an operational amplifier U2, a resistor and a capacitor are used to form an inverting adder and a fractional-order inverse integrator of different orders is utilized.
  • the multiplier U3 and the multiplier U4 implement multiplication, and the analog switch U5 is used to realize the selection and output of the analog signal.
  • the operational amplifier U1 and the operational amplifier U2 adopt LF347D
  • the multiplier U3 and the multiplier U4 adopt AD633JN
  • the analog switch U5 adopts ADG888
  • the operational amplifier U1 is connected to a multiplier U3, a multiplier U4 and an analog switch U5.
  • the operational amplifier U2 is connected to a multiplier U3 and an analog switch U5.
  • the multiplier U3 is connected to an operational amplifier U1, the multiplier U4 is connected to the operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1.
  • 12-pin ground the 4th pin is connected to VCC
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyl l through the resistor Ryl l
  • the parallel connection of the resistor Ryl2 and the capacitor Cyl2 is connected.
  • the resistor Ryl3 After the resistor Ryl3 is connected in parallel with the capacitor Cyl3, it is connected to the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, and connected in parallel with the resistor Ry22 and the capacitor Cy22, and then connected in parallel with the resistor Ry23 and the capacitor Cy23, and then Connect the fifth pin of analog switch U5, the seventh pin of operational amplifier U1 is connected to the 13th pin of operational amplifier U1 through resistor R2, the second pin of operational amplifier U1 through resistor R4, and the second of multiplier M1.
  • the 3 pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R5, the second pin of the operational amplifier U2, the first pin of the multiplier U3, and the multiplier U4.
  • the first pin, the ninth pin of the operational amplifier U1 passes through the resistor Rxl l
  • the fourth pin of the analog switch U5 is connected, and the 14th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R1, and is connected to the 9th pin of the operational amplifier U1 through the
  • the sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12 pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of resistors R13 and R14, connected to the 8th and 9th pins of analog switch U5 through R13, and the 8th pin of operational amplifier U2 is connected to the 9th pin of operational amplifier U2 through resistor R11.
  • the third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czl l through the resistor Rzl l, and the parallel connection of the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the resistor Rzl3 and the capacitor Czl 3, and then connected
  • the 10th pin of the analog switch U5 is connected in parallel with the capacitor C Z 21 through the resistor Rz21, and the parallel connection of the resistor Rz22 and the capacitor Cz22, and then connected in parallel with the capacitor Rz23 and the capacitor Cz23, and then connected to the 12th pin of the analog switch U5.
  • the 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
  • the first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the seventh pin of the operational amplifier U1.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
  • the first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are left floating, and the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected.
  • the seventh pin of amplifier U1, the eleventh pin is connected to the eighth pin of operational amplifier U2.
  • a novel switching method and circuit for a novel chaotic system is proposed, which provides a new idea for increasing the type of chaotic system switching and the application of the chaotic system to engineering practice.
  • FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.
  • a classical Lii chaotic switching system method with different fractional orders characterized in that it comprises the following steps:
  • the operational amplifier U1 is connected to a multiplier U3, a multiplier U4 and an analog switch U5, the operational amplifier U2 is connected to a multiplier U3 and an analog switch U5, and the multiplier U3 is connected to an operational amplifier U1, the multiplier U4 Connecting an operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
  • the first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1.
  • 12-pin ground the 4th pin is connected to VCC
  • the 11th pin is connected to VEE
  • the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyll through the resistor Ryll, the parallel connection of the resistor Ryl2 and the capacitor Cyl2, and then the resistor Ryl3 In parallel with the capacitor Cyl3, connect the 7th pin of the analog switch U5, connect the resistor Ry21 and the capacitor Cy21 in parallel, connect the resistor Ry22 and the capacitor Cy22 in parallel, and then connect the resistor Ry23 and the capacitor Cy23 in parallel, then connect the analog Pin 5 of switch U5, 7th lead of operational amplifier U1
  • the pin is connected to the 13th pin of the operational amplifier U1 through the resistor R2, the second pin of the operational amplifier U1 through
  • the 9th pin of amplifier U1 is connected to the 2nd pin of the operational amplifier U2, the 1st pin of the multiplier U3 is connected, the 1st pin of the multiplier U4 is connected, and the 9th pin of the operational amplifier U1 passes the resistor Rxl l In parallel with the capacitor Cxl l, connect the resistor Rxl2 and the capacitor Cxl 2 in parallel, and then connect the resistor Rxl3 and the capacitor Cxl3 in parallel, then connect the second pin of the analog switch U5, connect the resistor Rx21 and the capacitor Cx21 in parallel, connect the resistor Parallel connection of Rx22 and capacitor Cx22, followed by parallel connection of resistor Rx23 and capacitor Cx23, and then connected to pin 4 of analog switch U5.
  • Pin 14 of operational amplifier ill is connected to pin 13 of operational amplifier U1 through resistor R1. Connected to the ninth pin of the operational amplifier U1 through a resistor R6;
  • the sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and twelve pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of resistors R13 and R14, connected to the 8th and 9th pins of analog switch U5 through R13, and the 8th pin of operational amplifier U2 is connected to the 9th pin of operational amplifier U2 through resistor R11.
  • the third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czl l through the resistor Rzl l, and the parallel connection of the resistor Rzl2 and the capacitor Czl 2, and then connected in parallel with the resistor Rzl3 and the capacitor Cz l3, and then Connect the 10th pin of the analog switch U5, connect the resistor Rz21 and the capacitor Cz21 in parallel, connect the resistor Rz22 and the capacitor Cz22 in parallel, connect the resistor Rz23 and the capacitor Cz23 in parallel, and then connect the 12th pin of the analog switch U5.
  • the 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
  • the first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier m, the third pin is connected to the seventh pin of the operational amplifier U1, and the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
  • the first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are floating, the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier.
  • the 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2. .
  • a Lii chaotic switching system circuit with different fractional orders characterized in that an operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used to form an inverting adder and a fractional-order inverse integrator of different orders is utilized.
  • the multiplier U3 and the multiplier U4 implement a multiplication operation, and the analog switch U5 is used to realize the selective output of the analog signal.
  • the operational amplifier U1 and the operational amplifier U2 adopt LF347D
  • the multiplier U3 and the multiplier U4 adopt AD633JN, and the analog is turned on.
  • the U5 is connected to the U5, the operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analog switch U5, the operational amplifier U2 is connected to the multiplier U3 and the analog switch U5, and the multiplier U3 is connected to the operational amplifier U1, the multiplication
  • the U4 is connected to the operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
  • the first pin of the operational amplifier m is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1. 12-pin ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyl l through the resistor Ryl l, and the parallel connection of the resistor Ryl2 and the capacitor Cyl2 is connected.
  • the resistor Ryl3 After the resistor Ryl3 is connected in parallel with the capacitor Cyl3, it is connected to the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, and connected in parallel with the resistor Ry22 and the capacitor Cy22, and then connected in parallel with the resistor Ry23 and the capacitor Cy23, and then Connect the fifth pin of analog switch U5, the seventh pin of operational amplifier U1 is connected to the 13th pin of operational amplifier U1 through resistor R2, the second pin of operational amplifier U1 through resistor R4, and the second pin of multiplier U4
  • the 3 pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R5, the second pin of the operational amplifier U2, the first pin of the multiplier U3, and the multiplier U4.
  • the 9th pin of the operational amplifier U1 is connected in parallel with the capacitor Cxl l through the resistor Rxl l, and the parallel connection of the resistor Rxl2 and the capacitor Cxl2, and then connected in parallel with the resistor Rxl3 and the capacitor Cxl3, and then connected to the second lead of the analog switch U5.
  • the pin is connected in parallel with the capacitor Cx21 through the resistor Rx21, and the parallel connection between the resistor Rx22 and the capacitor Cx22, and then connected in parallel with the resistor Rx23 and the capacitor Cx23, and then connected to the fourth pin of the analog switch U5, the 14th pin of the operational amplifier U1.
  • the sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12 pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of resistors R13 and R14, connected to the 8th and 9th pins of analog switch U5 through R13, and the 8th pin of operational amplifier U2 is connected to the 9th pin of operational amplifier U2 through resistor R11.
  • the third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czl1 through the resistor Rzl l, and the parallel connection of the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the resistor Rzl3 and the capacitor Czl3, and then connected to the analog
  • the 10th pin of the switch U5 is connected in parallel with the capacitor Cz21 through the resistor Rz21 and the capacitor Cz21. Then, the parallel connection between the resistor Rz23 and the capacitor Cz23 is connected, and then the 12th pin of the analog switch U5 is connected, and the operational amplifier is connected.
  • the 14th pin of U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
  • the first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2.
  • the second, fourth, and sixth pins are grounded, and the fifth pin is connected.
  • VEE the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
  • the first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the operational amplifier U1.
  • the 7th pin, the 2nd, 4th, and 6th pins are all grounded, the 5th pin is connected to VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
  • the first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are floating, the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier.
  • the 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2.

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Abstract

Provided are a classical Lü chaotic system switching method and circuit with different fractional orders. An operational amplifier U1, an operational amplifier U2 and a resistor and a capacitor are utilized for constituting an inverting adder and an inverting integrator with different fractional orders, a multiplier U3 and a multiplier U4 are utilized for achieving multiplication operation, and an analogue switch U5 is utilized for achieving selective output of analogue signals. LF347Ds are adopted for the operational amplifier U1 and the operational amplifier U2, AD633JNs are adopted for the multiplier U3 and the multiplier U4, and an ADG888 is adopted for the analogue switch U5. The operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analogue switch U5, the operational amplifier U2 is connected to the multiplier U3 and the analogue switch U5, the multiplier U3 is connected to the operational amplifier U1, the multiplier U4 is connected to the operational amplifier U2, and the analogue switch U5 is connected to the operational amplifier U1 and the operational amplifier U2. Proposed are a novel switching method and circuit for a novel chaotic system, which provides a new thought for increasing chaotic system switching types and applying such a chaotic system to engineering practices.

Description

一种分数阶次不同的经典 Lii混沌切换系统方法及电路  Method and circuit for classical Lii chaotic switching system with different fractional orders
技术领域 Technical field
本发明涉及一个混沌系统及电路实现， 特别涉及一种分数阶次不同的经典 Lii混沌切换 系统方法及电路。  The invention relates to a chaotic system and a circuit implementation, in particular to a classical Lii chaotic switching system method and circuit with different fractional orders.
背景技术 Background technique
目前， 己有的切换混沌系统的方法与电路主要包括混沌系统中不同线性项或非线性项 的之间的切换， 以及基于这 2种切换模式的分数阶形式， 关于不同阶次的分数阶混沌系统的 切换方法及电路还没有被提出， 本发明提出了一种分数阶次不同的经典 Lii混沌切换系统方 法及电路， 本发明提出了一个新型的混沌系统的新型切换方法及电路， 这对增加混沌系统切 换的类型及这种混沌系统应用于工程实践提供了一种新思路。  At present, the methods and circuits for switching chaotic systems mainly include switching between different linear or nonlinear terms in chaotic systems, and fractional order based on the two switching modes. The system switching method and circuit have not been proposed yet. The present invention proposes a novel Lii chaotic switching system method and circuit with different fractional orders. The present invention proposes a novel switching method and circuit for a novel chaotic system, which adds The type of chaotic system switching and the application of this chaotic system to engineering practice provide a new idea.
发明内容 Summary of the invention
本发明要解决的技术问题是提供一种分数阶次不同的经典 Lii混沌切换系统方法及电 路， 本发明采用如下技术手段实现发明目的：  The technical problem to be solved by the present invention is to provide a classical Lii chaotic switching system method and circuit with different fractional orders. The present invention adopts the following technical means to achieve the object of the invention:
1、 一种分数阶次不同的经典 Li混沌切换系统方法， 其特征是在于， 包括以下步骤： ( 1 ) Lii混沌系统 i的方程为：  A classical Li chaotic switching system method with different fractional orders, characterized in that it comprises the following steps: (1) The equation of the Lii chaotic system i is:
dxl dt = ay - x)  Dxl dt = ay - x)
dy I dt = cy— xz a - 36, b = 3,c = 22  Dy I dt = cy— xz a - 36, b = 3,c = 22
dz / dt = xy-bz  Dz / dt = xy-bz
(2) 0.9阶 Lii混沌系统 ii的方程为:
Figure imgf000002_0001
(2) The equation of the 0.9-order Lii chaotic system ii is:
Figure imgf000002_0001
(3) 0.1阶 Lii混沌系统 i i i的方程为:  (3) The order of the 0.1-order Lii chaotic system i i i is:
d x I dt =a y-x)  d x I dt = a y-x)
d0Ay / dt01 = cy-xz a = 36, b = 3,c = 22 d 0A y / dt 01 = cy-xz a = 36, b = 3, c = 22
daiz/dt01 = xy-bz d ai z/dt 01 = xy-bz
(4)构造切换函数 g = f(x)，其中 f(x)的表达式 iv为:
Figure imgf000002_0002
(4) Construct a switching function g = f(x), where the expression iv of f(x) is:
Figure imgf000002_0002
(5)由 ii、 iii和 iv构造一种分数阶次不同的 Lii混沌切换系统 V为: dqx I dtq― a(y― x) (5) Construct a Lii chaotic switching system V with different fractional orders from ii, iii and iv: d q x I dt q ― a(y― x)
dq y I dtq—cy-xz a - 36,b = 3,c = 22 , q = /(x)二 d q y I dt q —cy-xz a - 36,b = 3,c = 22 , q = /(x) two
dq z I d 二 — fe d q z I d di- fe
(6)根据分数阶次不同的 Lii混沌切换系统 v构造模拟电路系统， 利用运算放大器 Ul、 运算放 大器 U2及电阻和电容构成反相加法器和不同阶次的分数阶反相积分器， 利用乘法器 U3和乘 法器 U4实现乘法运算， 利用模拟开关 U5实现模拟信号的选择输出， 所述运算放大器 U1和 运算放大器 U2采用 LF347D, 所述乘法器 U3和乘法器 U4采用 AD633JN, 所述模拟开关 U5采 用 ADG888, 所述运算放大器 U1连接乘法器 113、 乘法器 U4和模拟开关 U5, 所述运算放大器 U2连接乘法器 U3和模拟开关 U5， 所述乘法器 U3连接运算放大器 Ul， 所述乘法器 U4连接 运算放大器 U2， 所述模拟开关 U5连接运算放大器 U1和运算放大器 U2; (6) Constructing an analog circuit system based on the Lii chaotic switching system with different fractional orders, using the operational amplifier Ul, the operational amplifier U2, and the resistor and capacitor to form an inverting adder and a fractional-order inverting integrator of different orders, using multiplication The U3 and the multiplier U4 implement a multiplication operation, and the analog output of the analog signal is implemented by the analog switch U5. The operational amplifier U1 and the operational amplifier U2 are LF347D, and the multiplier U3 and the multiplier U4 are AD633JN, and the analog switch U5 is used. Using ADG888, the operational amplifier U1 is connected to a multiplier 113, a multiplier U4 and an analog switch U5. The operational amplifier U2 is connected to a multiplier U3 and an analog switch U5. The multiplier U3 is connected to an operational amplifier U1, the multiplier U4 Connecting an operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
所述运算放大器 U1的第 1引脚通过电阻 R3与运算放大器 U1的第 2引脚相接， 通过电 阻 R7与运算放大器 U1的第 6引脚相接， 运算放大器 U1的第 3、 5、 10、 12引脚接地， 第 4 引脚接 VCC, 第 11引脚接 VEE， 运算放大器 U1的第 6引脚通过电阻 Ryll与电容 Cyll 的并 联， 接电阻 Ryl2与电容 Cyl2的并联， 再接电阻 Ryl3与电容 Cyl3的并联后， 再接模拟开关 U5的第 7引脚， 通过电阻 Ry21与电容 Cy21 的并联， 接电阻 Ry22与电容 Cy22的并联， 再 接电阻 Ry23与电容 Cy23的并联后， 再接模拟开关 U5的第 5引脚， 运算放大器 U1的第 7引 脚通过电阻 R2接运算放大器 U1的第 13引脚， 通过电阻 R4接运算放大器 U1的第 2引脚， 接乘法器 U4的第 3引脚， 运算放大器 U1的第 8引脚通过电阻 R5接运算放大器 U1的第 9引 脚， 接运算放大器 U2的第 2引脚， 接乘法器 U3的第 1引脚， 接乘法器 U4的第 1引脚， 运 算放大器 U1的第 9引脚通过电阻 Rxll与电容 Cxll的并联， 接电阻 Rxl2与电容 Cxl2的并 联， 再接电阻 Rxl3与电容 Cxl3的并联后， 再接模拟幵关 U5的第 2引脚， 通过电阻 Rx21与 电容 Cx21 的并联， 接电阻 Rx22与电容 Cx22 的并联， 再接电阻 Rx23 与电容 Cx23 的并联 后， 再接模拟开关 U5的第 4 引脚， 运算放大器 U1 的第 14引脚通过电阻 R1接运算放大器 U1的第 13引脚， 通过电阻 R6接运算放大器 U1的第 9引脚；  The first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1. 12-pin ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyll through the resistor Ryll, the parallel connection of the resistor Ryl2 and the capacitor Cyl2, and then the resistor Ryl3 In parallel with the capacitor Cyl3, connect the 7th pin of the analog switch U5, connect the resistor Ry21 and the capacitor Cy21 in parallel, connect the resistor Ry22 and the capacitor Cy22 in parallel, and then connect the resistor Ry23 and the capacitor Cy23 in parallel, then connect the analog The fifth pin of the switch U5, the seventh pin of the operational amplifier U1 is connected to the thirteenth pin of the operational amplifier U1 via the resistor R2, the second pin of the operational amplifier U1 via the resistor R4, and the third lead of the multiplier U4. The 8th pin of the operational amplifier U1 is connected to the ninth pin of the operational amplifier U1 via the resistor R5, to the second pin of the operational amplifier U2, to the first pin of the multiplier U3, and to the first pin of the multiplier U4. lead The 9th pin of the operational amplifier U1 is connected in parallel with the capacitor Cx11 through the resistor Rx11, and the parallel connection between the resistor Rxl2 and the capacitor Cxl2, and then connected in parallel with the resistor Rxl3 and the capacitor Cxl3, and then connected to the second pin of the analog switch U5. In parallel with the resistor Rx21 and the capacitor Cx21, connect the resistor Rx22 and the capacitor Cx22 in parallel, and then connect the resistor Rx23 and the capacitor Cx23 in parallel, then connect to the fourth pin of the analog switch U5, and the 14th pin of the operational amplifier U1 passes. The resistor R1 is connected to the 13th pin of the operational amplifier U1, and is connected to the 9th pin of the operational amplifier U1 through the resistor R6;
所述运算放大器 U2的第 6、 7引脚悬空， 所述运算放大器 U2的第 3、 5、 10、 12引脚 接地， 第 4引脚接 VCC， 第 11 引脚接 VEE， 运算放大器 U2的第 1引脚通过电阻 R13和 R14 的串联接地，通过 R13接模拟开关 U5的第 8、 9引脚， 运算放大器 U2 的第 8 引脚通过电阻 R11接运算放大器 U2的第 9引脚， 接乘法器 U3的第 3引脚， 运算放大器 U2的第 9引脚通 过电阻 Rzll与电容 Czll 的并联， 接电阻 Rzl2与电容 Czl2的并联， 再接电阻 Rzl3与电容 Czl3的并联后， 再接模拟开关 U5的第 10引脚， 通过电阻 Rz21与电容 CZ21 的并联， 接电 阻 Rz22与电容 Cz22的并联， 再接电阻 Rz23与电容 Cz23的并联后， 再接模拟开关 U5的第 12引脚， 运算放大器 U2的第 14引脚通过电阻 R10接运算放大器 U2的第 13引脚， 通过电 阻 R12接运算放大器 U2的第 9引脚； The sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12 pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of the resistors R13 and R14, connected to the 8th and 9th pins of the analog switch U5 through R13, and the 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R11. The third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czll through the resistor Rzll, and the parallel connection between the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the capacitor Rzl3 and the capacitor Czl3, and then connected to the analog switch U5. The 10th pin, in parallel with the capacitor R Z21 and the capacitor C Z 21 , is connected in parallel with the capacitor Rz22 and the capacitor Cz22, and then connected in parallel with the resistor Rz23 and the capacitor Cz23, and then connected to the analog switch U5. 12-pin, the 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
所述乘法器 U3的第 1 引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U2的 第 8引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R8接运算放大器 U1的第 6引脚， 第 8引脚接 VCC;  The first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2. The second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
所述乘法器 U4的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U1的 第 7引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R9接运算放大器 U2的第 13引脚， 第 8引脚接 VCC;  The first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the seventh pin of the operational amplifier U1. The second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
所述模拟开关 U5的第 1 引脚接 VCC，第 16 引脚接地， 第 13、 14、 15引脚悬空， 第 3 引脚接运算放大器 U1的第 8引脚， 第 6引脚接运算放大器 U1的第 7引脚， 第 11引脚接运 算放大器 U2的第 8引脚。  The first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are floating, the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier. The 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2.
2、 一种分数阶次不同的 Lii混沌切换系统电路， 其特征是在于， 利用运算放大器 III、 运算放大器 U2 及电阻和电容构成反相加法器和不同阶次的分数阶反相积分器， 利用乘法器 U3和乘法器 U4实现乘法运算， 利用模拟开关 U5 实现模拟信号的选择输出， 所述运算放大 器 U1和运算放大器 U2采用 LF347D, 所述乘法器 U3和乘法器 U4采用 AD633JN, 所述模拟开 关 U5采用 ADG888, 所述运算放大器 U1连接乘法器 U3、 乘法器 U4和模拟开关 U5， 所述运 算放大器 U2连接乘法器 U3和模拟开关 U5, 所述乘法器 U3连接运算放大器 U1， 所述乘法器 U4连接运算放大器 U2， 所述模拟开关 U5连接运算放大器 U1和运算放大器 U2;  2. A Lii chaotic switching system circuit with different fractional orders, characterized in that an operational amplifier III, an operational amplifier U2, a resistor and a capacitor are used to form an inverting adder and a fractional-order inverse integrator of different orders is utilized. The multiplier U3 and the multiplier U4 implement multiplication, and the analog switch U5 is used to realize the selection and output of the analog signal. The operational amplifier U1 and the operational amplifier U2 adopt LF347D, and the multiplier U3 and the multiplier U4 adopt AD633JN, the analog switch U5 adopts ADG888, and the operational amplifier U1 is connected to a multiplier U3, a multiplier U4 and an analog switch U5. The operational amplifier U2 is connected to a multiplier U3 and an analog switch U5. The multiplier U3 is connected to an operational amplifier U1, the multiplier U4 is connected to the operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
所述运算放大器 U1的第 1引脚通过电阻 R3与运算放大器 U1的第 2引脚相接， 通过电 阻 R7与运算放大器 U1的第 6引脚相接， 运算放大器 U1的第 3、 5、 10、 12引脚接地， 第 4 引脚接 VCC, 第 11引脚接 VEE， 运算放大器 U1的第 6引脚通过电阻 Ryl l与电容 Cyl l的并 联， 接电阻 Ryl2与电容 Cyl2的并联， 再接电阻 Ryl3与电容 Cyl3的并联后， 再接模拟开关 U5的第 7引脚， 通过电阻 Ry21与电容 Cy21 的并联， 接电阻 Ry22与电容 Cy22的并联， 再 接电阻 Ry23与电容 Cy23的并联后， 再接模拟开关 U5的第 5引脚， 运算放大器 U1的第 7引 脚通过电阻 R2接运算放大器 U1的第 13引脚， 通过电阻 R4接运算放大器 U1的第 2引脚， 接乘法器 M的第 3引脚， 运算放大器 U1的第 8引脚通过电阻 R5接运算放大器 U1的第 9引 脚， 接运算放大器 U2的第 2引脚， 接乘法器 U3的第 1引脚， 接乘法器 U4的第 1引脚， 运 算放大器 U1的第 9引脚通过电阻 Rxl l与电容 Cxl l的并联， 接电阻 Rxl2与电容 Cxl2的并 联， 再接电阻 Rxl3与电容 Cxl3的并联后， 再接模拟开关 U5的第 2引脚， 通过电阻 Rx21与 电容 Cx21 的并联， 接电阻 Rx22与电容 Cx22 的并联， 再接电阻 Rx23与电容 Cx23 的并联 后， 再接模拟开关 U5的第 4引脚， 运算放大器 U1 的第 14引脚通过电阻 R1接运算放大器 U1的第 13引脚， 通过电阻 R6接运算放大器 U1的第 9引脚； . The first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1. 12-pin ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyl l through the resistor Ryl l, and the parallel connection of the resistor Ryl2 and the capacitor Cyl2 is connected. After the resistor Ryl3 is connected in parallel with the capacitor Cyl3, it is connected to the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, and connected in parallel with the resistor Ry22 and the capacitor Cy22, and then connected in parallel with the resistor Ry23 and the capacitor Cy23, and then Connect the fifth pin of analog switch U5, the seventh pin of operational amplifier U1 is connected to the 13th pin of operational amplifier U1 through resistor R2, the second pin of operational amplifier U1 through resistor R4, and the second of multiplier M1. The 3 pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R5, the second pin of the operational amplifier U2, the first pin of the multiplier U3, and the multiplier U4. The first pin, the ninth pin of the operational amplifier U1 passes through the resistor Rxl l The parallel connection of the capacitor Cxl l, the parallel connection of the resistor Rxl2 and the capacitor Cxl2, and then the parallel connection of the resistor Rxl3 and the capacitor Cxl3, and then connected to the second pin of the analog switch U5, through the parallel connection of the resistor Rx21 and the capacitor Cx21, the resistor Rx22 and Parallel connection of capacitor Cx22, followed by parallel connection of resistor Rx23 and capacitor Cx23 After that, the fourth pin of the analog switch U5 is connected, and the 14th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R1, and is connected to the 9th pin of the operational amplifier U1 through the resistor R6.
所述运算放大器 U2的第 6、 7引脚悬空， 所述运算放大器 U2的第 3、 5、 10、 12引脚 接地， 第 4引脚接 VCC， 第 11 引脚接 VEE， 运算放大器 U2的第 1 引脚通过电阻 R13和 R14 的串联接地，通过 R13接模拟开关 U5的第 8、 9 引脚， 运算放大器 U2的第 8引脚通过电阻 R11接运算放大器 U2的第 9引脚， 接乘法器 U3的第 3引脚， 运算放大器 U2的第 9引脚通 过电阻 Rzl l与电容 Czl l 的并联， 接电阻 Rzl2与电容 Czl2的并联， 再接电阻 Rzl3与电容 Czl 3的并联后， 再接模拟开关 U5的第 10引脚， 通过电阻 Rz21与电容 CZ21 的并联， 接电 阻 Rz22与电容 Cz22的并联， 再接电阻 Rz23与电容 Cz23的并联后， 再接模拟开关 U5的第 12引脚， 运算放大器 U2的第 14引脚通过电阻 R10接运算放大器 U2的第 13引脚， 通过电 阻 R12接运算放大器 U2的第 9引脚； The sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12 pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of resistors R13 and R14, connected to the 8th and 9th pins of analog switch U5 through R13, and the 8th pin of operational amplifier U2 is connected to the 9th pin of operational amplifier U2 through resistor R11. The third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czl l through the resistor Rzl l, and the parallel connection of the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the resistor Rzl3 and the capacitor Czl 3, and then connected The 10th pin of the analog switch U5 is connected in parallel with the capacitor C Z 21 through the resistor Rz21, and the parallel connection of the resistor Rz22 and the capacitor Cz22, and then connected in parallel with the capacitor Rz23 and the capacitor Cz23, and then connected to the 12th pin of the analog switch U5. The 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
所述乘法器 U3的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U2的 第 8引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R8接运算放大器 U1的第 6引脚， 第 8引脚接 VCC; ,  The first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2. The second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
所述乘法器 U4的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U1的 第 7引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R9接运算放大器 U2的第 13引脚， 第 8引脚接 VCC;  The first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the seventh pin of the operational amplifier U1. The second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
所述模拟幵关 U5的第 1 引脚接 VCC，第 16引脚接地， 第 13、 14、 15 引脚悬空， 第 3 引脚接运算放大器 U1的第 8引脚， 第 6引脚接运算放大器 U1的第 7引脚， 第 11引脚接运 算放大器 U2的第 8引脚。  The first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are left floating, and the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected. The seventh pin of amplifier U1, the eleventh pin is connected to the eighth pin of operational amplifier U2.
本发明的有益效果是： 提出了一个新型的混沌系统的新型切换方法及电路， 这对增加 混沌系统切换的类型及这种混沌系统应用于工程实践提供了一种新思路。  The beneficial effects of the invention are as follows: A novel switching method and circuit for a novel chaotic system is proposed, which provides a new idea for increasing the type of chaotic system switching and the application of the chaotic system to engineering practice.
附图说明 DRAWINGS
图 1为本发明优选实施例的电路连接结构示意图。  FIG. 1 is a schematic diagram of a circuit connection structure according to a preferred embodiment of the present invention.
图 2和图 3为本发明的电路实际连接图。  2 and 3 are actual connection diagrams of the circuit of the present invention.
具体实施方式 detailed description
下面结合附图和优选实施例对本发明作更进一步的详细描述， 参见图 1-图 3。  The present invention will now be described in further detail with reference to the accompanying drawings and preferred embodiments, to FIGS.
1、 一种分数阶次不同的经典 Lii混沌切换系统方法， 其特征是在于， 包括以下步骤： A classical Lii chaotic switching system method with different fractional orders, characterized in that it comprises the following steps:
( 1 ) Lii混沌系统 i的方程为： dxl dt = a(y - x) (1) The equation of the Lii chaotic system i is: Dxl dt = a(y - x)
<dy I dt = cy-xz i a = 36, b = 3,c = 22 <dy I dt = cy-xz i a = 36, b = 3, c = 22
dz / dt = xy-bz  Dz / dt = xy-bz
(2) 0.9阶 Lii混沌系统 ii的方程为： (2) 0.9 order Lii chaotic system The equation of ii is:
d^x/dt09 =a(y-x) d^x/dt 09 = a(yx)
d09y/dt09 =cy-xz ii α = 36,b = 3,c = 22 d 09 y/dt 09 =cy-xz ii α = 36,b = 3,c = 22
cTz/dt。9 =xy-bz cT z /dt. 9 =xy-bz
(3) 0.1阶 Lii混沌系统 iii的方程为：
Figure imgf000006_0001
(3) The equation of the 0.1-order Lii chaotic system iii is:
Figure imgf000006_0001
(4)构造切换函数 g = f(x)，其中 /0)的表达式 iv为：  (4) Construct the switching function g = f(x), where the expression iv of /0) is:
ίθ.9 >0  Θθ.9 >0
¾ [0.1 x<0  3⁄4 [0.1 x<0
(5)由 ii、 iii和 iv构造一种分数阶次不同的 Lii混沌切换系统 v为： (5) Construct a Lii chaotic switching system with different fractional orders from ii, iii and iv v:
d'x/di" =a(y-x) f D'x/di" =a(yx) f
0.9 x>0  0.9 x>0
dqyld =cy-xz a = 36,b = 3,c = 22 , q = f(x) = v d q yld =cy-xz a = 36, b = 3,c = 22 , q = f(x) = v
0.1 JC < 0  0.1 JC < 0
dqzl dtq = xy-bz d q zl dt q = xy-bz
(6)根据分数阶次不同的 Lii混沌切换系统 v构造模拟电路系统， 利用运算放大器 Ul、 运算放 大器 U2及电阻和电容构成反相加法器和不同阶次的分数阶反相积分器， 利用乘法器 U3和乘 法器 U4实现乘法运算， 利用模拟开关 U5实现模拟信号的选择输出， 所述运算放大器 U1和 运算放大器 U2采用 LF347D, 所述乘法器 U3和乘法器 U4采用 AD633JN, 所述模拟开关 U5采 用 ADG888, 所述运算放大器 U1连接乘法器 U3、 乘法器 U4和模拟开关 U5， 所述运算放大器 U2连接乘法器 U3和模拟开关 U5， 所述乘法器 U3连接运算放大器 Ul， 所述乘法器 U4连接 运算放大器 U2， 所述模拟开关 U5连接运算放大器 U1和运算放大器 U2; (6) Constructing an analog circuit system based on the Lii chaotic switching system with different fractional orders, using the operational amplifier Ul, the operational amplifier U2, and the resistor and capacitor to form an inverting adder and a fractional-order inverting integrator of different orders, using multiplication The U3 and the multiplier U4 implement a multiplication operation, and the analog output of the analog signal is implemented by the analog switch U5. The operational amplifier U1 and the operational amplifier U2 are LF347D, and the multiplier U3 and the multiplier U4 are AD633JN, and the analog switch U5 is used. Using ADG888, the operational amplifier U1 is connected to a multiplier U3, a multiplier U4 and an analog switch U5, the operational amplifier U2 is connected to a multiplier U3 and an analog switch U5, and the multiplier U3 is connected to an operational amplifier U1, the multiplier U4 Connecting an operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
所述运算放大器 U1的第 1引脚通过电阻 R3与运算放大器 U1的第 2引脚相接， 通过电 阻 R7与运算放大器 U1的第 6引脚相接， 运算放大器 U1的第 3、 5、 10、 12引脚接地， 第 4 引脚接 VCC， 第 11引脚接 VEE， 运算放大器 U1 的第 6引脚通过电阻 Ryll与电容 Cyll的并 联， 接电阻 Ryl2与电容 Cyl2的并联， 再接电阻 Ryl3与电容 Cyl3的并联后， 再接模拟开关 U5的第 7引脚， 通过电阻 Ry21与电容 Cy21 的并联， 接电阻 Ry22与电容 Cy22的并联， 再 接电阻 Ry23与电容 Cy23的并联后， 再接模拟开关 U5的第 5引脚， 运算放大器 U1的第 7引 脚通过电阻 R2接运算放大器 U1的第 13引脚， 通过电阻 R4接运算放大器 U1的第 2引脚， 接乘法器 U4的第 3引脚， 运算放大器 U1的第 8引脚通过电阻 R5接运算放大器 U1的第 9引 脚， 接运算放大器 U2的第 2引脚， 接乘法器 U3的第 1引脚， 接乘法器 U4的第 1引脚， 运 算放大器 U1的第 9引脚通过电阻 Rxl l与电容 Cxl l的并联， 接电阻 Rxl2与电容 Cxl 2的并 联， 再接电阻 Rxl3与电容 Cxl3的并联后， 再接模拟开关 U5的第 2引脚， 通过电阻 Rx21与 电容 Cx21 的并联， 接电阻 Rx22与电容 Cx22 的并联， 再接电阻 Rx23 与电容 Cx23 的并联 后， 再接模拟开关 U5的第 4引脚， 运算放大器 ill 的第 14引脚通过电阻 R1接运算放大器 U1的第 13引脚， 通过电阻 R6接运算放大器 U1的第 9引脚； The first pin of the operational amplifier U1 is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1. 12-pin ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyll through the resistor Ryll, the parallel connection of the resistor Ryl2 and the capacitor Cyl2, and then the resistor Ryl3 In parallel with the capacitor Cyl3, connect the 7th pin of the analog switch U5, connect the resistor Ry21 and the capacitor Cy21 in parallel, connect the resistor Ry22 and the capacitor Cy22 in parallel, and then connect the resistor Ry23 and the capacitor Cy23 in parallel, then connect the analog Pin 5 of switch U5, 7th lead of operational amplifier U1 The pin is connected to the 13th pin of the operational amplifier U1 through the resistor R2, the second pin of the operational amplifier U1 through the resistor R4, the third pin of the multiplier U4, and the eighth pin of the operational amplifier U1 is connected via the resistor R5. The 9th pin of amplifier U1 is connected to the 2nd pin of the operational amplifier U2, the 1st pin of the multiplier U3 is connected, the 1st pin of the multiplier U4 is connected, and the 9th pin of the operational amplifier U1 passes the resistor Rxl l In parallel with the capacitor Cxl l, connect the resistor Rxl2 and the capacitor Cxl 2 in parallel, and then connect the resistor Rxl3 and the capacitor Cxl3 in parallel, then connect the second pin of the analog switch U5, connect the resistor Rx21 and the capacitor Cx21 in parallel, connect the resistor Parallel connection of Rx22 and capacitor Cx22, followed by parallel connection of resistor Rx23 and capacitor Cx23, and then connected to pin 4 of analog switch U5. Pin 14 of operational amplifier ill is connected to pin 13 of operational amplifier U1 through resistor R1. Connected to the ninth pin of the operational amplifier U1 through a resistor R6;
所述运算放大器 U2的第 6、 7引脚悬空， 所述运算放大器 U2的第 3、 5、 10、 12引脚 接地， 第 4引脚接 VCC, 第 11引脚接 VEE， 运算放大器 U2的第 1 引脚通过电阻 R13和 R14 的串联接地，通过 R13接模拟开关 U5的第 8、 9 引脚， 运算放大器 U2的第 8 引脚通过电阻 R11接运算放大器 U2的第 9引脚， 接乘法器 U3的第 3引脚， 运算放大器 U2的第 9引脚通 过电阻 Rzl l与电容 Czl l 的并联， 接电阻 Rzl2与电容 Czl 2的并联， 再接电阻 Rzl3与电容 Cz l3的并联后， 再接模拟开关 U5的第 10引脚， 通过电阻 Rz21与电容 Cz21 的并联， 接电 阻 Rz22与电容 Cz22的并联， 再接电阻 Rz23与电容 Cz23的并联后， 再接模拟开关 U5的第 12引脚， 运算放大器 U2的第 14引脚通过电阻 R10接运算放大器 U2的第 13引脚， 通过电 阻 R12接运算放大器 U2的第 9引脚；  The sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and twelve pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of resistors R13 and R14, connected to the 8th and 9th pins of analog switch U5 through R13, and the 8th pin of operational amplifier U2 is connected to the 9th pin of operational amplifier U2 through resistor R11. The third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czl l through the resistor Rzl l, and the parallel connection of the resistor Rzl2 and the capacitor Czl 2, and then connected in parallel with the resistor Rzl3 and the capacitor Cz l3, and then Connect the 10th pin of the analog switch U5, connect the resistor Rz21 and the capacitor Cz21 in parallel, connect the resistor Rz22 and the capacitor Cz22 in parallel, connect the resistor Rz23 and the capacitor Cz23 in parallel, and then connect the 12th pin of the analog switch U5. The 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
所述乘法器 U3的第 1 引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U2的 第 8引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R8接运算放大器 U1的第 6引脚， 第 8引脚接 VCC;  The first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2. The second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
所述乘法器 U4的第 1引脚接运算放大器 m的第 8引脚， 第 3引脚接运算放大器 U1的 第 7引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R9接运算放大器 U2的第 13引脚， 第 8引脚接 VCC;  The first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier m, the third pin is connected to the seventh pin of the operational amplifier U1, and the second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
所述模拟开关 U5的第 1 引脚接 VCC，第 16 引脚接地， 第 13、 14、 15引脚悬空， 第 3 引脚接运算放大器 U1的第 8引脚， 第 6引脚接运算放大器 U1的第 7引脚， 第 11引脚接运 算放大器 U2的第 8引脚。 .  The first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are floating, the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier. The 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2. .
2、 一种分数阶次不同的 Lii混沌切换系统电路， 其特征是在于， 利用运算放大器 Ul、 运算放大器 U2 及电阻和电容构成反相加法器和不同阶次的分数阶反相积分器， 利用乘法器 U3和乘法器 U4实现乘法运算， 利用模拟开关 U5实现模拟信号的选择输出， 所述运算放大 器 U1和运算放大器 U2采用 LF347D, 所述乘法器 U3和乘法器 U4采用 AD633JN, 所述模拟开 关 U5采用 ADG888 , 所述运算放大器 U1连接乘法器 U3、 乘法器 U4和模拟开关 U5， 所述运 算放大器 U2连接乘法器 U3和模拟开关 U5， 所述乘法器 U3连接运算放大器 U1， 所述乘法器 U4连接运算放大器 U2， 所述模拟开关 U5连接运算放大器 U1和运算放大器 U2; 2. A Lii chaotic switching system circuit with different fractional orders, characterized in that an operational amplifier U1, an operational amplifier U2, a resistor and a capacitor are used to form an inverting adder and a fractional-order inverse integrator of different orders is utilized. The multiplier U3 and the multiplier U4 implement a multiplication operation, and the analog switch U5 is used to realize the selective output of the analog signal. The operational amplifier U1 and the operational amplifier U2 adopt LF347D, and the multiplier U3 and the multiplier U4 adopt AD633JN, and the analog is turned on. The U5 is connected to the U5, the operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analog switch U5, the operational amplifier U2 is connected to the multiplier U3 and the analog switch U5, and the multiplier U3 is connected to the operational amplifier U1, the multiplication The U4 is connected to the operational amplifier U2, the analog switch U5 is connected to the operational amplifier U1 and the operational amplifier U2;
所述运算放大器 m的第 1引脚通过电阻 R3与运算放大器 U1的第 2引脚相接， 通过电 阻 R7与运算放大器 U1的第 6引脚相接， 运算放大器 U1的第 3、 5、 10、 12引脚接地， 第 4 引脚接 VCC， 第 11引脚接 VEE， 运算放大器 U1的第 6引脚通过电阻 Ryl l与电容 Cyl l的并 联， 接电阻 Ryl2与电容 Cyl2的并联， 再接电阻 Ryl3与电容 Cyl3的并联后， 再接模拟开关 U5的第 7引脚， 通过电阻 Ry21与电容 Cy21 的并联， 接电阻 Ry22与电容 Cy22的并联， 再 接电阻 Ry23与电容 Cy23的并联后， 再接模拟开关 U5的第 5引脚， 运算放大器 U1的第 7引 脚通过电阻 R2接运算放大器 U1的第 13引脚， 通过电阻 R4接运算放大器 U1的第 2引脚， 接乘法器 U4的第 3引脚， 运算放大器 U1的第 8引脚通过电阻 R5接运算放大器 U1的第 9引 脚， 接运算放大器 U2的第 2引脚， 接乘法器 U3的第 1引脚， 接乘法器 U4的第 1引脚， 运 算放大器 U1的第 9引脚通过电阻 Rxl l与电容 Cxl l的并联， 接电阻 Rxl2与电容 Cxl2的并 联， 再接电阻 Rxl3与电容 Cxl3的并联后， 再接模拟开关 U5的第 2引脚， 通过电阻 Rx21与 电容 Cx21 的并联， 接电阻 Rx22与电容 Cx22 的并联， 再接电阻 Rx23与电容 Cx23 的并联 后， 再接模拟开关 U5的第 4引脚， 运算放大器 U1 的第 14引脚通过电阻 R1接运算放大器 U1的第 13引脚， 通过电阻 R6接运算放大器 U1的第 9引脚；  The first pin of the operational amplifier m is connected to the second pin of the operational amplifier U1 via the resistor R3, and is connected to the sixth pin of the operational amplifier U1 via the resistor R7, and the third, fifth, and tenth of the operational amplifier U1. 12-pin ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel with the capacitor Cyl l through the resistor Ryl l, and the parallel connection of the resistor Ryl2 and the capacitor Cyl2 is connected. After the resistor Ryl3 is connected in parallel with the capacitor Cyl3, it is connected to the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, and connected in parallel with the resistor Ry22 and the capacitor Cy22, and then connected in parallel with the resistor Ry23 and the capacitor Cy23, and then Connect the fifth pin of analog switch U5, the seventh pin of operational amplifier U1 is connected to the 13th pin of operational amplifier U1 through resistor R2, the second pin of operational amplifier U1 through resistor R4, and the second pin of multiplier U4 The 3 pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier U1 through the resistor R5, the second pin of the operational amplifier U2, the first pin of the multiplier U3, and the multiplier U4. 1st The 9th pin of the operational amplifier U1 is connected in parallel with the capacitor Cxl l through the resistor Rxl l, and the parallel connection of the resistor Rxl2 and the capacitor Cxl2, and then connected in parallel with the resistor Rxl3 and the capacitor Cxl3, and then connected to the second lead of the analog switch U5. The pin is connected in parallel with the capacitor Cx21 through the resistor Rx21, and the parallel connection between the resistor Rx22 and the capacitor Cx22, and then connected in parallel with the resistor Rx23 and the capacitor Cx23, and then connected to the fourth pin of the analog switch U5, the 14th pin of the operational amplifier U1. Connected to the 13th pin of the operational amplifier U1 through the resistor R1, and connected to the 9th pin of the operational amplifier U1 through the resistor R6;
所述运算放大器 U2的第 6、 7引脚悬空， 所述运算放大器 U2的第 3、 5、 10、 12引脚 接地， 第 4引脚接 VCC， 第 11 引脚接 VEE， 运算放大器 U2的第 1 引脚通过电阻 R13和 R14 的串联接地，通过 R13接模拟开关 U5的第 8、 9 引脚， 运算放大器 U2的第 8 引脚通过电阻 R11接运算放大器 U2的第 9引脚， 接乘法器 U3的第 3引脚， 运算放大器 U2的第 9引脚通 过电阻 Rzl l与电容 Czl l的并联， 接电阻 Rzl2与电容 Czl2的并联， 再接电阻 Rzl3与电容 Czl3的并联后， 再接模拟开关 U5的第 10引脚， 通过电阻 Rz21与电容 Cz21 的并联， 接电 阻 Rz22与电容 Cz22的并联， 再接电阻 Rz23与电容 Cz23的并联后， 再接模拟开关 U5的第 12引脚， 运算放大器 U2的第 14引脚通过电阻 R10接运算放大器 U2的第 13引脚， 通过电 阻 R12接运算放大器 U2的第 9引脚；  The sixth and seventh pins of the operational amplifier U2 are left floating, the third, fifth, ten, and 12 pins of the operational amplifier U2 are grounded, the fourth pin is connected to VCC, the eleventh pin is connected to VEE, and the operational amplifier U2 is The first pin is connected to the series ground of resistors R13 and R14, connected to the 8th and 9th pins of analog switch U5 through R13, and the 8th pin of operational amplifier U2 is connected to the 9th pin of operational amplifier U2 through resistor R11. The third pin of U3, the ninth pin of the operational amplifier U2 is connected in parallel with the capacitor Czl1 through the resistor Rzl l, and the parallel connection of the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the resistor Rzl3 and the capacitor Czl3, and then connected to the analog The 10th pin of the switch U5 is connected in parallel with the capacitor Cz21 through the resistor Rz21 and the capacitor Cz21. Then, the parallel connection between the resistor Rz23 and the capacitor Cz23 is connected, and then the 12th pin of the analog switch U5 is connected, and the operational amplifier is connected. The 14th pin of U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and is connected to the 9th pin of the operational amplifier U2 through the resistor R12;
所述乘法器 U3的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U2的 第 8引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R8接运算放大器 U1的第 6引脚， 第 8引脚接 VCC;  The first pin of the multiplier U3 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the eighth pin of the operational amplifier U2. The second, fourth, and sixth pins are grounded, and the fifth pin is connected. VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
所述乘法器 U4的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U1的 第 7引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R9接运算放大器 U2的第 13引脚， 第 8引脚接 VCC; The first pin of the multiplier U4 is connected to the eighth pin of the operational amplifier U1, and the third pin is connected to the operational amplifier U1. The 7th pin, the 2nd, 4th, and 6th pins are all grounded, the 5th pin is connected to VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
所述模拟开关 U5的第 1 引脚接 VCC，第 16引脚接地， 第 13、 14、 15引脚悬空， 第 3 引脚接运算放大器 U1的第 8引脚， 第 6引脚接运算放大器 U1的第 7引脚， 第 11引脚接运 算放大器 U2的第 8引脚。  The first pin of the analog switch U5 is connected to VCC, the 16th pin is grounded, the 13th, 14th, and 15th pins are floating, the third pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier. The 7th pin of U1 and the 11th pin are connected to the 8th pin of the operational amplifier U2.
¾ ¾ Φ ¾ ¾ Rl = R3 = R6 = RT = Rl0 = RU = \0kn , R8 = R9 = lkQ, , R4 = 4.5kQ , R2 = R5^2 kQ ， Rll = 333kQ ， 7?13 = 100 :Ω ， R\4 = S0kQ ， Rx\l = Ry\\ = Rz\\ = 62.84 Ω , Rx\2 = Ry\2 = Rz\2 = 250kQ , 7^13 = ifyl3 = J?zl3 = 2.5人 Ω， Rx2\ = Ry2\ = Rz2\ = 0.636 Ω ， Rx22 = Ryll = Rz22 = 0.3815ΜΩ ， 3⁄4 3⁄4 Φ 3⁄4 3⁄4 Rl = R3 = R6 = RT = Rl0 = RU = \0kn , R8 = R9 = lkQ, , R4 = 4.5kQ , R2 = R5^2 kQ , Rll = 333kQ , 7?13 = 100 : Ω , R\4 = S0kQ , Rx\l = Ry\\ = Rz\\ = 62.84 Ω , Rx\2 = Ry\2 = Rz\2 = 250kQ , 7^13 = ifyl3 = J?zl3 = 2.5 Ω, Rx2\ = Ry2\ = Rz2\ = 0.636 Ω , Rx22 = Ryll = Rz22 = 0.3815ΜΩ ,
RxTi = Ry23 = Rz2 = 0.5672 Ω ， Cxi 1 = yl 1 = Czl 1 = 1.2 ，
Figure imgf000009_0001
Cz2\ = 5.75juF， Cx22 = Cy22 = Cz22 = 0.1575^/ ， Cx23 = Cy23 = Cz23 = 633.5n 。 RxTi = Ry23 = Rz2 = 0.5672 Ω , Cxi 1 = yl 1 = Czl 1 = 1.2
Figure imgf000009_0001
Cz2\ = 5.75juF, Cx22 = Cy22 = Cz22 = 0.1575^/ , Cx23 = Cy23 = Cz23 = 633.5n .
当然， 上述说明并非对本发明的限制， 本发明也不仅限于上述举例， 本技术领域的普 通技术人员在本发明的实质范围内所做出的变化、 改型、 添加或替换， 也属于本发明的保护 范围。  The above description is not intended to limit the invention, and the invention is not limited to the above examples, and variations, modifications, additions or substitutions made by those skilled in the art within the scope of the invention also belong to the invention. protected range.

Claims

权 利 要 求 书 claims
1、 一种分数阶次不同的经典 Lii混沌切换系统方法， 其特征是在于， 包括以下步骤： 1. A classical Lii chaotic switching system method with different fractional orders, which is characterized by including the following steps:
(1) Lii混沌系统 i的方程为： (1) The equation of Lii chaotic system i is:
dxl dt = a(y - x) dxl dt = a(y - x)
dy I dt = cy- xz i a = 36,b = 3,c = 22 dy I dt = cy- xz i a = 36, b = 3, c = 22
dz / dt = xy-bz dz/dt = xy-bz
(2) 0.9阶 Lii混沌系统 i i的方程为： (2) The equation of the 0.9th order Lii chaotic system i i is:
d°'9x I dt0'9 = a(y - x) d°' 9 x I dt 0 ' 9 = a(y - x)
d^y/dt09 =cy-xz ii Ω = 36,b = 3,c = 22 d^y/dt 09 =cy-xz ii Ω = 36,b = 3,c = 22
d09z/dt09 =xy-bz d 09 z/dt 09 =xy-bz
(3) 0.1阶 Lii混沌系统 i i i的方程为： (3) The equation of the 0.1-order Lii chaotic system i i is:
d0 lx I clt0A = a(y一 x) d 0 l x I clt 0A = a(y-x)
d0Ay/dt0A =cy-xz iii a = 36,b = 3,c = 22 d 0A y/dt 0A =cy-xz iii a = 36,b = 3,c = 22
d0Az I dt01 = xy-bz d 0A z I dt 01 = xy-bz
(4)构造切换函数 g = f(x) '其中 /(x)的表达式 iv为： (4) Construct the switching function g = f(x) 'where the expression iv of /(x) is:
ίθ.9 χ>0 ίθ.9 χ>0
[θ.Ι <0 [θ.Ι <0
(5)由 ϋ、 iii和 iv构造一种分数阶次不同的 Lii混沌切换系统 V为： (5) A Lii chaotic switching system V with different fractional orders is constructed from ϋ, iii and iv:
dqxl dtq =a(y~x) r d q xl dt q =a(y~x) r
γ ' ίθ.9 χ>0 γ 'ίθ.9 χ>0
dqyl df =cy-xz Ω = 36,b = 3, c = 22 , q = f{x) = \ v d q yl df =cy-xz Ω = 36,b = 3, c = 22, q = f{x) = \ v
y γ 0.1 x<0 y γ 0.1 x<0
dqzld = xy-bz 1 d q zld = xy-bz 1
(6)根据分数阶次不同的 Lii混沌切换系统 v构造模拟电路系统， 利用运算放大器 Ul、 运算放 大器 U2及电阻和电容构成反相加法器和不同阶次的分数阶反相积分器， 利用乘法器 U3和乘 法器 U4实现乘法运算， 利用模拟开关 U5实现模拟信号的选择输出， 所述运算放大器 U1和 运算放大器 U2采用 LF347D, 所述乘法器 U3和乘法器 U4采用 AD633JN, 所述模拟开关 U5采 用 ADG888, 所述运算放大器 U1连接乘法器 U3、 乘法器 U4和模拟开关 U5， 所述运算放大器 U2连接乘法器 U3和模拟开关 U5， 所述乘法器 U3连接运算放大器 Ul， 所述乘法器 U4连接 运算放大器 U2, 所述模拟开关 U5连接运算放大器 U1和运算放大器 U2; (6) Construct an analog circuit system based on the Lii chaotic switching system v with different fractional orders, use operational amplifiers Ul, operational amplifier U2, resistors and capacitors to form an inverting adder and fractional-order inverting integrators of different orders, using multiplication The multiplier U3 and the multiplier U4 realize the multiplication operation, and the analog switch U5 is used to realize the selective output of the analog signal. The operational amplifier U1 and the operational amplifier U2 adopt LF347D, the multiplier U3 and the multiplier U4 adopt AD633JN, and the analog switch U5 Using ADG888, the operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analog switch U5, the operational amplifier U2 is connected to the multiplier U3 and the analog switch U5, the multiplier U3 is connected to the operational amplifier U1, and the multiplier U4 Connect the operational amplifier U2, and the analog switch U5 connects the operational amplifier U1 and the operational amplifier U2;
所述运算放大器 U1的第 1引脚通过电阻 R3与运算放大器 U1的第 2引脚相接， 通过电 阻 R7与运算放大器 U1的第 6引脚相接， 运算放大器 U1的第 3、 5、 10、 12引脚接地， 第 4 引脚接 VCC， 第 11引脚接 VEE， 运算放大器 U1的第 6引脚通过电阻 Ryll与电容 Cyll的并 联， 接电阻 Ryl2与电容 Cyl2的并联， 再接电阻 Ryl3与电容 Cyl3的并联后， 再接模拟开关 U5的第 7引脚， 通过电阻 Ry21与电容 Cy21的并联， 接电阻 Ry22与电容 Cy22的并联， 再 接电阻 Ry23与电容 Cy23的并联后， 再接模拟开关 U5的第 5引脚， 运算放大器 U1的第 7引 脚通过电阻 R2接运算放大器 U1的第 13引脚， 通过电阻 R4接运算放大器 U1的第 2引脚， 接乘法器 M的第 3引脚， 运算放大器 U1的第 8引脚通过电阻 R5接运算放大器 L11的第 9引 脚， 接运算放大器 U2的第 2引脚， 接乘法器 U3的第 1引脚， 接乘法器 IM的第 1 引脚， 运 算放大器 U1的第 9引脚通过电阻 Rxll与电容 Cxll的并联， 接电阻 Rxl2与电容 Cxl2的并 联， 再接电阻 Rxl3与电容 Cxl3的并联后， 再接模拟开关 U5的第 2引脚， 通过电阻 Rx21与 电容 Cx21 的并联， 接电阻 Rx22与电容 Cx22 的并联， 再接电阻 Rx23 与电容 Cx23 的并联 后， 再接模拟开关 U5的第 4引脚， 运算放大器 U1 的第 14引脚通过电阻 R1接运算放大器 U1的第 13引脚， 通过电阻 R6接运算放大器 U1的第 9引脚； The 1st pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor R3, the 6th pin of the operational amplifier U1 is connected to the resistor R7, and the 3rd, 5th, and 10th pins of the operational amplifier U1 , 12 pins are connected to ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel through the resistor Ryll and the capacitor Cyll, connected in parallel with the resistor Ryl2 and the capacitor Cyl2, and then connected to the resistor Ryl3 After connecting in parallel with the capacitor Cyl3, then connect the analog switch The 7th pin of U5 is connected through the parallel connection of the resistor Ry21 and the capacitor Cy21, to the parallel connection of the resistor Ry22 and the capacitor Cy22, and then to the parallel connection of the resistor Ry23 and the capacitor Cy23, and then to the 5th pin of the analog switch U5, and the operational amplifier U1 The 7th pin of the Resistor R5 is connected to the 9th pin of the operational amplifier L11, to the 2nd pin of the operational amplifier U2, to the 1st pin of the multiplier U3, to the 1st pin of the multiplier IM, to the 9th pin of the operational amplifier U1 Through the parallel connection of resistor Rxll and capacitor Cxll, connect the parallel connection of resistor Rxl2 and capacitor Cxl2, then connect the parallel connection of resistor Rxl3 and capacitor Cxl3, and then connect the second pin of analog switch U5, through the parallel connection of resistor Rx21 and capacitor Cx21, connect The resistor Rx22 and the capacitor Cx22 are connected in parallel, and then the resistor Rx23 and the capacitor Cx23 are connected in parallel, and then the 4th pin of the analog switch U5 is connected. The 14th pin of the operational amplifier U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R1. , connected to the 9th pin of the operational amplifier U1 through the resistor R6;
所述运算放大器 U2的第 6、 7引脚悬空， 所述运算放大器 U2的第 3、 5、 10、 12引脚 接地， 第 4引脚接 VCC， 第 11引脚接 VEE， 运算放大器 U2的第 1 引脚通过电阻 R13和 R14 的串联接地，通过 R13接模拟开关 U5的第 8、 9 引脚， 运算放大器 U2的第 8 引脚通过电阻 R11接运算放大器 U2的第 9引脚， 接乘法器 U3的第 3引脚， 运算放大器 U2的第 9引脚通 过电阻 Rzll与电容 Czll 的并联， 接电阻 Rzl2与电容 Czl2的并联， 再接电阻 Rzl3与电容 Czl3的并联后， 再接模拟开关 U5的第 10引脚， 通过电阻 Rz21与电容 Cz21 的并联， 接电 阻 Rz22与电容 Cz22的并联， 再接电阻 Rz23与电容 Cz23的并联后， 再接模拟开关 U5的第 12引脚， 运算放大器 U2的第 14引脚通过电阻 R10接运算放大器 U2的第 13引脚， 通过电 阻 R12接运算放大器 U2的第 9引脚； The 6th and 7th pins of the operational amplifier U2 are floating, the 3rd, 5th, 10th and 12th pins of the operational amplifier U2 are connected to ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, and the 11th pin of the operational amplifier U2 is connected to the ground. The first pin is connected to the ground through the series connection of resistors R13 and R14, and is connected to the 8th and 9th pins of the analog switch U5 through R13. The 8th pin of the operational amplifier U2 is connected to the 9th pin of the operational amplifier U2 through the resistor R11, and is connected to the multiplication The 3rd pin of the amplifier U3, the 9th pin of the operational amplifier U2 are connected in parallel through the resistor Rzll and the capacitor Czll, then connected in parallel with the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the resistor Rzl3 and the capacitor Czl3, and then connected to the analog switch U5 The 10th pin is connected through the parallel connection of resistor Rz21 and capacitor Cz21, to the parallel connection of resistor Rz22 and capacitor Cz22, and then to the parallel connection of resistor Rz23 and capacitor Cz23, and then to the 12th pin of analog switch U5, and the parallel connection of operational amplifier U2. The 14th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and the 9th pin of the operational amplifier U2 is connected through the resistor R12;
所述乘法器 U3的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U2的 第 8引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R8接运算放大器 U1的第 6引脚， 第 8引脚接 VCC; The first pin of the multiplier U3 is connected to the 8th pin of the operational amplifier U1, the 3rd pin is connected to the 8th pin of the operational amplifier U2, the 2nd, 4th, and 6th pins are all connected to ground, and the 5th pin is connected to VEE, the 7th pin is connected to the 6th pin of the operational amplifier U1 through the resistor R8, and the 8th pin is connected to VCC;
所述乘法器 U4的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U1的 第 7引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R9接运算放大器 U2的第 13引脚， 第 8引脚接 VCC; The first pin of the multiplier U4 is connected to the 8th pin of the operational amplifier U1, the 3rd pin is connected to the 7th pin of the operational amplifier U1, the 2nd, 4th and 6th pins are all connected to ground, and the 5th pin is connected to VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
所述模拟开关 U5的第 1 引脚接 VCC,第 16引脚接地， 第 13、 14、 15引脚悬空， 第 3 引脚接运算放大器 U1的第 8引脚， 第 6引脚接运算放大器 U1的第 7引脚， 第 11引脚接运 算放大器 U2的第 8引脚。 The 1st pin of the analog switch U5 is connected to VCC, the 16th pin is connected to ground, the 13th, 14th and 15th pins are floating, the 3rd pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier The 7th pin and 11th pin of U1 are connected to the 8th pin of the operational amplifier U2.
2、 一种分数阶次不同的 Li混沌切换系统电路， 其特征是在于， 利用运算放大器 Ul、 运算放大器 U2 及电阻和电容构成反相加法器和不同阶次的分数阶反相积分器， 利用乘法器 U3和乘法器 U4实现乘法运算， 利用模拟开关 U5 实现模拟信号的选择输出， 所述运算放大 器 U1和运算放大器 U2采用 LF347D, 所述乘法器 U3和乘法器 U4采用 AD633JN, 所述模拟开 关 U5采用 ADG888, 所述运算放大器 U1连接乘法器 U3、 乘法器 U4和模拟开关 U5， 所述运 算放大器 U2连接乘法器 U3和模拟开关 U5, 所述乘法器 U3连接运算放大器 U1 , 所述乘法器 U4连接运算放大器 U2, 所述模拟开关 U5连接运算放大器 U1和运算放大器 U2; 2. A Li chaotic switching system circuit with different fractional orders, characterized by using operational amplifiers Ul, operational amplifier U2, resistors and capacitors to form an inverting adder and fractional-order inverting integrators of different orders, using Multiplier U3 and multiplier U4 realize multiplication operation, and use analog switch U5 to realize the selective output of analog signals. The operational amplifier U1 and operational amplifier U2 adopt LF347D, the multiplier U3 and multiplier U4 adopt AD633JN, and the analog switch U5 adopts ADG888, the operational amplifier U1 is connected to the multiplier U3, the multiplier U4 and the analog switch U5, the operational amplifier U2 is connected to the multiplier U3 and the analog switch U5, the multiplier U3 is connected to the operational amplifier U1, and the multiplier U4 is connected to Operational amplifier U2, the analog switch U5 connects the operational amplifier U1 and the operational amplifier U2;
所述运算放大器 U1的第 1引脚通过电阻 R3与运算放大器 U1的第 2引脚相接， 通过电 阻 R7与运算放大器 U1的第 6引脚相接， 运算放大器 U1的第 3、 5、 10、 12引脚接地， 第 4 引脚接 VCC， 第 11引脚接 VEE, 运算放大器 U1的第 6引脚通过电阻 Ryl l与电容 Cyl l的并 联， 接电阻 Ryl2与电容 Cyl2的并联， 再接电阻 Ryl3与电容 Cyl3的并联后， 再接模拟开关 U5的第 7引脚， 通过电阻 Ry21与电容 Cy21 的并联， 接电阻 Ry22与电容 Cy22的并联， 再 接电阻 Ry23与电容 Cy23的并联后， 再接模拟开关 U5的第 5引脚， 运算放大器 U1的第 7引 脚通过电阻 R2接运算放大器 U1的第 13引脚， 通过电阻 R4接运算放大器 U1的第 2引脚，， 接乘法器 U4的第 3引脚， 运算放大器 U1的第 8引脚通过电阻 R5接运算放大器 L'l的第 9引 脚， 接运算放大器 U2的第 2引脚， 接乘法器 U3的第 1引脚， 接乘法器 U4的第 1 引脚， 运 算放大器 U1的第 9引脚通过电阻 Rxl l与电容 Cxl l的并联， 接电阻 Rxl2与电容 Cxl2的并 联， 再接电阻 Rxl3与电容 Cxl3的并联后， 再接模拟开关 U5的第 2引脚， 通过电阻 Rx21与 电容 Cx21 的并联， 接电阻 Rx22与电容 Cx22 的并联， 再接电阻 Rx23与电容 Cx23 的并联 后， 再接模拟开关 U5的第 4引脚， 运算放大器 U1 的第 14引脚通过电阻 R1接运算放大器 U1的第 13引脚， 通过电阻 R6接运算放大器 U1的第 9引脚； The 1st pin of the operational amplifier U1 is connected to the 2nd pin of the operational amplifier U1 through the resistor R3, the 6th pin of the operational amplifier U1 is connected to the resistor R7, and the 3rd, 5th, and 10th pins of the operational amplifier U1 , 12 pins are connected to ground, the 4th pin is connected to VCC, the 11th pin is connected to VEE, the 6th pin of the operational amplifier U1 is connected in parallel through the resistor Ryl l and the capacitor Cyl l, and then connected in parallel with the resistor Ryl2 and the capacitor Cyl2, and then connected After the resistor Ryl3 and the capacitor Cyl3 are connected in parallel, then connect the 7th pin of the analog switch U5, through the parallel connection of the resistor Ry21 and the capacitor Cy21, then connect the parallel connection of the resistor Ry22 and the capacitor Cy22, then connect the parallel connection of the resistor Ry23 and the capacitor Cy23, and then Connect to the 5th pin of the analog switch U5, connect the 7th pin of the operational amplifier U1 to the 13th pin of the operational amplifier U1 through the resistor R2, connect to the 2nd pin of the operational amplifier U1 through the resistor R4, and connect to the multiplier U4 The 3rd pin, the 8th pin of the operational amplifier U1 is connected to the 9th pin of the operational amplifier L'l through the resistor R5, connected to the 2nd pin of the operational amplifier U2, connected to the 1st pin of the multiplier U3, connected to the multiplication The 1st pin of the device U4, the 9th pin of the operational amplifier U1 are connected in parallel through the resistor Rxl l and the capacitor Cxl l, then connected in parallel with the resistor Rxl2 and the capacitor Cxl2, and then connected in parallel with the resistor Rxl3 and the capacitor Cxl3, and then connected in parallel with the analog The 2nd pin of the switch U5 is connected in parallel with the resistor Rx21 and the capacitor Cx21, then connected in parallel with the resistor Rx22 and the capacitor Cx22, and then connected in parallel with the resistor Rx23 and the capacitor Cx23, and then connected with the 4th pin of the analog switch U5, operational amplifier The 14th pin of U1 is connected to the 13th pin of the operational amplifier U1 through the resistor R1, and the 9th pin of the operational amplifier U1 is connected through the resistor R6;
所述运算放大器 U2的第 6、 7引脚悬空， 所述运算放大器 U2的第 3、 5、 10、 12引脚 接地， 第 4引脚接 VCC' 第 11 引脚接 VEE， 运算放大器 L'2的第 1 引脚通过电阻 R13和 R14 的串联接地,通过 R13接模拟开关 U5的第 8、 9 引脚， 运算放大器 L'2的第 8引脚通过电阻 R11接运算放大器 U2的第 9引脚， 接乘法器 U3的第 3引脚， 运算放大器 U2的第 9引脚通 过电阻 Rzl l与电容 Czl l的并联， 接电阻 Rzl2与电容 Czl2的并联， 再接电阻 Rzl3与电容 Czl3的并联后， 再接模拟开关 U5的第 10引脚， 通过电阻 Rz21与电容 Cz21 的并联， 接电 阻 Rz22与电容 Cz22的并联， 再接电阻 Rz23与电容 Cz23的并联后， 再接模拟开关 U5的第 12引脚， 运算放大器 U2的第 14引脚通过电阻 R10接运算放大器 U2的第 13引脚， 通过电 阻 R12接运算放大器 U2的第 9引脚； The 6th and 7th pins of the operational amplifier U2 are floating, the 3rd, 5th, 10th and 12th pins of the operational amplifier U2 are connected to ground, the 4th pin is connected to VCC', the 11th pin is connected to VEE, and the operational amplifier L' The first pin of 2 is connected to the ground through the series connection of resistors R13 and R14, and is connected to the 8th and 9th pins of the analog switch U5 through R13. The 8th pin of the operational amplifier L'2 is connected to the 9th pin of the operational amplifier U2 through the resistor R11. pin, connected to the 3rd pin of the multiplier U3, the 9th pin of the operational amplifier U2 is connected in parallel through the resistor Rzl l and the capacitor Czl l, connected in parallel with the resistor Rzl2 and the capacitor Czl2, and then connected in parallel with the resistor Rzl3 and the capacitor Czl3 , then connect the 10th pin of the analog switch U5, through the parallel connection of the resistor Rz21 and the capacitor Cz21, then connect the parallel connection of the resistor Rz22 and the capacitor Cz22, then connect the parallel connection of the resistor Rz23 and the capacitor Cz23, and then connect the 12th pin of the analog switch U5 pin, the 14th pin of the operational amplifier U2 is connected to the 13th pin of the operational amplifier U2 through the resistor R10, and the 9th pin of the operational amplifier U2 is connected through the resistor R12;
所述乘法器 U3的第 1引脚接运算放大器 ΙΠ的第 8引脚， 第 3引脚接运算放大器 U2的 第 8引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R8接运算放大器 Ul的第 6引脚， 第 8引脚接 VCC; The first pin of the multiplier U3 is connected to the 8th pin of the operational amplifier U2, the 3rd pin is connected to the 8th pin of the operational amplifier U2, the 2nd, 4th, and 6th pins are all connected to ground, and the 5th pin is connected to VEE, pin 7 is connected to the operational amplifier through resistor R8 The 6th pin of Ul and the 8th pin are connected to VCC;
所述乘法器 U4的第 1引脚接运算放大器 U1的第 8引脚， 第 3引脚接运算放大器 U1的 第 Ί引脚， 第 2、 4、 6引脚均接地， 第 5引脚接 VEE， 第 7引脚通过电阻 R9接运算放大器 U2的第 13引脚， 第 8引脚接 VCC; The first pin of the multiplier U4 is connected to the 8th pin of the operational amplifier U1, the 3rd pin is connected to the Ίth pin of the operational amplifier U1, the 2nd, 4th, and 6th pins are all connected to ground, and the 5th pin is connected to VEE, the 7th pin is connected to the 13th pin of the operational amplifier U2 through the resistor R9, and the 8th pin is connected to VCC;
所述模拟开关 U5的第 1 引脚接 VCC，第 16引脚接地， 第 13、 14、 15 引脚悬空， 第 3 引脚接运算放大器 U1的第 8引脚， 第 6引脚接运算放大器 U1的第 7引脚， 第】1 引脚接运 算放大器 U2的第 8引脚。 The 1st pin of the analog switch U5 is connected to VCC, the 16th pin is connected to ground, the 13th, 14th, and 15th pins are floating, the 3rd pin is connected to the 8th pin of the operational amplifier U1, and the 6th pin is connected to the operational amplifier The 7th pin and 1st pin of U1 are connected to the 8th pin of the operational amplifier U2.
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