CN103997400A - Method and circuit for different-fractional-order y<2>-containing Liu chaotic switching system - Google Patents

Abstract

The invention provides a method and a circuit for a different-fractional-order y<2>-containing Liu chaotic switching system. An operational amplifier U1, an operational amplifier U2, resistors and capacitors are utilized for forming reverse phase adders and fractional order reverse phase integrators with different orders; a multiplier U3 and a multiplier U4 are utilized for realizing multiplication operation; an analog switch U5 is used for realizing the selective output of analog signals; the operational amplifier U1 and the operational amplifier U2 adopt LF347D; the multiplier U3 and the multiplier U4 adopt AD633JN; the analog switch U5 adoptes ADG888; the operational amplifier U1 is connected with the multiplier U3, the multiplier U4 and the analog switch U5; the operational amplifier U2 is connected with the multiplier U3 and the analog switch U5; the multiplier U3 is connected with the operational amplifier U1; the multiplier U4 is connected with the operational amplifier U2; and the analog switch U5 is connected with the operational amplifier U1 and the operational amplifier U2. The invention provides the novel switching method and the novel circuit for the novel chaotic system, and a new thought is provided for increasing the chaotic system switching types and the application of the chaotic system to engineering practice.

Description

What a kind of fractional-order was different contains y 2liu chaos switched system method and circuit

Technical field

The present invention relates to a chaos system and circuit and realize, what particularly a kind of fractional-order was different contains y ²liu chaos switched system method and circuit.

Background technology

At present, the method of the switching chaos system that oneself has and main circuit to comprise different linear terms in chaos system or nonlinear terms between switching, and fractional order form based on these 2 kinds of switch modes, changing method and circuit about the chaotic systems with fractional order of different orders are not also suggested, the present invention proposes a kind of fractional-order different containing y ²liu chaos switched system method and circuit, the present invention proposes New-type switching method and the circuit of a novel chaos system, this is applied to engineering practice to the type that increases chaos system and switch and this chaos system a kind of new approaches is provided.

Summary of the invention

The technical problem to be solved in the present invention be to provide a kind of fractional-order different containing y ²liu chaos switched system method and circuit, the present invention adopts following technological means to realize goal of the invention:

What 1, a kind of fractional-order was different contains y ²liu chaos switched system method, it is characterized in that being, comprise the following steps:

(1) containing y ²the equation of Liu chaos system i be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{cxz}\\ \mathrm{dz}/\mathrm{dt}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---i,a=10,b=40,c=10,d=2.5,h=4$

(2) 0.9 rank are containing y ²the equation of Liu chaos system ii be:

$\left\{\begin{array}{c}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=a(y-x)\\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{bx}-\mathrm{cxz}\\ d^{0.9}z/{\mathrm{dt}}^{0.9}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---\mathrm{ii},a=10,b=40,c=10,d=2.5,h=4$

(3) 0.1 rank are containing y ²the equation of Liu chaos system iii be:

$\left\{\begin{array}{c}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=a(y-x)\\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{bx}-\mathrm{cxz}\\ d^{0.1}z/{\mathrm{dt}}^{0.1}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---\mathrm{ii},a=10,b=40,c=10,d=2.5,h=4$

(4) structure switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.---\mathrm{iv}$

(5) by ii, iii and iv construct a kind of fractional-order different containing y ²liu chaos switched system v be:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}-\mathrm{cxz}\\ d^{q}z/{\mathrm{dt}}^q={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.,a=10,b=40,c=10,d=2.5,h=4,q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.,v$

(6) according to fractional-order different containing y ²liu chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R 4, connect the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,

The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

What 2, a kind of fractional-order was different contains y ²liu chaos switched system circuit, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R 4, connect the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,

The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

The invention has the beneficial effects as follows: proposed New-type switching method and the circuit of a novel chaos system, the type that this switches increase chaos system and this chaos system are applied to engineering practice provides a kind of new approaches.

Brief description of the drawings

Fig. 1 is the circuit connection structure schematic diagram of the preferred embodiment of the present invention.

Fig. 2 and Fig. 3 are the actual connection layout of circuit of the present invention.

Embodiment

Below in conjunction with accompanying drawing and preferred embodiment, the present invention is further described in detail, referring to Fig. 1-Fig. 3.

What 1, a kind of fractional-order was different contains y ²liu chaos switched system method, it is characterized in that being, comprise the following steps:

(1) containing y ²the equation of Liu chaos system i be:

$\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{cxz}\\ \mathrm{dz}/\mathrm{dt}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---i,a=10,b=40,c=10,d=2.5,h=4$

(2) 0.9 rank are containing y ²the equation of Liu chaos system ii be:

$\left\{\begin{array}{c}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=a(y-x)\\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{bx}-\mathrm{cxz}\\ d^{0.9}z/{\mathrm{dt}}^{0.9}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---\mathrm{ii},a=10,b=40,c=10,d=2.5,h=4$

(3) 0.1 rank are containing y ²the equation of Liu chaos system iii be:

$\left\{\begin{array}{c}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=a(y-x)\\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{bx}-\mathrm{cxz}\\ d^{0.1}z/{\mathrm{dt}}^{0.1}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---\mathrm{ii},a=10,b=40,c=10,d=2.5,h=4$

(4) structure switching function q=f (x), wherein the expression formula iv of f (x) is:

$q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.---\mathrm{iv}$

(5) by ii, iii and iv construct a kind of fractional-order different containing y ²liu chaos switched system v be:

$\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}-\mathrm{cxz}\\ d^{q}z/{\mathrm{dt}}^q={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.,a=10,b=40,c=10,d=2.5,h=4,q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.,v$

(6) according to fractional-order different containing y ²liu chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R 4, connect the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,

The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

What 2, a kind of fractional-order was different contains y ²liu chaos switched system circuit, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R 4, connect the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,

The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,

The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;

The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;

The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.

Resistance R 1=R3=R6=R7=R10=R12=10kW in circuit, R8=100W, R9=250W, R4=2.5kW, R2=R5=10kW, R11=40kW, R13=100kW, R14=80kW, Rx11=Ry11=Rz11=62.84MW, Rx12=Ry12=Rz12=250kW, Rx13=Ry13=Rz13=2.5kW, Rx21=Ry21=Rz21=0.636MW, Rx22=Ry22=Rz22=0.3815MW, Rx23=Ry23=Rz23=0.5672MW, Cx11=Cy11=Cz11=1.2mF, Cx12=Cy12=Cz13=1.8mF, Cx13=Cy13=Cz13=1.1mF, Cx21=Cy21=Cz21=15.75mF, Cx22=Cy22=Cz22=0.1575mF, Cx23=Cy23=Cz23=633.5nF.

Certainly, above-mentioned explanation is not limitation of the present invention, and the present invention is also not limited only to above-mentioned giving an example, and variation, remodeling, interpolation or replacement that those skilled in the art make in essential scope of the present invention, also belong to protection scope of the present invention.

Claims (2)

1. A fractional-order different containing y ²liu chaos switched system method, it is characterized in that being, comprise the following steps:

   (1) containing y ²the equation of Liu chaos system i be:

   $\left\{\begin{array}{c}\mathrm{dx}/\mathrm{dt}=a(y-x)\\ \mathrm{dy}/\mathrm{dt}=\mathrm{bx}-\mathrm{cxz}\\ \mathrm{dz}/\mathrm{dt}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---i,a=10,b=40,c=10,d=2.5,h=4$

   (2) 0.9 rank are containing y ²the equation of Liu chaos system ii be:

   $\left\{\begin{array}{c}{d}^{0.9}x/{\mathrm{dt}}^{0.9}=a(y-x)\\ d^{0.9}y/{\mathrm{dt}}^{0.9}=\mathrm{bx}-\mathrm{cxz}\\ d^{0.9}z/{\mathrm{dt}}^{0.9}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---\mathrm{ii},a=10,b=40,c=10,d=2.5,h=4$

   (3) 0.1 rank are containing y ²the equation of Liu chaos system iii be:

   $\left\{\begin{array}{c}{d}^{0.1}x/{\mathrm{dt}}^{0.1}=a(y-x)\\ d^{0.1}y/{\mathrm{dt}}^{0.1}=\mathrm{bx}-\mathrm{cxz}\\ d^{0.1}z/{\mathrm{dt}}^{0.1}={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.---\mathrm{ii},a=10,b=40,c=10,d=2.5,h=4$

   (4) structure switching function q=f (x), wherein the expression formula iv of f (x) is:

   $q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.---\mathrm{iv}$

   (5) by ii, iii and iv construct a kind of fractional-order different containing y ²liu chaos switched system v be:

   $\left\{\begin{array}{c}{d}^{q}x/{\mathrm{dt}}^q=a(y-x)\\ d^{q}y/{\mathrm{dt}}^q=\mathrm{bx}-\mathrm{cxz}\\ d^{q}z/{\mathrm{dt}}^q={\mathrm{hy}}^2-\mathrm{dz}\end{array}\right.,a=10,b=40,c=10,d=2.5,h=4,q=f\left(x\right)=\left\{\begin{array}{cc}0.9& x>0\\ 0.1& x\&le;0\end{array}\right.,v$

   (6) according to fractional-order different containing y ²liu chaos switched system v constructing analog Circuits System, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

   The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R 4, connect the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,

   The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,

   The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;

   The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;

   The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.
2. A fractional-order different containing y ²liu chaos switched system circuit, it is characterized in that being, utilize operational amplifier U1, operational amplifier U2 and resistance and electric capacity form the fractional order inverting integrator of anti-phase adder and different orders, utilize multiplier U3 and multiplier U4 to realize multiplying, utilize analog switch U5 to realize the selection output of analog signal, described operational amplifier U1 and operational amplifier U2 adopt LF347D, described multiplier U3 and multiplier U4 adopt AD633JN, described analog switch U5 adopts ADG888, described operational amplifier U1 connects multiplier U3, multiplier U4 and analog switch U5, described operational amplifier U2 connects multiplier U3 and analog switch U5, described multiplier U3 concatenation operation amplifier U1, described multiplier U4 concatenation operation amplifier U2, described analog switch U5 concatenation operation amplifier U1 and operational amplifier U2,

   The 1st pin of described operational amplifier U1 joins by resistance R 3 and the 2nd pin of operational amplifier U1, join by resistance R 7 and the 6th pin of operational amplifier U1, the 3rd of operational amplifier U1, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 6th pin of operational amplifier U1 is in parallel by resistance R y11 and capacitor C y11's, connecting resistance Ry12 is in parallel with capacitor C y12's, again after connecting resistance Ry13 and capacitor C y13 in parallel, connect again the 7th pin of analog switch U5, in parallel by resistance R y21 and capacitor C y21, connecting resistance Ry22 is in parallel with capacitor C y22's, again after connecting resistance Ry23 and capacitor C y23 in parallel, connect again the 5th pin of analog switch U5, the 7th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 2, meet the 1st of multiplier U4, 3 pins, the 8th pin of operational amplifier U1 connects the 2nd pin of operational amplifier U1 by resistance R 4, connect the 9th pin of operational amplifier U1 by resistance R 5, connect the 2nd pin of operational amplifier U2, connect the 1st pin of multiplier U3, the 9th pin of operational amplifier U1 is in parallel by resistance R x11 and capacitor C x11's, connecting resistance Rx12 is in parallel with capacitor C x12's, again after connecting resistance Rx13 and capacitor C x13 in parallel, connect again the 2nd pin of analog switch U5, in parallel by resistance R x21 and capacitor C x21, connecting resistance Rx22 is in parallel with capacitor C x22's, again after connecting resistance Rx23 and capacitor C x23 in parallel, connect again the 4th pin of analog switch U5, the 14th pin of operational amplifier U1 connects the 13rd pin of operational amplifier U1 by resistance R 1, connect the 9th pin of operational amplifier U1 by resistance R 6,

   The 6th of described operational amplifier U2, 7 pins are unsettled, the 3rd of described operational amplifier U2, 5, 10, 12 pin ground connection, the 4th pin meets VCC, the 11st pin meets VEE, the 1st pin of operational amplifier U2 is by the series connection ground connection of resistance R 13 and R14, meet the 8th of analog switch U5 by R13, 9 pins, the 8th pin of operational amplifier U2 connects the 9th pin of operational amplifier U2 by resistance R 11, connect the 3rd pin of multiplier U3, the 9th pin of operational amplifier U2 is in parallel by resistance R z11 and capacitor C z11's, connecting resistance Rz12 is in parallel with capacitor C z12's, again after connecting resistance Rz13 and capacitor C z13 in parallel, connect again the 10th pin of analog switch U5, in parallel by resistance R z21 and capacitor C z21, connecting resistance Rz22 is in parallel with capacitor C z22's, again after connecting resistance Rz23 and capacitor C z23 in parallel, connect again the 12nd pin of analog switch U5, the 14th pin of operational amplifier U2 connects the 13rd pin of operational amplifier U2 by resistance R 10, connect the 9th pin of operational amplifier U2 by resistance R 12,

   The 1st pin of described multiplier U3 connects the 8th pin of operational amplifier U1, the 3rd pin connects the 8th pin of operational amplifier U2, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, the 7th pin connects the 6th pin of operational amplifier U1 by resistance R 8, the 8th pin meets VCC;

   The 1st, 3 pins of described multiplier U4 connect the 7th pin of operational amplifier U1, the equal ground connection of the 2nd, 4,6 pin, and the 5th pin meets VEE, and the 7th pin connects the 13rd pin of operational amplifier U2 by resistance R 9, and the 8th pin meets VCC;

   The 1st pin of described analog switch U5 meets VCC, the 16th pin ground connection, and the 13rd, 14,15 pins are unsettled, and the 3rd pin connects the 8th pin of operational amplifier U1, and the 6th pin connects the 7th pin of operational amplifier U1, and the 11st pin connects the 8th pin of operational amplifier U2.