CN106936565B - L-shaped multi-scroll chaotic circuit - Google Patents
L-shaped multi-scroll chaotic circuit Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
Abstract
The invention provides an L-shaped multi-scroll chaotic circuit which comprises a first hysteresis circuit, a second inverting and adding circuit, a third inverting and adding circuit, a fourth inverting and adding circuit, a first integrating circuit, a second integrating circuit, a first inverter and a second inverter. The switching function of the chaotic circuit is realized by the first hysteresis circuit and the second hysteresis circuit, and the characteristics of the hysteresis circuits are that the output state numbers of the independent variables are different when the independent variables are changed from small to large and from large to small, so that an L-shaped chaotic attractor can be generated, and the defect that the output state of the traditional grid-shaped or strip-shaped chaotic attractor is single is overcome; the chaotic circuit is realized by the improved hysteresis comparator, the addition circuit, the integration circuit and other existing circuit modules, has a simple circuit structure, is convenient to adjust and is suitable for wide popularization.
Description
Technical Field
The invention relates to a multi-scroll chaotic circuit, in particular to an L-shaped multi-scroll chaotic circuit which can generate an L-shaped multi-scroll chaotic attractor.
Background
The multi-scroll chaotic circuit is a common chaotic circuit and is widely applied to the fields of industrial control, communication and the like. The multi-scroll chaotic circuit can generate a multi-scroll chaotic attractor, the shape of which is determined according to the balance point of a chaotic circuit equation, and most of which are in a grid shape or a strip shape. The multi-scroll chaotic circuit has the characteristics of simple circuit structure and wide parameter range, and is commonly used in chaotic encryption and chaotic communication.
However, when the independent variable is increased from small or decreased from large, the switching control function adopted by the existing multi-scroll chaotic circuit has the same output state value, so that the output state is single, and the arrangement mode of the generated chaotic attractors is only grid-shaped or strip-shaped. Therefore, in chaotic encryption, chaotic communication and other systems, the chaotic key confidentiality realized by adopting the existing multi-scroll chaotic circuit is poor and is easy to crack.
Disclosure of Invention
The invention aims to provide a chaotic circuit capable of generating an L-shaped multi-scroll chaotic attractor, aiming at the defect that the existing chaotic circuit can only generate a grid-shaped or strip-shaped multi-scroll chaotic attractor.
Therefore, the invention adopts the following technical scheme:
an L-shaped multi-scroll chaotic circuit comprises a first hysteresis circuit, a second inverting adder circuit, a third inverting adder circuit, a fourth inverting adder circuit, a first integrating circuit, a second integrating circuit, a first inverter and a second inverter, wherein:
the structure of the first hysteresis circuit is the same as that of the second hysteresis circuit, the output end of the first hysteresis circuit is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverting adder circuit and the input end of the third inverting adder circuit, the output end of the third inverting adder circuit is connected with the input end of the fourth inverting adder circuit, the output end of the fourth inverting adder circuit is connected with the input end of the second integrating circuit, the output end of the second integrating circuit is connected with the input end of the second hysteresis circuit, the input end of the second inverting adder circuit and the input end of the fourth inverting adder circuit, the output end of the second inverter is connected with the input end of the second inverting adder circuit and the input end of the fourth inverting adder circuit, the output end of the second inverting adder circuit is connected with the input end of the first integrating circuit, and the output end of the first inverting adder circuit is connected with the input end of the second inverting adder circuit. And the output end of the first integrating circuit forms an X output end, and the output end of the second integrating circuit forms a Y output end.
Further, the first hysteresis circuit is composed of a first hysteresis comparator, a second hysteresis comparator and a first inverting adder circuit, wherein:
the first hysteresis comparator consists of a first operational amplifier U1, a first resistor R1 and a second resistor R2; the non-inverting input end of the first operational amplifier U1 is grounded through a first resistor R1, and a second resistor R2 is connected between the non-inverting input end and the output end;
the second hysteresis comparator consists of a second operational amplifier U2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first diode D1 and a second diode D2; the non-inverting input end of the second operational amplifier U2 is grounded through a third resistor R3, and a fourth resistor R4, a fifth resistor R5, a first diode D1 and a second diode D2 are connected between the non-inverting input end and the output end in parallel; the fourth resistor R4 is connected with the first diode D1 in series, the fifth resistor R5 is connected with the second diode D2 in series, and the cathode of the first diode D1 and the anode of the second diode D2 are connected with the output end of the second operational amplifier U2;
the first inverting addition circuit consists of a third operational amplifier U3, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8; the non-inverting input end of the third operational amplifier U3 is grounded, the inverting input end is connected with the output end of the first operational amplifier U1 through a sixth resistor R6, and is connected with the output end of the second operational amplifier U2 through a seventh resistor R7, and an eighth resistor R8 is connected between the inverting input end and the output end;
and the inverting input ends of the first operational amplifier U1 and the second operational amplifier U2 form the input end of the first hysteresis circuit, and the output end of the third operational amplifier U3 forms the output end of the first hysteresis circuit.
Further, the second inverting adder circuit is composed of a fourth operational amplifier U4, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a fourteenth resistor R14; the non-inverting input end of the fourth operational amplifier U4 is grounded, the inverting input end is respectively connected with a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13, and a fourteenth resistor R14 is connected between the inverting input end and the output end; the other ends of the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13 respectively form four input ends of a second inverting adder circuit, and the output end of the fourth operational amplifier U4 forms the output end of the second inverting adder circuit; and the other end of the tenth resistor R10 is connected with the output end of the first integrating circuit, the other end of the eleventh resistor R11 is connected with the output end of the first inverter, the other end of the twelfth resistor R12 is connected with the output end of the second inverter, and the other end of the thirteenth resistor R13 is connected with the output end of the second integrating circuit.
Further, the first integrating circuit is composed of a fifth operational amplifier U5, a fifteenth resistor R15 and a first capacitor C1; the non-inverting input end of the fifth operational amplifier U5 is grounded, the inverting input end is connected with a fifteenth resistor R15, and a first capacitor C1 is connected between the inverting input end and the output end; the other end of the fifteenth resistor R15 forms an input end of the first integrating circuit, and the output end of the fifth operational amplifier U5 forms an output end of the first integrating circuit.
Further, the first inverter is composed of a sixth operational amplifier U6, a sixteenth resistor R16 and a seventeenth resistor R17; the non-inverting input end of the sixth operational amplifier U6 is grounded, the inverting input end is connected with a sixteenth resistor R16, and a seventeenth resistor R17 is connected between the inverting input end and the output end; the other end of the sixteenth resistor R16 forms an input terminal of the first inverter, and the output terminal of the sixth operational amplifier U6 forms an output terminal of the first inverter.
Further, the third inverting circuit is composed of a seventh operational amplifier U7, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20; the non-inverting input end of the seventh operational amplifier U7 is grounded, the inverting input end is connected with an eighteenth resistor R18 and a nineteenth resistor R19, and a twentieth resistor R20 is connected between the inverting input end and the output end; the other ends of the eighteenth resistor R18 and the nineteenth resistor R19 form two input ends of a third inverting circuit respectively, the output end of the seventh operational amplifier U7 forms the output end of the third inverting circuit, the other end of the eighteenth resistor R18 is connected with the output end of the first integrating circuit, and the other end of the nineteenth resistor R19 is connected with the output end of the first inverter.
Further, the fourth inverting adder circuit is composed of a tenth operational amplifier U10, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23 and a twenty-fourth resistor R24; the non-inverting input end of the tenth operational amplifier U10 is grounded, the inverting input end is respectively connected with a twenty-first resistor R21, a twenty-second resistor R22 and a twenty-third resistor R23, and a twenty-fourth resistor R24 is connected between the inverting input end and the output end; the other ends of the twenty-first resistor R21, the twenty-second resistor R22 and the twenty-third resistor R23 respectively form three input ends of a fourth inverting and adding circuit, the output end of the tenth operational amplifier U10 forms the output end of the fourth inverting and adding circuit, the other end of the twenty-first resistor R21 is connected with the output end of the second integrating circuit, the other end of the twenty-second resistor R22 is connected with the output end of the third inverting and adding circuit, and the other end of the twenty-third resistor R23 is connected with the output end of the second inverter.
Further, the second integrating circuit is composed of a ninth operational amplifier U9, a twenty-fifth resistor R25 and a second capacitor C2; the non-inverting input end of the ninth operational amplifier U9 is grounded, the inverting input end is connected with a twenty-fifth resistor R25, and a second capacitor C2 is connected between the inverting input end and the output end; the other end of the twenty-fifth resistor R25 forms an input end of the second integrating circuit, and the output end of the ninth operational amplifier U9 forms an output end of the second integrating circuit.
Further, the second inverter is composed of an eighth operational amplifier U8, a twenty-sixth resistor R26 and a twenty-seventh resistor R27; the non-inverting input end of the eighth operational amplifier U8 is grounded, the inverting input end is connected with a twenty-sixth resistor R26, and a twenty-seventh resistor R27 is connected between the inverting input end and the output end; the other end of the twenty-sixth resistor R26 forms an input end of the second inverter, and the output end of the eighth operational amplifier U8 forms an output end of the second inverter.
The circuit principle of the invention is as follows:
the L-shaped multi-scroll chaotic circuit can generate an L-shaped multi-scroll chaotic attractor, which means that the multi-scroll attractor output by the chaotic circuit is arranged in a space in an L shape (shown in figure 5). If the L-shaped multi-scroll chaotic attractor is to be obtained, the balance point of the multi-scroll chaotic attractor needs to be calculated in advance, and then the system orbit is adjusted to be diffused in the subspace of the preset balance point by adjusting the switching function, so that the L-shaped multi-scroll attractor can be obtained. The equation of the L-shaped multi-scroll chaotic circuit is shown in formula 1:
（1）
in the formula (1), the components are as follows,representing the variable->Derivative after derivative of time variable t. In the invention, X is the output signal value of the X output end of the chaotic circuit of the invention, and Y is the output signal value of the Y output end of the chaotic circuit of the invention; />，/>Is real and->Determining an estimated rotational speed of the scroll>Determining the expansion speed of scroll>The value range of the (B) can be obtained by calculating the balance point distribution of the circuit; />，/>Is a system switching function.
The switching function required by the invention is realized by an improved hysteresis circuit, namely a first hysteresis circuit and a second hysteresis circuit, and the characteristics of the hysteresis circuit are as follows: the number of output states when the argument changes from small to large is different from the number of output states when the argument changes from large to small. FIG. 2 is a characteristic diagram of the hysteresis circuit of the present inventionIn (a): the abscissa represents the input state value of the hysteresis circuit and the ordinate represents the output state value of the hysteresis circuit. As can be seen from FIG. 2, when the input state value, i.e., the argument, is small to large, only the minimum value H 1 And a maximum value H n Two output states; h is present when the argument changes from large to small n 、H n-1 …H 2 、H 1 N output states in total, and the transition interval of the output states is (H n - H 1 ) And/n. And according to the switching rule of the system, the following steps are obtained: the L-shaped multi-scroll chaotic attractor generated by the chaotic circuit is 2n-1 in total; and n scrolls are arranged in the x and y directions respectively, and 2n-1 scrolls are arranged in total because the scrolls in the x and y directions are coincident at the minimum output value of the hysteresis circuit.
In summary, the invention has the following beneficial effects:
1. after the circuit is improved, the L-shaped chaotic attractor can be generated, and the defect that the output state of the traditional grid-shaped or strip-shaped chaotic attractor is single is overcome;
2. the invention is realized by the improved hysteresis comparator, the addition circuit, the integration circuit and other existing circuit modules, the circuit structure is simple, and the adjustment is convenient;
3. the number and the size of the output values of the hysteresis circuit can be set according to actual needs, and the hysteresis circuit is suitable for wide popularization.
Drawings
FIG. 1 is a circuit implementation diagram of a hysteresis circuit of the present invention;
FIG. 2 is a characteristic diagram of the hysteresis circuit of the present invention;
FIG. 3 is a characteristic diagram of a hysteresis circuit according to an embodiment of the present invention;
FIG. 4 is a circuit implementation diagram of the L-shaped multi-scroll chaotic circuit of the invention;
fig. 5 is a circuit phase diagram of an L-type multi-scroll chaotic circuit in an x-y plane according to an embodiment of the present invention.
Detailed Description
The design principle of the L-shaped multi-scroll chaotic attractor can be produced by the invention is explained in detail below by taking the design of a 5-coil L-shaped multi-scroll chaotic circuit as an example.
An L-shaped multi-scroll chaotic circuit comprises a first hysteresis circuit, a second inverting adder circuit, a third inverting adder circuit, a fourth inverting adder circuit, a first integrating circuit, a second integrating circuit, a first inverter and a second inverter, wherein:
the first hysteresis circuit and the second hysteresis circuit have the same structure; the output end of the first hysteresis circuit is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverting adder circuit and the input end of the third inverting adder circuit, the output end of the third inverting adder circuit is connected with the input end of the fourth inverting adder circuit, the output end of the fourth inverting adder circuit is connected with the input end of the second integrating circuit, the input end of the second inverting adder circuit and the input end of the fourth inverting adder circuit, the output end of the second hysteresis circuit is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the second inverting adder circuit and the input end of the fourth inverting adder circuit, the output end of the second inverting adder circuit is connected with the input end of the first integrating circuit, and the output end of the first integrating circuit is connected with the input end of the second inverting adder circuit, the input end of the third inverting adder circuit and the input end of the first hysteresis circuit; and the output end of the first integrating circuit forms an X output end, and the output end of the second integrating circuit forms a Y output end.
First, the implementation of the first hysteresis circuit and the second hysteresis circuit is explained. As shown in fig. 1, taking a first hysteresis circuit as an example, the first hysteresis circuit is composed of a first hysteresis comparator, a second hysteresis comparator and a first inverting adder circuit, where:
the first hysteresis comparator consists of a first operational amplifier U1, a first resistor R1 and a second resistor R2; the non-inverting input end of the first operational amplifier U1 is grounded through a first resistor R1, and a second resistor R2 is connected between the non-inverting input end and the output end;
the second hysteresis comparator consists of a second operational amplifier U2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first diode D1 and a second diode D2; the non-inverting input end of the second operational amplifier U2 is grounded through a third resistor R3, and a fourth resistor R4, a fifth resistor R5, a first diode D1 and a second diode D2 are connected between the non-inverting input end and the output end in parallel; the fourth resistor R4 is connected with the first diode D1 in series, the fifth resistor R5 is connected with the second diode D2 in series, and the cathode of the first diode D1 and the anode of the second diode D2 are connected with the output end of the second operational amplifier U2;
the first inverting addition circuit consists of a third operational amplifier U3, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8; the non-inverting input end of the third operational amplifier U3 is grounded, the inverting input end is connected with the output end of the first operational amplifier U1 through a sixth resistor R6, and is connected with the output end of the second operational amplifier U2 through a seventh resistor R7, and an eighth resistor R8 is connected between the inverting input end and the output end;
and the inverting input ends of the first operational amplifier U1 and the second operational amplifier U2 form the input end of the first hysteresis circuit, and the output end of the third operational amplifier U3 forms the output end of the first hysteresis circuit.
The resistance of the first hysteresis circuit takes the value as follows:，/>，，/>，/>. The transition limit of the first hysteresis comparator isOutput value is +.>The method comprises the steps of carrying out a first treatment on the surface of the When the output value of the second hysteresis comparator is +.>At the time, the second diode D2 is turned on, and the jump point of the voltage is +.>The method comprises the steps of carrying out a first treatment on the surface of the When the output value of the second hysteresis comparator is +.>At the time, the first diode D1 is turned on, and the jump point of the voltage is +.>. The output result shown in fig. 3 is obtained after the operation of the first inverting adder circuit. As can be seen from fig. 3, in the present embodiment, the input state value of the first hysteresis circuit, i.e. the argument, has two output states during the small increase, and three output states during the small decrease. The specific function expression is as follows:
when the argument x increases from small
（2）
When the argument x decreases from large:
（3）
the first hysteresis circuit is packaged into a circuit module H1, and the second hysteresis circuit is packaged into a circuit module H2. In this embodiment, the switching function in the equation of the circuit of formula (1) is implemented by the first hysteresis circuit and the second hysteresis circuit, if the input signal value of the first hysteresis circuit is x and the input signal value of the second hysteresis circuit is y, the output value of the first hysteresis circuit is H (x), the output value of the second hysteresis circuit is H (y), and the parameters in the equation (1) are obtained,ω= 15，The circuit equation of the L-shaped multi-scroll chaotic circuit in this embodiment is:
（4）
specific implementations of the L-shaped multi-scroll chaotic circuit are described below. As shown in fig. 4:
the second inverting addition circuit consists of a fourth operational amplifier U4, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13 and a fourteenth resistor R14; the non-inverting input end of the fourth operational amplifier U4 is grounded, the inverting input end is respectively connected with a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13, and a fourteenth resistor R14 is connected between the inverting input end and the output end; the other ends of the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12 and the thirteenth resistor R13 respectively form four input ends of a second inverting adder circuit, and the output end of the fourth operational amplifier U4 forms the output end of the second inverting adder circuit; and the other end of the tenth resistor R10 is connected with the output end of the first integrating circuit, the other end of the eleventh resistor R11 is connected with the output end of the first inverter, the other end of the twelfth resistor R12 is connected with the output end of the second inverter, and the other end of the thirteenth resistor R13 is connected with the output end of the second integrating circuit.
The first integrating circuit consists of a fifth operational amplifier U5, a fifteenth resistor R15 and a first capacitor C1; the non-inverting input end of the fifth operational amplifier U5 is grounded, the inverting input end is connected with a fifteenth resistor R15, and a first capacitor C1 is connected between the inverting input end and the output end; the other end of the fifteenth resistor R15 forms an input end of the first integrating circuit, and the output end of the fifth operational amplifier U5 forms an output end of the first integrating circuit.
The first inverter consists of a sixth operational amplifier U6, a sixteenth resistor R16 and a seventeenth resistor R17; the non-inverting input end of the sixth operational amplifier U6 is grounded, the inverting input end is connected with a sixteenth resistor R16, and a seventeenth resistor R17 is connected between the inverting input end and the output end; the other end of the sixteenth resistor R16 forms an input terminal of the first inverter, and the output terminal of the sixth operational amplifier U6 forms an output terminal of the first inverter.
The third inverting circuit consists of a seventh operational amplifier U7, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20; the non-inverting input end of the seventh operational amplifier U7 is grounded, the inverting input end is connected with an eighteenth resistor R18 and a nineteenth resistor R19, and a twentieth resistor R20 is connected between the inverting input end and the output end; the other ends of the eighteenth resistor R18 and the nineteenth resistor R19 form two input ends of a third inverting circuit respectively, the output end of the seventh operational amplifier U7 forms the output end of the third inverting circuit, the other end of the eighteenth resistor R18 is connected with the output end of the first integrating circuit, and the other end of the nineteenth resistor R19 is connected with the output end of the first inverter.
The fourth inverting addition circuit consists of a tenth operational amplifier U10, a twenty-first resistor R21, a twenty-second resistor R22, a twenty-third resistor R23 and a twenty-fourth resistor R24; the non-inverting input end of the tenth operational amplifier U10 is grounded, the inverting input end is respectively connected with a twenty-first resistor R21, a twenty-second resistor R22 and a twenty-third resistor R23, and a twenty-fourth resistor R24 is connected between the inverting input end and the output end; the other ends of the twenty-first resistor R21, the twenty-second resistor R22 and the twenty-third resistor R23 respectively form three input ends of a fourth inverting and adding circuit, the output end of the tenth operational amplifier U10 forms the output end of the fourth inverting and adding circuit, the other end of the twenty-first resistor R21 is connected with the output end of the second integrating circuit, the other end of the twenty-second resistor R22 is connected with the output end of the third inverting and adding circuit, and the other end of the twenty-third resistor R23 is connected with the output end of the second inverter.
The second integrating circuit consists of a ninth operational amplifier U9, a twenty-fifth resistor R25 and a second capacitor C2; the non-inverting input end of the ninth operational amplifier U9 is grounded, the inverting input end is connected with a twenty-fifth resistor R25, and a second capacitor C2 is connected between the inverting input end and the output end; the other end of the twenty-fifth resistor R25 forms an input end of the second integrating circuit, and the output end of the ninth operational amplifier U9 forms an output end of the second integrating circuit.
The second inverter consists of an eighth operational amplifier U8, a twenty-sixth resistor R26 and a twenty-seventh resistor R27; the non-inverting input end of the eighth operational amplifier U8 is grounded, the inverting input end is connected with a twenty-sixth resistor R26, and a twenty-seventh resistor R27 is connected between the inverting input end and the output end; the other end of the twenty-sixth resistor R26 forms an input end of the second inverter, and the output end of the eighth operational amplifier U8 forms an output end of the second inverter.
Setting the output signal value of the output end of the first integrating circuit as x, and obtaining an output result H (x) at the output end of the first hysteresis circuit H1 after passing through the first hysteresis circuit H1; the output end of the first hysteresis circuit is connected to the input end of the first inverter, and the output value of the output end of the first inverter is. Setting the output signal value of the output end of the second integrating circuit as y, and obtaining an output result H (y) at the output end of the second hysteresis circuit H2 after passing through the second hysteresis circuit H2; the output end of the second hysteresis circuit is connected to the input end of the second inverter, and the output value of the output end of the second inverter is +.>. The output end of the first integrating circuit, the output end of the second integrating circuit, the output end of the first inverter and the output end of the second inverter are respectively connected to the input end of the second inverting adder circuit, and the result obtained at the output end of the second inverting adder circuit is that. The output end of the second inverting adder circuit is connected to the input end of the first integrating circuit, and the output end of the first integrating circuit obtains the result that。
The output end of the first inverter and the output end of the first integrating circuit are connected to the input end of the third inverting and adding circuitThe output end of the third inverting and adding circuit obtains the result thatThe method comprises the steps of carrying out a first treatment on the surface of the The output end of the third inverting adder, the output end of the second integrating circuit and the output end of the second inverter are connected to the input end of the fourth inverting adder, and the output end of the fourth inverting adder obtains the result that. The output end of the fourth inverting adder circuit is connected to the input end of the second integrating circuit, and the output end of the second integrating circuit obtains the result that。
The resistance value is:,,/>,,/>. The equation result of the L-shaped multi-scroll chaotic circuit of the embodiment can be obtained by calculating the output result of the circuit and the formula (4) is as follows:
（5）
the phase diagram of the circuit equation in the x-y plane is shown in fig. 5 according to the output characteristics of the first hysteresis circuit and the second hysteresis circuit shown in equations (2) and (3). As can be seen from FIG. 5, the present invention can produce an L-shaped multi-scroll chaotic attractor, and the phase diagram has 5 scrolls in total, 3 scrolls in the x and y directions, and the scrolls at the L-shaped corners coincide, thus exhibiting 5 scrolls in total.
Claims (1)
1. The utility model provides an L type multi-scroll chaotic circuit which is characterized in that, includes first hysteresis circuit, second inverting addition circuit, third inverting addition circuit, fourth inverting addition circuit, first integrating circuit, second integrating circuit, first inverter and second inverter, wherein:
the structure of the first hysteresis circuit is the same as that of the second hysteresis circuit, the output end of the first hysteresis circuit is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverting adder circuit and the input end of the third inverting adder circuit, the output end of the third inverting adder circuit is connected with the input end of the fourth inverting adder circuit, the output end of the fourth inverting adder circuit is connected with the input end of the second integrating circuit, the output end of the second integrating circuit is connected with the input end of the second hysteresis circuit, the input end of the second inverting adder circuit and the input end of the fourth inverting adder circuit, the output end of the second inverter is connected with the input end of the second inverting adder circuit and the input end of the fourth inverting adder circuit, the output end of the second inverting adder circuit is connected with the input end of the first integrating circuit, and the output end of the first inverting adder circuit is connected with the input end of the second inverting adder circuit. The output end of the first integrating circuit forms an X output end, and the output end of the second integrating circuit forms a Y output end;
the first hysteresis circuit is composed of a first hysteresis comparator, a second hysteresis comparator and a first inverting adder circuit, wherein: the first hysteresis comparator consists of a first operational amplifier (U1), a first resistor (R1) and a second resistor (R2); the non-inverting input end of the first operational amplifier (U1) is grounded through a first resistor (R1), and a second resistor (R2) is connected between the non-inverting input end and the output end; the second hysteresis comparator consists of a second operational amplifier (U2), a third resistor (R3), a fourth resistor (R4), a fifth resistor (R5), a first diode (D1) and a second diode (D2); the non-inverting input end of the second operational amplifier (U2) is grounded through a third resistor (R3), and a fourth resistor (R4), a fifth resistor (R5), a first diode (D1) and a second diode (D2) are connected between the non-inverting input end and the output end in parallel; the fourth resistor (R4) is connected with the first diode (D1) in series, the fifth resistor (R5) is connected with the second diode (D2) in series, the cathode of the first diode (D1) and the anode of the second diode (D2) are connected with the output end of the second operational amplifier (U2); the first inverting addition circuit consists of a third operational amplifier (U3), a sixth resistor (R6), a seventh resistor (R7) and an eighth resistor (R8); the non-inverting input end of the third operational amplifier (U3) is grounded, the inverting input end of the third operational amplifier is connected with the output end of the first operational amplifier (U1) through a sixth resistor (R6), the inverting input end of the third operational amplifier is connected with the output end of the second operational amplifier (U2) through a seventh resistor (R7), and an eighth resistor (R8) is connected between the inverting input end and the output end; the inverting input ends of the first operational amplifier (U1) and the second operational amplifier (U2) form an input end of a first hysteresis circuit, and the output end of the third operational amplifier (U3) forms an output end of the first hysteresis circuit;
the second inverting addition circuit consists of a fourth operational amplifier (U4), a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13) and a fourteenth resistor (R14); the non-inverting input end of the fourth operational amplifier (U4) is grounded, the inverting input end is respectively connected with a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12) and a thirteenth resistor (R13), and a fourteenth resistor (R14) is connected between the inverting input end and the output end; the other ends of the tenth resistor (R10), the eleventh resistor (R11), the twelfth resistor (R12) and the thirteenth resistor (R13) respectively form four input ends of a second inverting adder circuit, and the output end of the fourth operational amplifier (U4) forms the output end of the second inverting adder circuit; the other end of the tenth resistor (R10) is connected with the output end of the first integrating circuit, the other end of the eleventh resistor (R11) is connected with the output end of the first inverter, the other end of the twelfth resistor (R12) is connected with the output end of the second inverter, and the other end of the thirteenth resistor (R13) is connected with the output end of the second integrating circuit;
the first integrating circuit consists of a fifth operational amplifier (U5), a fifteenth resistor (R15) and a first capacitor (C1); the non-inverting input end of the fifth operational amplifier (U5) is grounded, the inverting input end of the fifth operational amplifier is connected with a fifteenth resistor (R15), and a first capacitor (C1) is connected between the inverting input end and the output end; the other end of the fifteenth resistor (R15) forms an input end of the first integrating circuit, and the output end of the fifth operational amplifier (U5) forms an output end of the first integrating circuit;
the first inverter is composed of a sixth operational amplifier (U6), a sixteenth resistor (R16) and a seventeenth resistor (R17); the non-inverting input end of the sixth operational amplifier (U6) is grounded, the inverting input end of the sixth operational amplifier is connected with a sixteenth resistor (R16), and a seventeenth resistor (R17) is connected between the inverting input end and the output end; the other end of the sixteenth resistor (R16) forms an input end of the first inverter, and the output end of the sixth operational amplifier (U6) forms an output end of the first inverter;
the third inverting circuit consists of a seventh operational amplifier (U7), an eighteenth resistor (R18), a nineteenth resistor (R19) and a twentieth resistor (R20); the non-inverting input end of the seventh operational amplifier (U7) is grounded, the inverting input end is connected with an eighteenth resistor (R18) and a nineteenth resistor (R19), and a twentieth resistor (R20) is connected between the inverting input end and the output end; the other ends of the eighteenth resistor (R18) and the nineteenth resistor (R19) form two input ends of a third inverting circuit respectively, the output end of the seventh operational amplifier (U7) forms the output end of the third inverting circuit, the other end of the eighteenth resistor (R18) is connected with the output end of the first integrating circuit, and the other end of the nineteenth resistor (R19) is connected with the output end of the first inverter;
the fourth inverting addition circuit consists of a tenth operational amplifier (U10), a twenty-first resistor (R21), a twenty-second resistor (R22), a twenty-third resistor (R23) and a twenty-fourth resistor (R24); the non-inverting input end of the tenth operational amplifier (U10) is grounded, the inverting input end is respectively connected with a twenty-first resistor (R21), a twenty-second resistor (R22) and a twenty-third resistor (R23), and a twenty-fourth resistor (R24) is connected between the inverting input end and the output end; the other ends of the twenty-first resistor (R21), the twenty-second resistor (R22) and the twenty-third resistor (R23) respectively form three input ends of a fourth inverting and adding circuit, the output end of the tenth operational amplifier (U10) forms the output end of the fourth inverting and adding circuit, the other end of the twenty-first resistor (R21) is connected with the output end of the second integrating circuit, the other end of the twenty-second resistor (R22) is connected with the output end of the third inverting and adding circuit, and the other end of the twenty-third resistor (R23) is connected with the output end of the second inverter;
the second integrating circuit consists of a ninth operational amplifier (U9), a twenty-fifth resistor (R25) and a second capacitor (C2); the non-inverting input end of the ninth operational amplifier (U9) is grounded, the inverting input end of the ninth operational amplifier is connected with a twenty-fifth resistor (R25), and a second capacitor (C2) is connected between the inverting input end and the output end; the other end of the twenty-fifth resistor (R25) forms an input end of a second integrating circuit, and the output end of the ninth operational amplifier (U9) forms an output end of the second integrating circuit;
the second inverter consists of an eighth operational amplifier (U8), a twenty-sixth resistor (R26) and a twenty-seventh resistor (R27); the non-inverting input end of the eighth operational amplifier (U8) is grounded, the inverting input end of the eighth operational amplifier is connected with a twenty-sixth resistor (R26), and a twenty-seventh resistor (R27) is connected between the inverting input end and the output end; the other end of the twenty-sixth resistor (R26) forms an input end of the second inverter, and the output end of the eighth operational amplifier (U8) forms an output end of the second inverter.
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