CN102738095B - 半导体装置以及半导体装置的制造方法 - Google Patents
半导体装置以及半导体装置的制造方法 Download PDFInfo
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- CN102738095B CN102738095B CN201210175731.0A CN201210175731A CN102738095B CN 102738095 B CN102738095 B CN 102738095B CN 201210175731 A CN201210175731 A CN 201210175731A CN 102738095 B CN102738095 B CN 102738095B
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- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Die Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-010786 | 2009-01-21 | ||
JP2009010786 | 2009-01-21 | ||
CN2010100033401A CN101794765B (zh) | 2009-01-21 | 2010-01-21 | 半导体装置以及半导体装置的制造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010100033401A Division CN101794765B (zh) | 2009-01-21 | 2010-01-21 | 半导体装置以及半导体装置的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102738095A CN102738095A (zh) | 2012-10-17 |
CN102738095B true CN102738095B (zh) | 2015-09-23 |
Family
ID=42336275
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201210175731.0A Active CN102738095B (zh) | 2009-01-21 | 2010-01-21 | 半导体装置以及半导体装置的制造方法 |
CN2010100033401A Active CN101794765B (zh) | 2009-01-21 | 2010-01-21 | 半导体装置以及半导体装置的制造方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2010100033401A Active CN101794765B (zh) | 2009-01-21 | 2010-01-21 | 半导体装置以及半导体装置的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US8222744B2 (ja) |
JP (1) | JP5392107B2 (ja) |
KR (1) | KR101634810B1 (ja) |
CN (2) | CN102738095B (ja) |
TW (1) | TWI458054B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI458054B (zh) * | 2009-01-21 | 2014-10-21 | Sony Corp | 半導體裝置及半導體裝置之製造方法 |
US8193036B2 (en) | 2010-09-14 | 2012-06-05 | Stats Chippac, Ltd. | Semiconductor device and method of forming mold underfill using dispensing needle having same width as semiconductor die |
JP5954075B2 (ja) | 2012-09-21 | 2016-07-20 | ソニー株式会社 | 半導体装置及び半導体装置の製造方法 |
US9735043B2 (en) * | 2013-12-20 | 2017-08-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and process |
US9583366B2 (en) * | 2015-03-16 | 2017-02-28 | Asm Technology Singapore Pte Ltd | Thermally-enhanced provision of underfill to electronic devices using a stencil |
US10283428B2 (en) | 2017-06-30 | 2019-05-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method manufacturing the same |
CN115377021A (zh) * | 2022-08-29 | 2022-11-22 | 北京超材信息科技有限公司 | 电子器件模组封装结构及制作方法 |
CN115662959B (zh) * | 2022-12-26 | 2023-09-26 | 长电集成电路(绍兴)有限公司 | 一种芯片封装结构及其制备方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3534501B2 (ja) * | 1995-08-25 | 2004-06-07 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US20020089836A1 (en) * | 1999-10-26 | 2002-07-11 | Kenzo Ishida | Injection molded underfill package and method of assembly |
US6772512B2 (en) * | 2001-01-13 | 2004-08-10 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a flip-chip ball-grid-array package without causing mold flash |
JP3898958B2 (ja) * | 2002-02-18 | 2007-03-28 | ソニーケミカル&インフォメーションデバイス株式会社 | 異方導電性接着剤及び電気装置 |
JP2003324182A (ja) * | 2002-04-30 | 2003-11-14 | Fujitsu Ltd | フリップチップ接合方法及びフリップチップ接合構造 |
JP3639272B2 (ja) * | 2002-08-30 | 2005-04-20 | 株式会社東芝 | 半導体装置、半導体装置の製造方法 |
TWI223421B (en) * | 2003-06-13 | 2004-11-01 | Advanced Semiconductor Eng | Structure of flip chip package |
JP3718205B2 (ja) * | 2003-07-04 | 2005-11-24 | 松下電器産業株式会社 | チップ積層型半導体装置およびその製造方法 |
JP4415717B2 (ja) | 2004-03-23 | 2010-02-17 | ソニー株式会社 | 半導体装置及びその製造方法 |
US7179683B2 (en) * | 2004-08-25 | 2007-02-20 | Intel Corporation | Substrate grooves to reduce underfill fillet bridging |
JP4035733B2 (ja) * | 2005-01-19 | 2008-01-23 | セイコーエプソン株式会社 | 半導体装置の製造方法及び電気的接続部の処理方法 |
JP4760361B2 (ja) * | 2005-12-20 | 2011-08-31 | ソニー株式会社 | 半導体装置 |
JP2007220866A (ja) * | 2006-02-16 | 2007-08-30 | Sony Corp | 半導体装置 |
JP4910512B2 (ja) * | 2006-06-30 | 2012-04-04 | 富士通セミコンダクター株式会社 | 半導体装置および半導体装置の製造方法 |
TWI300614B (en) * | 2006-07-20 | 2008-09-01 | Siliconware Precision Industries Co Ltd | Flip-chip semiconductor package and chip carrier thereof |
US7682872B2 (en) * | 2007-03-02 | 2010-03-23 | Stats Chippac Ltd. | Integrated circuit package system with underfill |
TWI458054B (zh) * | 2009-01-21 | 2014-10-21 | Sony Corp | 半導體裝置及半導體裝置之製造方法 |
-
2010
- 2010-01-06 TW TW099100182A patent/TWI458054B/zh not_active IP Right Cessation
- 2010-01-15 US US12/688,029 patent/US8222744B2/en active Active
- 2010-01-19 KR KR1020100004616A patent/KR101634810B1/ko active IP Right Grant
- 2010-01-20 JP JP2010010091A patent/JP5392107B2/ja not_active Expired - Fee Related
- 2010-01-21 CN CN201210175731.0A patent/CN102738095B/zh active Active
- 2010-01-21 CN CN2010100033401A patent/CN101794765B/zh active Active
-
2011
- 2011-01-13 US US13/005,841 patent/US9425070B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2010192886A (ja) | 2010-09-02 |
CN102738095A (zh) | 2012-10-17 |
KR101634810B1 (ko) | 2016-06-29 |
TWI458054B (zh) | 2014-10-21 |
US8222744B2 (en) | 2012-07-17 |
CN101794765B (zh) | 2012-07-11 |
US20110175239A1 (en) | 2011-07-21 |
US9425070B2 (en) | 2016-08-23 |
JP5392107B2 (ja) | 2014-01-22 |
US20100181680A1 (en) | 2010-07-22 |
KR20100085857A (ko) | 2010-07-29 |
TW201034134A (en) | 2010-09-16 |
CN101794765A (zh) | 2010-08-04 |
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