CN102543775A - 半导体装置的制造方法及制造装置 - Google Patents

半导体装置的制造方法及制造装置 Download PDF

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Publication number
CN102543775A
CN102543775A CN2011102763460A CN201110276346A CN102543775A CN 102543775 A CN102543775 A CN 102543775A CN 2011102763460 A CN2011102763460 A CN 2011102763460A CN 201110276346 A CN201110276346 A CN 201110276346A CN 102543775 A CN102543775 A CN 102543775A
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semiconductor chip
mentioned
thickness
semiconductor device
adhesive linkage
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CN102543775B (zh
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种泰雄
片村幸雄
芳村淳
岩见文宏
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Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Abstract

根据实施方式的半导体装置的制造方法，在半导体晶片的芯片区域的第1面形成粘接层。沿着切割区域将半导体芯片单片化，并经由粘接层阶梯状地层叠半导体芯片。在粘接层的形成中，在第1面中的不以层叠的状态与其它半导体芯片接触的第1区域的至少一部分设置粘接层形成为比与其它半导体芯片接触的第2区域厚的凸部。

Description

半导体装置的制造方法及制造装置
相关申请的引用
本申请要求2010年12月10日提出的日本专利申请编号2010-275988的优先权的利益，该日本专利申请的全部内容在本申请中引用。
技术领域
本发明的实施方式一般涉及半导体装置的制造方法及制造装置。
背景技术
利用具有NAND型闪速存储器等半导体存储芯片的半导体装置，在形成有电路图案的基板上装载了半导体存储芯片。在这样的半导体装置中，由于高密度安装的要求，因此存在多个半导体存储芯片阶梯状地层叠在电路基板上的情况。
在阶梯状地层叠半导体芯片的基础上，由于在上层的半导体芯片中不与下层的半导体芯片接触的区域中进行电极的连接，因此，期望提高芯片的强度(即接合强度)。
发明内容
本发明的实施方式可提高阶梯状地层叠的半导体芯片的接合强度。
根据实施方式，半导体装置的制造方法在多个芯片区域经由切割区域形成的半导体晶片的芯片区域的第1面形成粘接层。沿着切割区域分割半导体晶片，将具有芯片区域的半导体芯片单片化，并经由粘接层阶梯状地层叠半导体芯片。在粘接层的形成中，在第1面中的不以层叠的状态与其它半导体芯片接触的第1区域的至少一部分，设置有粘接层形成为比与其它半导体芯片接触的第2区域厚的凸部。
根据本发明的实施方式，能够提高阶梯状地层叠的半导体芯片的接合强度。
附图说明
图1是用于说明实施方式所涉及的半导体装置的制造方法的流程图。
图2是从表面一侧看半导体晶片的图。
图3是沿着图2所示的A-A线箭头方向的剖视图。
图4是表示实施方式所涉及的半导体装置的制造方法的一个工序的图。
图5是沿着图2所示的A-A线箭头方向的剖视图，是表示经过了图4的工序的状态的图。
图6是表示实施方式所涉及的半导体装置的制造方法的一个工序的图。
图7是沿着图2所示的A-A线箭头方向的剖视图，是表示经过了图6的工序的状态的图。
图8是表示实施方式所涉及的半导体装置的制造方法的一个工序的图。
图9是沿着图2所示的A-A线箭头方向的剖视图，是表示经过了图8的工序的状态的图。
图10是从背面一侧看半导体晶片的图，是表示经过了图8的工序的状态的图。
图11是实施方式所涉及的半导体装置的剖视图。
图12是沿着图10所示的B-B线箭头方向的剖视图，是表示背面涂敷了粘合剂的状态的图。
图13是从半导体晶片拆下的半导体芯片的剖视图。
图14是从背面一侧看半导体芯片的图。
图15是涂敷装置的侧视图。
图16是沿着图15所示的D-D线箭头方向的视图。
图17是实施方式的变形例1所涉及的半导体装置的剖视图。
图18A是实施方式的变形例2所涉及的半导体装置的剖视图。
图18B是实施方式的变形例3所涉及的半导体装置的剖视图。
图19是从背面一侧看图18所示的半导体装置具备的半导体芯片的图。
图20是实施方式的变形例4所涉及的半导体装置的剖视图。
图21是从背面一侧看图20所示的半导体装置具备的半导体芯片的图。
图22是实施方式的变形例5所涉及的半导体装置的剖视图。
图23是从背面一侧看图22所示的半导体装置具备的半导体芯片的图。
具体实施方式
以下，参照附图详细说明实施方式所涉及的半导体装置的制造方法及制造装置。另外，本发明并不受到该实施方式的限制。
图1是用于说明实施方式所涉及的半导体装置的制造方法的流程图。图2是从表面一侧看半导体晶片的图。图3是沿着图1所示的A-A线箭头方向的剖视图。图4是表示实施方式所涉及的半导体装置的制造方法的一个工序的图。图5是沿着图1所示的A-A线箭头方向的剖视图，是表示经过了图4的工序的状态的图。图6是表示实施方式所涉及的半导体装置的制造方法的一个工序的图。图7是沿着图1所示的A-A线箭头方向的剖视图，是表示经过了图6的工序的状态的图。图8是实施方式所涉及的半导体装置的制造方法的一个工序的图。图9是沿着图1所示的A-A线箭头方向的剖视图，是表示经过了图8的工序的状态的图。图10是从背面一侧看半导体晶片的图，是表示经过了图8的工序的状态的图。图11是实施方式所涉及的半导体装置的剖视图。
如图2和图3所示，准备在表面一侧形成半导体电路等的半导体晶片1。半导体晶片1具有设置了多个芯片区域2的表面(第2面)1a和与之相反一侧的背面(第1面)1b。
在芯片区域2形成有包括半导体电路和/或布线层的半导体元件部。在多个芯片区域2之间设置有切割区域3，通过沿着该切割区域3切断半导体晶片1，可分割多个芯片区域2并将半导体芯片9单片化。
在制造半导体装置50时，首先，如图4和图5所示，在半导体晶片1上，从表面1a一侧沿着切割区域3形成沟槽4(步骤S1)。半导体晶片1的沟槽4例如使用具有与切割区域3的宽度相应的刃厚度的刀片5形成。
沟槽4的深度被设定为比半导体晶片1的厚度浅且比单片化的半导体芯片9完成时的厚度深。另外，沟槽4也可以用蚀刻等方式形成。通过在半导体晶片1上形成这种深度的沟槽4，多个芯片区域2分别被划分成与半导体芯片的厚度相应的状态。
接着，如图6和图7所示，在形成了沟槽4的半导体晶片1的表面1a粘贴保护片6(步骤S2)。保护片6在后面的工序中研磨半导体晶片1的背面1b时，保护在芯片区域2设置的半导体元件部。此外，保护片6在背面1b的研磨工序中维持单片化了芯片区域2后的半导体晶片1的形状。作为保护片6，使用例如具有粘接层的聚对苯二甲酸乙二醇酯(PET)片的树脂片。
接着，如图8和图9所示，研磨粘贴了保护片6的半导体晶片1的背面1b(步骤S3)。半导体晶片1的背面1b，例如如图8和/或图9所示，使用研磨盘7机械地研磨。
实施半导体晶片1的背面1b的研磨工序，直到从表面1a一侧形成的沟槽4从背面一侧露出。这样，通过研磨半导体晶片1的背面1b，各芯片区域2被分割，并且半导体芯片9被单片化(也参照图10)。
在该阶段，通过用保护片6保持，各半导体芯片9不会拆散，整体地维持晶片形状。即，用保护片6维持半导体晶片1的形状，并且已分别将半导体芯片9单片化。在单片化了的半导体芯片9之间存在沟槽4。
接着，在半导体晶片1的背面1b涂敷粘合剂(步骤S4)。粘合剂的涂敷例如通过后面详细说明的涂敷装置执行。接着，经由保护片6从半导体晶片1中上推半导体芯片9(步骤S5)，在形成有电路图案的基板51上，在与表面1a和背面1b平行的一个方向上错开且阶梯状地层叠半导体芯片9(步骤S6)。然后，通过对基板51的表面进行树脂制模(步骤S7)，制造半导体装置50(也参照图11)。
接着，对于向半导体晶片1的背面1b涂敷粘合剂进行详细说明。如图12所示，通过步骤S4所示的粘合剂的涂敷，在半导体晶片1的背面1b形成粘接层10。通过该粘接层10，半导体芯片9与在下层层叠的半导体芯片9粘着。
图13是从半导体晶片拆下的半导体芯片9的剖视图。图14是从背面1b一侧看半导体芯片的图。如图13和图14所示，粘接层10的厚度在半导体芯片9的背面1b整体上不是设置成一样，而是在其中一部分设置有形成为比其它区域厚的凸部10a。另外，粘接层10的厚度不仅有膜厚度薄的部分与凸部10a有台阶的情况，而且也有膜厚度平滑变化的情况。即，凸部10a的膜厚度只要至少比其它部分的膜厚度厚就可以。
凸部10a被形成为位于半导体芯片9的背面1b一侧中的不与在下层层叠的半导体芯片9接触的区域(第1区域)P1。在本实施方式中，形成为用凸部10a掩盖整个区域P1。在凸部10a中，粘接层10形成为比与在下层层叠的半导体芯片9接触的区域(第2区域)P2厚。此外，在层叠了半导体芯片9的情况下，凸部10a的厚度成为与基板51的表面接触的厚度。
例如，在半导体芯片9的厚度为20μm、区域P2中的粘接层10的厚度为10μm的情况下，凸部10a中的粘接层的厚度成为约40μm(台阶的高度为30μm)。粘接层10通过在半导体晶片1的背面1b涂敷含有树脂和溶剂的粘合剂并进行半硬化而形成。另外，整个区域P1和凸部10a的形状也可以不完全一致。这是由于凸部10a因管芯接合时的负荷和/或树脂密封工序的负荷等而变形，成为与区域P1的形状一致的缘故。
另外，作为半导体芯片9的单片化的方法，虽然以先进行步骤S3所示的研磨、然后如步骤S1所示的使用刀片5形成沟槽(切割)的所谓先切割为例进行了说明，但是，也可以通过在研磨后进行切割的所谓后切割来将半导体芯片9单片化。
接着，对于用于在半导体晶片1上涂敷粘合剂的涂敷装置进行说明。图15是作为半导体制造装置的涂敷装置的侧视图。图16是沿着图15所示的D-D线箭头方向的视图。在涂敷装置30中设置有基台31、移动部32、装载部33、支撑部34和排出部35等。
基台31呈大致长方体形状，在其底面设置有脚部31a。此外，在与底面相对一侧的面设置有底板31b。在移动部32中设置有导轨32a、移动块32b、安装部32c、驱动部32d等。
导轨32a呈大致矩形的截面形状，并设置在底板31b的顶面。此外，如图15所示，导轨32a在底板31b的长度方向延伸，并如图16所示，分别设置在基台31的两侧。
移动块32b呈大致倒U字形的截面形状，经由未图示的多个滚珠安装在导轨32a上。然后，使移动块32b横跨在导轨32a上并能够在导轨32a上往返复自由移动。安装部32c呈平板状，并设置在移动块32b的顶面。
在驱动部32d中设置有滚珠丝杠部32e、螺母部32f、驱动电机32g等。如图15所示，滚珠丝杠部32e在底板31b的长度方向延伸设置，其两端可以自由转动地安装在基台31上。如图16所示，螺母部32f设置在安装部32c的底面，与滚珠丝杠部32e螺纹接合。滚珠丝杠部32e的一端与伺服电机等驱动电机32g连接。因此，如果通过驱动电机32g，滚珠丝杠部32e被转动驱动，则安装部32e在如图15所示的箭头X的方向被往返地驱动。
在装载部33中内置有未图示的静电卡盘和/或真空卡盘等，在其装载面上放置并保持半导体晶片1(半导体芯片9)。此外，在装载部33中内置有加热器等加热部33a，能够加热在所保持的半导体晶片1上涂敷的粘合剂。另外，加热部33a也可以加热粘合剂，例如使热介质循环而进行加热。此外，也可以与装载部33隔开地设置加热部33a。例如，也可以在能够照射在装载部33上保持的半导体晶片1的位置设置红外线加热器等。即，加热部加热在半导体晶片1上涂敷的粘合剂，使其半硬化。
支撑部34呈大致倒U字形，横跨一对导轨32a，从底板31b上竖立地设置。此外，安装部34b以从支撑部34的架设部34a中突出的方式设置。在该安装部34b上安装排出部35。
排出部35使含有树脂和溶剂的粘合剂向半导体晶片1排出。排出部35通过喷墨法使粘合剂向半导体晶片1排出。喷墨法有通过加热产生气泡并利用膜沸腾现象使液体排出的“热泡式”和利用压电元件的弯曲位移使液体排出的“压电式”，但也可以采用任意一种方式。另外，作为排出部35，可以采用通过喷墨法使液体排出的已知的喷墨头。因此，对其详细的结构省略说明。
存贮部35a经由配管35b与排出部35连接，能够向排出部35提供粘合剂。在存贮部35a中存贮有被调整了粘度的粘合剂。在这种情况下，如前所述，为了抑制排出喷嘴的喷孔堵塞，优选地，降低粘合剂在25℃的粘度。从存贮部35a向排出部35提供粘合剂可以利用位置水头等，也可以使用泵等送液装置。
此外，设置有控制来自排出部35的排出定时和/或排出量等的控制部38。例如，在“压电式”的排出部35的情况下，通过改变对压电元件施加的电压并控制压电元件的工作量，可以控制从各压电元件相对的排出喷嘴排出的粘合剂的液滴的大小，即粘合剂的排出量。因此，能够将粘合剂膜状地附着时的厚度设定为小于等于1μm(微米)。此外，控制部38通过控制驱动电机32g的驱动和/或从排出部35排出粘合剂的排出定时，使粘合剂涂敷在半导体晶片1上的期望区域上。
控制部38根据在存储部39中存储的程序，使涂敷装置执行上述的粘合剂的涂敷。例如，在存储部39中存储的程序中，可以记录表示区域P1、P2的范围的信息和/或表示粘合剂的排出量的信息。或者，也可以在存储部39中存储区域P1、P2和/或表示用于形成区域P1、P2的粘合剂的排出量的表格信息，根据程序的记录，控制部38从存储部39中读出需要的信息，控制驱动电机32g和/或排出部35。
粘接层10通过将涂敷装置30所涂敷的粘合剂半硬化而形成。例如，在区域P1中涂敷粘合剂时，可以通过增加粘合剂的排出量或者增加涂敷次数来形成厚度比区域P2增加的凸部10a。另外，作为凸部10a的形成方法，可以是在涂敷包含凸部10a的整个粘接层10后使其半硬化以形成粘接层10的一并形成。此外，也可以是以区域P2下的粘接层10的厚度在区域P1和区域P2中涂敷粘合剂并使其半硬化之后再次在区域P1涂敷粘合剂并使其半硬化以形成凸部10a的分开形成。
例如，根据一并形成，比分开形成相比，减少了工序数，提高生产效率。另一方面，即使在由于粘合剂的粘度低而在一并形成中难以形成凸部10a的情况下，也容易根据分开形成来形成凸部10a。
如以上说明的，在半导体芯片9的背面1b一侧形成的粘接层10中，由于在区域P1中形成凸部10a，因此，增加了粘接层10的厚度，提高了在区域P1下的半导体芯片9的强度。在此，区域P1由于当在基板51上阶梯状地层叠时不与下层的半导体芯片9粘接，因此，与区域P2相比，强度容易变弱。另一方面，在本实施方式中，由于通过凸部10a谋求提高在区域P1下的半导体芯片9的强度，因此，当在基板51上阶梯状地层叠时，在区域P1下难以发生弯曲等变形。
此外，在本实施方式中，在由于凸部10a与基板51接触而在区域P1上向基板51侧施加力的情况下，在粘接层10(凸部10a)处能够支持区域P1。因此，能够进一步可靠地抑制在半导体芯片9处发生弯曲等变形。
此外，填补基板51与半导体芯片9的间隙的凸部10a在形成粘接层10的工序中一并形成，因此，与将半导体芯片9层叠在基板51上之后填补间隙的情况相比，能够减少工序数。此外，能够谋求操作的简易化。
此外，由于区域P1的强度高，因此，无需将半导体芯片9的厚度设为比其它半导体芯片9厚。其结果，所层叠的半导体芯片9的厚度在各个半导体芯片9中可以设为大致相等。此外，能够降低半导体装置的高度。因此，不需要对每个晶片改变研磨半导体晶片1的背面1b(步骤S3)的条件。因此，能够简化制造工序。此外，能够仅用从同一晶片中单片化的芯片制造半导体装置50。其结果，能够增加半导体芯片9的选择的自由度。
另外，在半导体芯片9的表面沿着平面看的一边形成有电极衬垫40。电极衬垫40通过金属线41的引线接合与在基板51上形成的连接衬垫和/或在其它半导体芯片9上形成的电极衬垫40电连接。该电极衬垫40形成在区域P1的背侧。在这样的构成中，当在电极衬垫40上对金属线41进行引线接合时，向基板51侧的力容易施加在区域P1上。但是，在本实施方式中，通过在粘接层10形成的凸部10a，谋求提高在区域P1下的半导体芯片9的强度。其结果，在引线接合时也难以发生半导体芯片9的变形。
此外，通过使用以喷墨法涂敷粘合剂的涂敷装置30，能够设定各种各样的被涂敷了粘合剂的区域的形状和/或涂敷厚度，容易形成被形成了凸部10a的粘接层10那样的复杂形状。
图17是实施方式的变形例1所涉及的半导体装置的剖视图。如图17所示，在本变形例1中，在将半导体芯片9层叠在基板51上时，以不与基板51接触的厚度形成凸部10a。即使在这样的不使凸部10a与基板51接触的情况下，如果凸部10a的侧面与下层的半导体芯片9的侧面粘接，也能够增加吸收在引线接合时施加的冲击的面积。其结果，能够通过粘接层10的厚度(凸部10a)提高在区域P1下的半导体芯片9的强度。
图18A是实施方式的变形例2所涉及的半导体装置的剖视图。图19是从背面一侧看图18A所示的半导体装置具备的半导体芯片的图。如图18A和图19所示，在本变形例2中，凸部10a并不在整个区域P1中形成，而是在区域P1和区域P2的边界部分形成。即，不需要在电极衬垫40的正下方形成凸部10a。凸部10a与在下层层叠的半导体芯片9的侧面接触。通过与在下层层叠的半导体芯片9接触以及增加凸部10a导致的粘接层10的厚度，能够提高半导体芯片9的强度。此外，由于不在整个区域P1中形成凸部10a，因此，能够降低粘合剂的使用量，有效地利用资源。另外，也可以以不与基板51接触的厚度形成凸部10a。
图18B是实施方式的变形例3所涉及的半导体装置的剖视图。如图18B所示，能够组合图17和图18A的构成。在图18B所示的结构中，也能够进一步可靠地抑制在半导体芯片9中发生弯曲等变形。
图20是实施方式的变形例4所涉及的半导体装置的剖视图。图21是从背面一侧看图20所示的半导体装置具备的半导体芯片的图。如图20和图21所示，在本变形例4中，凸部10a在区域P1的大致整个域中形成，但在半导体芯片9的平面看的外缘部分没有形成。这样，通过在半导体芯片9的外缘部分不形成凸部10a，容易将与基板51接触时的凸部10a的面积抑制到比区域P1向基板51的投影面积小。即，从顶面方向看，即使将基板51的电极衬垫40配置在半导体芯片9的附近，基板51的电极衬垫40也不会被粘合剂10的凸部10a覆盖。这样，能够抑制基板51的电路设计的自由度。
图22是实施方式的变形例5所涉及的半导体装置的剖视图。图23是从背面一侧看图22所示的半导体装置具备的半导体芯片的图。如图22和图23所示，在本变形例5中，凸部10a不在整个区域P1中形成，而是在半导体芯片9的平面看的边缘部中的沿着位于从其与区域P2的边界离开的位置的边缘部形成凸部10a。此外，凸部10a以与基板51接触的厚度形成。
这样，通过将凸部10a沿着位于从其与区域P2的边界离开的位置的边缘部形成，并且使其与基板51接触，在向区域P1施加朝向基板51侧的力的情况下，由凸部10a支撑区域P1并抑制半导体芯片9的变形，同时能够抑制粘合剂的使用量，有效地利用资源。另外，优选地，凸部10a在电极衬垫40的正下方区域形成。其结果，能够由凸部10a支撑区域P1，有效地防止半导体芯片9的变形。
更多的效果和/或变形例可以由本领域的普通技术人员容易地得出。因此，本发明的更广泛的实施方式并不限于如以上所述的特定的详细实施方式和代表性实施方式。因此，在不脱离所附的权利要求及其等同物所限定的总体的发明概念的精神或范围内，可以进行各种各样的变更。

Claims (14)

1.一种半导体装置的制造方法，包括：
在多个半导体芯片的第1面形成粘接层；以及
经由上述粘接层阶梯状地层叠上述半导体芯片；
在上述粘接层的形成中，在上述第1面中的不以层叠的状态与其它半导体芯片的顶面接触的第1区域的至少一部分，设置有上述粘接层形成为比与其它半导体芯片接触的第2区域厚的凸部。
2.如权利要求1所述的半导体装置的制造方法，其中，上述半导体芯片在基板上层叠，在上述凸部处的粘接层的厚度是与上述基板紧贴的厚度。
3.如权利要求1所述的半导体装置的制造方法，其中，上述半导体芯片在基板上层叠，在上述凸部处的粘接层的厚度是与上述基板不接触的厚度。
4.如权利要求1所述的半导体装置的制造方法，其中，上述凸部的侧面与上述其它半导体芯片的侧面相接。
5.如权利要求1所述的半导体装置的制造方法，其中，上述凸部在整个上述第2区域中形成。
6.如权利要求1所述的半导体装置的制造方法，其中，上述半导体芯片在基板上层叠，上述凸部避开平面看的半导体芯片的外缘部分形成，在上述凸部处的粘接层的厚度是与上述基板紧贴的厚度。
7.如权利要求1所述的半导体装置的制造方法，其中，在上述半导体芯片的上述第1面的相反面即第2面形成电极衬垫，上述半导体芯片在基板上层叠，上述凸部在上述电极衬垫的正下方区域形成，在上述凸部处的粘接层的厚度是与上述基板紧贴的厚度。
8.一种半导体装置的制造装置，具备：
装载部，其装载半导体芯片；
排出部，其对在上述装载部中装载的半导体芯片的第1面排出粘合剂，形成粘接层；以及
控制部，其控制上述排出部，以致在上述半导体芯片在基板上阶梯状地层叠时，在上述第1面中的不与其它半导体芯片的顶面接触的第1区域的至少一部分，形成上述粘接层的厚度比与其它半导体芯片接触的第2区域增加的凸部。
9.如权利要求8所述的半导体装置的制造装置，其中，上述半导体芯片在基板上层叠，在上述凸部处的粘接层的厚度是与上述基板紧贴的厚度。
10.如权利要求8所述的半导体装置的制造装置，其中，上述半导体芯片在基板上层叠，在上述凸部处的粘接层的厚度是不与上述基板接触的厚度。
11.如权利要求8所述的半导体装置的制造装置，其中，上述凸部的侧面与上述其它半导体芯片的侧面相接。
12.如权利要求8所述的半导体装置的制造装置，其中，上述凸部在整个上述第2区域中形成。
13.如权利要求8所述的半导体装置的制造装置，其中，上述半导体芯片在基板上层叠，上述凸部避开平面看的半导体芯片的外缘部分形成，在上述凸部处的粘接层的厚度是与上述基板紧贴的厚度。
14.如权利要求8所述的半导体装置的制造装置，其中，在上述半导体芯片的上述第1面的相反面即第2面形成电极衬垫，上述半导体芯片在基板上层叠，上述凸部在上述电极衬垫的正下方区域形成，在上述凸部处的粘接层的厚度是与上述基板紧贴的厚度。
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