CN102467962A - 用于可编程逻辑装置交互连结的相变装置 - Google Patents
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Abstract
本发明公开了一种具有耦合逻辑区块的可配置交互连结的可编程逻辑装置,其中可配置交互连结具有带有可变尺寸的非晶区域的相变元件以决定相变元件是开路或者短路,此将编程路径绝缘于逻辑路径。
Description
技术领域
本发明是关于耦合互连的可配置交互连结,以及带有如此可配置交互连结的可编程逻辑装置。
背景技术
在美国专利第7,307,451与7,511,523号,以及美国专利申请公开本第2007/0146012号所描述的现场可编程门阵列(Field Programmable GateArray,FPGA)装置中,相变材料储存元件是储存FPGA可配置交互连结(configurable interconnection)的设定的控制单元的一部分,控制单元有别于FPGA的实际可配置交互连结,每次打开FPGA,控制单元的内容被读取,且用于决定FPGA可配置交互连结的设定。
在美国专利第7,499,315号与美国专利申请公开本第2006/0171194号所描述的FPGA装置的可编程矩阵中,相变材料储存元件再次地是控制单元的一部分,有别于FPGA的实际可配置交互连结,也要讨论的是直接地连接垂直互连与水平互连的反熔丝装置的使用,如此的反熔丝装置是经由通过经由该反熔丝装置耦合的非常相同垂直互连与水平互连的讯号而编程,因为用于反熔丝装置的编程电路是连接至用于逻辑操作的相同互连,互连具有与编程电路负载关联的额外RC延迟。
发明内容
本发明的一个实施例是一种装置,包括具有多个逻辑区块的一可编程逻辑装置、耦合该多个逻辑区块的多个互连的多个可配置交互连结、以及该多个可配置交互连结的一编程电路,该多个可配置交互连结包括相变元件,每一相变元件耦合该多个逻辑区块的一第一互连以及一第二互连,每一相变元件包括一非晶区域,该非晶区域连接至一加热器以接收来自该编程电路的多个脉冲,该非晶区域将该加热器电性地绝缘于该第一互连与该第二互连,来自该编程电路该多个脉冲是透过有别于该第一互连与该第二互连的一路径而接收。
在若干实施例,该非晶区域将该多个逻辑区块的该第一互连与该第二互连电性地绝缘于该编程电路,当该相变元件透过该非晶区域接收来自该编程电路的该多个脉冲时,因为该非晶区域是高电阻区域,该相变元件的该剩余非非晶区域(举例:结晶区域)是电性地绝缘于该编程电路,类似地,电性地连接至该相变元件的该非非晶区域(举例:结晶区域)的该多个逻辑区块的该多个互连是电性地绝缘于该编程电路,因为来自该编程电路的该多个逻辑区块的该多个互连的电性绝缘,该多个逻辑区块的该多个互连是免除于RC延迟其将在其它方面是起因于编程电路负载。
在若干实施例,每一相变元件具有多种电性阻抗状态,一第一状态具有介于该第一互连与该第二互连之间的一第一电性阻抗,响应具有一第一尺寸的该非晶区域,一第二状态具有介于该第一互连与该第二互连之间的一第二电性阻抗,响应具有大于该第一尺寸的第二尺寸的该非晶区域,该第二电性阻抗高于该第一电性阻抗。
在若干实施例,该编程电路经配置用以供应该多个脉冲,包括不同电性特性的多个脉冲,例如,导致该非晶区域的一可变尺寸的不同电性特性的一第一复位脉冲与一第二复位脉冲,在某实施例,该第一复位脉冲与该第二复位脉冲具有相同延时,该第一复位脉冲与该第二复位脉冲的相同延时的范例是在1-50纳秒(nanosecond)范围之间的值,在另一实施例,该第一复位脉冲与该第二复位脉冲具有不同电压,然在另一实施例,该第一复位脉冲与该第二复位脉冲具有相同延时但不同电压。
若干实施例包括电性地耦合至该多个逻辑区块的该多个互连的多个接地晶体管,该多个接地晶体管将该多个互连电性地绝缘于该编程电路,例如,一编程位线打开该接地晶体管以在该多个可配置交互连结的编程期间电性地将该多个互连接地。
若干实施例包括连接至该非晶区域并在接收来自该编程电路的该多个脉冲的该路径中的该加热器。
本发明的另一个实施例是一种装置,包括耦合一第一节点与一第二节点的一开关,如在此所描述。
本发明的一个实施例是一种装置,包括具有多个逻辑区块的一可编程逻辑装置、耦合该多个逻辑区块的多个互连的多个可配置交互连结、以及该多个可配置交互连结的一编程电路,该编程电路具有多个编程字线与多个编程位线,每一该多个可配置交互连结包括一阻抗存储元件、以及相反导电性型态,如一p型场效应晶体管以及一n型场效应晶体管,之一的第一晶体管与一第二晶体管。
该阻抗存储元件具有不同状态以选择性地电性地耦合该多个逻辑区块的一第一互连与一第二互连,如此以致取决于该阻抗存储元件的状态,该多个逻辑区块的该第一互连与该第二互连被电性地耦合或者解耦合,该阻抗存储元件包括电性地耦合至该多个逻辑区块的该第一互连的一第一端,以及电性地耦合至该第一晶体管与该第二晶体管两者的一第一电流携带终端的一第二端,例如,该阻抗存储元件的该第二端是电性地耦合至一p型场效应晶体管的一源极/漏极终端与一n型场效应晶体管的一源极/漏极终端。
该第一晶体管具有一控制终端、该第一电流携带终端、以及电性地耦合至该多个逻辑电路的该第二互连的一第二电流携带终端,如前所述,该第一电流携带终端是电性地耦合至该阻抗存储元件的该第二端,例如,该第一晶体管是带有一栅极终端、电性地耦合至该阻抗存储元件的该第二端的一源极/漏极终端、以及电性地耦合至该多个逻辑区块的该第二互连的一源极/漏极终端的一p型场效应晶体管。
该第二晶体管具有一控制终端、该第一电流携带终端、以及电性地耦合至该编程电路的一编程位线的一第二电流携带终端,如前所述,该第一电流携带终端是电性地耦合至该阻抗存储元件的该第二端,例如,该第二晶体管是带有一栅极终端、电性地耦合至该阻抗存储元件的该第二端的一源极/漏极终端、以及电性地耦合至该多个逻辑区块的该第二互连的一源极/漏极终端的一n型场效应晶体管。
该第一晶体管与该第二晶体管两者的该多个控制终端是电性地耦合至该编程电路的一相同编程字线,例如,该p型场效应晶体管与该n型场效应晶体管两者是电性地耦合至该编程电路的一相同编程字线。
在若干实施例,在该多个逻辑区块的操作期间,该可编程逻辑装置包括供应一电压至该相同编程字线以打开该第一晶体管并关闭该第二晶体管的控制电路,例如,供应一低或者接地电压至相同编程字线打开该p型晶体管并关闭该n型晶体管,在该多个逻辑区块的操作期间,该第二晶体管(举例:该n型晶体管),在其关闭状态,将该编程位线(在该第二晶体管的一侧)绝缘于该阻抗存储元件、该第一互连、以及该第二互连(在该第二晶体管的他侧)。
在若干实施例,在该阻抗存储元件的编程期间,该可编程逻辑装置包括供应一电压至该相同编程字线以打开该第一晶体管并关闭该第二晶体管的控制电路,例如,供应一高电压至相同编程字线关闭该p型晶体管并打开该n型晶体管,在该阻抗存储元件的编程期间,该第一晶体管(举例:该p型晶体管)将该第二互连(在该第一晶体管的一侧)绝缘于该阻抗存储元件以及该编程位线(在该第一晶体管的他侧)。
据此,在许多实施例,在该多个可配置交互连结的正常操作包括该阻抗存储元件的编程以及该多个逻辑区块的操作期间,只有该第一晶体管是打开,或者只有该第二晶体管是打开。
本发明的另一实施例是一包括一可配置交互连结的一装置,该可配置交互连结包括一阻抗存储元件、以及相反导电性型态的一第一晶体管与一第二晶体管,如在此所述。
附图说明
图1展示FPGA的简化区块示意图;
图2展示图1的FPGA的简化区块示意图的范例部分的较大视图,其展示逻辑区块/单元、连接至逻辑区块/单元与导引逻辑区块/单元的逻辑区块/单元的互连、以及耦合这些互连的可配置交互连结的矩阵;
图3展示图1的可配置交互连结的矩阵的范例部分的较大视图,其展示该矩阵的一可配置交互连结;
图4展示图3的可配置交互连结,其可配置以电性地耦合或者解耦合FPGA的逻辑区块的互连1与2;
图5展示范例SRAM其储存用于配置图4的可配置交互连结的配置信息;
图6展示作为耦合逻辑区块的互连1与2的可配置交互连结的阻抗存储元件的范例电路,其中阻抗存储元件是通过连接至编程字线与编程位线的场效应晶体管而编程;
图7展示作为耦合逻辑区块的互连1与2的可配置交互连结的阻抗存储元件的范例电路,其中阻抗存储元件是通过连接至编程字线与编程位线的双极结晶体管而编程;
图8展示作为耦合逻辑区块的互连1与2的可配置交互连结的阻抗存储元件的范例电路,其中阻抗存储元件是通过连接至编程位线的二极管而编程;
图9展示作为选择性地耦合逻辑区块的互连1与2,以及选择性地将编程位线与逻辑区块的互连1耦合的可配置交互连结的阻抗存储元件与场效应晶体管的范例电路;
图10展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及可配置交互连结是在短路状态,或者低电阻状态,由于非晶区域的小尺寸;
图11展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及可配置交互连结是在开路状态,或者高电阻状态,由于非晶区域的大尺寸;
图12展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及相变元件是经由连接至编程字线与编程位线的场效应晶体管而编程;
图13展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,相变元件是经由连接至编程字线与编程位线的场效应晶体管而编程,以及逻辑区块的互连2是经由连接至编程位线的场效应晶体管而接地;
图14是作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列的顶视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域;
图15是作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列的顶视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及连接至非晶区域的加热器围绕逻辑区块的互连2;
图16是作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列的侧视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及连接至非晶区域的加热器围绕逻辑区块的互连2;
图17至图23展示用以制作作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的流程的侧视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域;
图24至图28展示用以制作作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的流程的顶视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域;以及
图29是带有逻辑区块、耦合逻辑区块的互连的可配置交互连接、以及可配置交互连结的编程电路的范例集成电路的功能区块示意图。
【主要元件符号说明】
L1:互联机1 L2:互联机2
T1:第一晶体管 T2:第一晶体管
D1:二极管 Via:通孔
BL:位线 WL:字线
STI:浅沟道绝缘 S/D:源极/漏极
PMOS:p型MOS晶体管 NMOS:n型MOS晶体管
1:互连 2:互连
12:衬底 14、15:浅沟道绝缘
16、17:源极/漏极 18:字线
20:通孔 21:位线
22、23、24:介电填充 26:加热器与互连材料层
28:光刻蚀图案层
32、34:互连 33:加热器
36:介电填充 38:相变元件
40、41:通孔 42、43:介电填充
50:通孔 51、60:互连
52、62:介电填充
2900:逻辑区块 2908:可配置交互连结
2910:编程电路 2950:集成电路
具体实施方式
可编程逻辑装置(PLDs)是集成电路的一种型态,集成电路能够经编程以执行特定逻辑功能,PLDs包括可编程逻辑阵列(PLA)装置、可编程阵列逻辑(PAL)装置、可擦除可编程逻辑装置(EPLD)、以及可编程门阵列(PGA)。
PLD的一种型态,现场可编程门阵列(FPGA),典型地包括可编程逻辑区块、可配置交互连结(configurable interconnection)、以及输入/输出区块,在一个在集成电路上的实行手段中,输入/输出区块是组装在围绕逻辑区块的晶粒的周缘上,逻辑区块执行各种复杂的逻辑功能,逻辑区块的范例为各种复杂的随机存取存储区块、乘法器、数字讯号处理区块、处理器、频率管理器、延迟锁定回路、布尔逻辑区块以及/或者状态机逻辑、以及同样者,经由编程耦合于逻辑区块的可配置互连,个别可配置逻辑区块的经编程逻辑功能能够被耦合在一起以实行更复杂与定制化逻辑功能。
图1是FPGA的简化区块示意图。
图2展示图1的FPGA的简化区块示意图的范例部分的较大视图,其展示逻辑区块/单元、连接至逻辑区块/单元与导引逻辑区块/单元的逻辑区块/单元的互连、以及耦合这些互连的可配置交互连结的矩阵。
图3展示图1的可配置交互连结的矩阵的范例部分的较大视图,其展示该矩阵的一可配置交互连结。
图4展示图3的可配置交互连结,其可配置以电性地耦合或者解耦合FPGA的逻辑区块的互连1与2。
图5展示范例SRAM其储存用于配置图4的可配置交互连结的配置信息。
图6展示作为耦合逻辑区块的互连1与2的可配置交互连结的阻抗存储元件的范例电路,其中阻抗存储元件是通过连接至编程字线与编程位线的场效应晶体管而编程。
不同的偏压条件被展示。为了编程阻抗存储元件,两条编程字线与编程位线具有Vcc,以及两条互连1与2是接地,为了读取阻抗存储元件,编程字线是接地。
图7展示作为耦合逻辑区块的互连1与2的可配置交互连结的阻抗存储元件的范例电路,其中阻抗存储元件是通过连接至编程字线与编程位线的双极结晶体管而编程。
不同的偏压条件被展示。为了编程阻抗存储元件,编程字线具有一半Vcc,编程位线具有Vcc,以及两条互连1与2是接地,为了读取阻抗存储元件,编程字线是接地。
图8展示作为耦合逻辑区块的互连1与2的可配置交互连结的阻抗存储元件的范例电路,其中阻抗存储元件是通过连接至编程位线的二极管而编程。
不同的偏压条件被展示。为了编程阻抗存储元件,两条编程字线与编程位线具有Vcc,以及两条互连1与2是接地,为了读取阻抗存储元件,编程字线是接地。
图9展示作为选择性地耦合逻辑区块的互连1与2,以及选择性地将编程位线与逻辑区块的互连1耦合的可配置交互连结的阻抗存储元件与场效应晶体管的范例电路。
在互联机2与编程位线之间,p型FET与n型FET串连地连接,互联机2是在p型FET侧上以及编程位线是在n型FET侧上,两个p型FET与n型FET的栅是连接至编程字线,可编程阻抗存储元件具有连接在p型FET与n型FET之间的一端,以及连接至互联机1的另一端,p型FET与n型FET的范例是NMOS与PMOS晶体管,在另一实施例,改变p型FET与n型FET的位置,以及改变编程字线的逻辑以交换逻辑高与逻辑低值。
在编程期间,编程字线,与编程位线具有Vdd,互连1是接地,结果是NMOS打开,且PMOS关闭,互连2是绝缘于编程电路路径与互连1。
在逻辑操作期间,编程字线,与编程位线是接地,结果是NMOS关闭,且PMOS打开,互连的逻辑路径是经由NMOS绝缘于编程电路。
以下通用地讨论相变存储单元的存储操作。读取或者写入至阻抗存储元件的相变存储单元实施例能够经由施加适当电压至对应字线与适当电压或者电流至对应位线以诱发通过存储元件的电流而达成,所施加的电压/电流的电位与延时是取决于所执行的操作,举例:一读取操作或者一写入操作。
在相变存储单元的复位(擦除)操作之中,施加至字线与位线的复位脉冲诱发通过存储元件的电流以引起存储元件的作用区域过渡进入非晶相,藉此设定相变材料至与复位状态关联的电阻值范围之内的电阻,复位脉冲是相对高能量脉冲,足够提升至少存储元件的作用区域的温度高于相变材料的过渡温度之上以及亦高于用以将至少作用区域置于液体状态的熔化温度之上,然后复位脉冲快速地终止,导致相对快速的骤冷时间当作用区域快速地冷却以低于过渡温度之下如此以致作用区域稳定于普通非晶相。
在相变存储单元的设定(或者编程)操作期间,合适振幅与延时的编程脉冲被施加至字线与位线,以诱发通过存储元件的足够提升存储元件的作用区域至少一部分的温度高于过渡温度并导致作用区域的至少一部分从非晶相过渡进入结晶相的电流,此过渡降低存储元件的电阻并设定存储单元至期望的状态。
在储存于存储单元的数据值的读取(或者感应)操作期间,合适振幅与延时的读取脉冲被施加至对应字线与对应位线以冲诱发不导致存储元件经历阻抗状态的改变的流通过存储元件的电流,通过存储单元的电流是取决于存储元件的电阻以及因而储存在存储单元内的数据值,储存在存储单元内的数据值能够,例如,经由位在线的电流与经由感应放大器提供的合适参考电流的比较,而决定,或者,储存在存储单元内的数据值能够,例如,使用源极侧感应经由在存储平面的电导体材料上的电流与合适的参考电流的比较,而决定。
在各种实施例中,可配置交互连结包括阻抗存储元件,可编程阻抗存储材料包括使用不同结晶相变以决定电阻的材料,或者使用电脉冲已改变电阻状态的存储材料,范例包括使用在阻抗随机存取存储器(RRAM)的材料如包括氧化钨(WOX)、NiO、Nb2O5、CuO2、Ta2O5、Al2O3、CoO、Fe2O3、HfO2、TiO2、SrTiO3、SrZrO3、(BaSr)TiO3的金属氧化物,额外范例包括使用在磁电阻式随机存取存储器(MRAM)的材料如自旋矩转移(STT)MRAM,例如CoFeB、Fe、Co、Ni、Gd、Dy、CoFe、NiFe、MnAs、MnBi、MnSb、CrO2、MnOFe2O3、FeOFe2O5、NiOFe2O3、MgOFe2、EuO与Y3Fe5O12的至少其中之一,参见,例如:美国专利申请公开本第2007/0176251号其名为“Magnetic Memory Device and Method of Fabricatingthe Same”,在此并入以供参考,额外范例包括用于可编程金属化单元(PMC)存储器,或者纳米离子存储器的固态电解质材料,例如银掺杂锗硫化物电解质与铜掺杂锗硫化物电解质,参见,例如:N.E.Gilbertet al.,“A macromodel of programmable metallization cell devices”,固态电子49(2005)1813-1819,在此并入以供参考。
存储元件的可编程阻抗材料的实施例包括相变基(phase-change-based)存储材料,包括硫属化物基(chalcogenide based)材料与其它材料,硫属包括,形成周期表VIA族的一部分的,氧(O)、硫(S)、硅(S)与锑(Se)四元素中的任一,硫属化物包含带有更多阳性元素或者基的硫属化合物,硫属化物合金包含带有其它材料如过渡材料的硫属化物的组合,硫属化物合金通常含有一或者更多来自元素周期表IVA族的元素,如锗(Ge)与锡(Sn),往往,硫属化物合金包括包括一或者更多的锑(Sb)、镓(Ga)、铟(In)与银(Ag)的组合,许多相变基存储材料已经在技术文献中描述,包括:Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te与Te/Ge/Sb/S的合金,在Ge/Sb/Te合金的家族,大范围的合金合成物是可行的,此合成物的特征在于TeaGebSb100-(a+b),某研究者已经描述最有用的合金如具有在沉积材料中Te的平均浓度良好地低于70%者,典型地低于约60%以及通常在介于从低到如约23%升到约58%范围之间的Te且最佳地约48%到58%的Te,Ge的浓度大于约5%以及平均在材料中介于从低约8%到约30%范围之间,剩余者通常低于50%,最佳地,Ge的浓度介于从约8%到约40%范围之间,在此合成物中的剩余主要组成元素为Sb,这些百分比是合计100%的组成元素的原子的原子百分比(Ovshinsky美国专利第5,687,112号第10-11栏),由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4与Ge Sb4Te7(Noboru Yamada,“Potential of Ge-Sb-Te Phase-Change OpticalDisks for High-Data-Rate Recording”,SPIE v.3109,第28-37页(1997)),更通常地,过渡金属例如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、铅(Pd)、铂(Pt)与其混合物或者合金可与Ge/Sb/Te组合以形成具有可编程阻抗特质的相变合金,在Ovshinsky‘112第10-13栏中提供了有用的存储材料的具体范例,在此并入以供参考。
在若干实施例中是将硫属化物与其它相变材料掺杂入“杂质”以使用掺杂后的硫属化物来修改导电性、过渡温度、融化温度、与存储元件的其它特质,作为掺杂硫属化物的代表性杂质包括氮、硅、氧、氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛与氧化钛,参见,举例:美国专利第6,800,504号与美国专利申请公开本第U.S.2005/0029502号。
相变合金可以经由电脉冲的施加而从某相态改变到另一相态,据观察一较短、较高振幅脉冲倾向于改变相变材料至普通非晶态,一较长、较低振幅脉冲倾向于改变相变材料至普通结晶态,一较短、较高振幅脉冲的能量是高到足够使结晶结构的键能被打断且短到足够预防原子重新排列进入结晶态,脉冲的适当曲线,无须过度实验,即可被决定,具体地适应于一个特殊相变合金,在以下揭露的章节,相变材料是指GST,且其将被理解为可以使用其它型态的相变材料,在此描述有用于PCRAM的实施的材料为Ge2Sb2Te5。
一种形成硫属化物材料的范例方法是使用在1mTorr~100mTorr的压力下并同Ar、N2以及/或者He等气体源的PVD溅射或者磁控溅射方法,沉积通常是在室温下进行,带有1~5深宽比的准直仪可以用来改进填充表现,为了改进填充表现,也可以使用数十伏特至数千伏特的DC偏压,再者,可以使用DC偏压与准直仪的组合。
一种形成硫属化物材料的范例方法是使用化学气相沉积(CVD)如揭露在美国专利申请公开本第2006/0172067号其名为“Chemical VaporDeposition of Chalcogenide Material”,在此并入以供参考。
在真空或者在N2环境中选择性地执行沉积后退火处理以改进硫属化物材料的结晶态,退火温度典型地介于从100℃至400℃范围之间并带有少于30分钟的退火时间。
在图10~图16中展示的实施例是以导致(i)短路状态或者低电阻以及(ii)开路状态或者高电阻状态的不同状态的相对高能量且短延时的多种类似的复位脉冲为特征,脉冲具有介于1V-5V范围之间的大小与1ns至100ns的延时的大小,不管特殊复位脉冲之后的特殊状态,施加设定脉冲使阻抗存储元件预备好面对多种类似复位脉冲其中之一的接续应用。
此不同于许多其它应用,其依赖非常不同复位与设定脉冲以导致不同状态,尤其是(i)相对高能量且短延时的复位脉冲以导致开路状态或者高电阻状态,以及(ii)相对低能量且长延时的设定脉冲以导致短路状态或者低电阻。
图10展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及可配置交互连结是在短路状态,或者低电阻状态,由于非晶区域的小尺寸。
图11展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及可配置交互连结是在开路状态,或者高电阻状态,由于非晶区域的大尺寸。
图12展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及相变元件是经由连接至编程字线与编程位线的场效应晶体管而编程。
图13展示作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,相变元件是经由连接至编程字线与编程位线的场效应晶体管而编程,以及逻辑区块的互连2是经由连接至编程位线的场效应晶体管而接地。
图14是作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列的顶视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域。
图15是作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列的顶视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及连接至非晶区域的加热器围绕逻辑区块的互连2,此实施例节省一个掩模步骤。
图16是作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的范例排列的侧视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域,以及连接至非晶区域的加热器围绕逻辑区块的互连2。
可编程路径包括编程位线BL其连接,通过一个通孔,至晶体管源极/漏极S/D,其它晶体管源极/漏极S/D连接,通过另一个通孔,至加热器,加热器围绕互连2并连接至相变元件的非晶区域,相变元件实体地连接互连1与互连2,互连2是在多层上,经由一个通孔而连接。
图17至图23展示用以制作作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的流程的侧视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域。
在图17,浅沟道绝缘(STI)结构14与15电性地将介于其间的场效应晶体管绝缘于,邻近电子装置,衬底材料(或者掺杂n阱或者掺杂p阱)12是定位于STI结构14与15之间,场效应晶体管包括作为本体的材料12的一部分,源极与漏极区域16与17,以及作为栅极的编程字线18,在代表性的实施例,字线材料可以是掺杂多晶硅,或者其它导电材料如氮化钛或者其它导电氮化物,钨,或者其它金属,再者,可使用如此材料的组合,导电通孔20与位线21电性地连接至源极与漏极16与17,介电填充材料22、23与24围绕导电通孔20与位线21,形成加热器与互连材料层26以覆盖该多个结构。
在图18,形成在加热器与互连材料层26上的光刻蚀图案层28。
在图19,光刻蚀图案掩模层28允许不受光刻蚀图案层28所保护的加热器与互连材料层26区的选择性刻蚀,刻蚀后的剩余物为加热器33与互连32与34,在若干实施例加热器33具有大于通孔20的材料的电性阻抗,加热器33的材料也可以是,例如,包含具有阻抗大于拟形成的存储元件材料的最高电阻状态的材料,在某些实施例加热器33包含掺杂半导体材料,互连32与34是导引至可编程逻辑装置的逻辑区块的不同互连,虽然,在此实施例,为了高效率的制造互连32与34是作为加热器33的相同材料,或者互连32与34是不同于作为加热器33的材料,以额外步骤的成本,在如此不同材料的实施例,互连32与34是任何合适的导电材料。
在图20,介电填充材料36是沉积在加热器33以及互连32与34附近,超量介电填充材料经由平坦化工艺如化学机械抛光(CMP)而移除。
在图21,相变元件38形成在结构的顶部,以连接加热器33以及互连32与34,在Hsiang-Lan Lung(龙翔澜)的美国专利第7,459,717号中讨论了形成桥接相变元件38,在此并入以供参考。
在图22,形成连接互连32与34的通孔40与41,介电填充材料42与43是沉积在通孔40与41附近,超量介电填充材料经由平坦化工艺如化学机械抛光(CMP)而移除。
在图23,形成连接至通孔40的通孔50,以及连接至通孔41的互连51,介电填充材料52沉积在通孔50与互连51之间,且移除超量者,形成互连60以连接至通孔50,介电填充材料62是沉积在通孔50旁,且移除超量者,互连51与60连接至可编程逻辑装置的逻辑区块。
沉积介电填充材料42与43以围绕通孔40与41,超量介电填充材料经由平坦化工艺如化学机械抛光(CMP)而移除。
图24至图28展示用以制作作为耦合逻辑区块的互连1与2的可配置交互连结的相变元件的流程的顶视图,其中相变元件具有相变元件通过其从编程电路接收脉冲的非晶区域。
在图24,字线18形成在作用区域上,分隔源极与漏极区域16与17,字线18是用于可配置互连的编程电路的一部分,源极与漏极区域16与17是在衬底12之内。
在图25,通孔20与位线21形成在源极与漏极区域16与17上,位线21是用于可配置互连的编程电路的一部分。
在图26,形成互连32与34,以及加热器33,加热器33连接通孔20,虽然互连32出现在字线18上,互连32与字线18是经由居中介电填充而分隔。
在图27,相变元件38形成在互连32与34,以及加热器33上。
在图28,形成通孔40与41以连接至互连32与34,接续地,形成至逻辑区块的互连,其导引至可编程逻辑装置的逻辑区块。
图29是带有逻辑区块、耦合逻辑区块的互连的可配置交互连接、以及可配置交互连结的编程电路的范例可编程逻辑装置集成电路的功能区块示意图。
可编程逻辑装置集成电路2950具有多个功能区块(为了方便分隔地展示,虽然每一功能区块在集成电路中是实体地散开并与其它功能区块多次的互连),逻辑区块2900经由可配置交互连结2908而连接,可配置交互连结2908经由编程电路2910而编程,编程电路2910包括,除编程位线与编程字线外,实行可配置交互连结2908的状态改变的控制电路,经由通过编程位线与经由编程字线发送各种脉冲与控制讯号。
虽然本发明经由参照以上所详述的较佳实施例与范例而揭露,这些范例意在说明而非限制之意,因此,本领域技术人员可在不违背本发明的精神对上述实施例进行修改及变化,然皆不脱如本申请权利要求范围所欲保护者。
Claims (10)
1.一种装置,包含:
具有多个逻辑区块的一可编程逻辑装置、耦合该多个逻辑区块的多个互连的多个可配置交互连结、以及该多个可配置交互连结的一编程电路,其中该多个可配置交互连结包括:
多个相变元件,该多个相变元件的每一相变元件耦合该多个逻辑区块的一第一互连以及一第二互连,该多个相变元件的每一相变元件包括:
连接至一加热器以透过有别于该第一互连与该第二互连的一路径接收来自该编程电路的多个脉冲的一非晶区域,其中该非晶区域将该加热器电性地绝缘于该第一互连与该第二互连。
2.根据权利要求1所述的装置,其中该非晶区域将该第一互连与该第二互连电性地绝缘于该编程电路。
3.根据权利要求1所述的装置,其中该多个相变元件的每一相变元件具有多个电性阻抗状态,包括:
介于该第一互连与该第二互连之间的一第一电性阻抗的一第一状态,响应具有一第一尺寸的该非晶区域;
介于该第一互连与该第二互连之间的一第二电性阻抗的一第二状态,该第二电性阻抗高于该第一电性阻抗,响应具有大于该第一尺寸的第二尺寸的该非晶区域。
4.根据权利要求1所述的装置,其中该编程电路经配置用以供应该多个脉冲,包括不同电性特性或包括相同延时但不同电压的一第一复位脉冲与一第二复位脉冲以导致该非晶区域的一可变尺寸。
5.一种装置,包含:
具有多个逻辑区块的一可编程逻辑装置、耦合该多个逻辑区块的多个互连的多个可配置交互连结、以及该多个可配置交互连结的一编程电路,
其中该多个可配置交互连结的该编程电路包括多个编程字线与多个编程位线;
其中每一该多个可配置交互连结包括一阻抗存储元件、以及具有相反导电性型态的一第一晶体管与一第二晶体管,
该阻抗存储元件具有不同状态以选择性地电性地耦合该多个逻辑区块的一第一互连与一第二互连,该阻抗存储元件包括:
电性地耦合至该多个逻辑区块的该第一互连的一第一端,以及
电性地耦合至该第一晶体管与该第二晶体管两者之一的第一电流携带终端的一第二端;
该第一晶体管具有一控制终端、该第一电流携带终端、以及电性地耦合至该多个逻辑电路的该第二互连的一第二电流携带终端;以及
该第二晶体管具有一控制终端、该第一电流携带终端、以及电性地耦合至该多个位线的一编程位线的一第二电流携带终端,
其中该第一晶体管与该第二晶体管两者的该多个控制终端是电性地耦合至该多个编程字线的一相同编程字线。
6.根据权利要求5所述的装置,其中该第一晶体管为一p型场效应晶体管以及该第二晶体管为一n型场效应晶体管。
7.根据权利要求5所述的装置,其中在该多个逻辑区块的操作期间,该可编程逻辑装置包括供应一电压至该相同编程字线以打开该第一晶体管并关闭该第二晶体管的控制电路,该第二晶体管将该编程位线绝缘于该阻抗存储元件、该第一互连、以及该第二互连。
8.根据权利要求5所述的装置,其中在该阻抗存储元件的编程期间,该可编程逻辑装置包括供应一电压至该相同编程字线以打开该第一晶体管并关闭该第二晶体管的控制电路,且该第一晶体管将该第二互连绝缘于该阻抗存储元件与该编程位线。
9.根据权利要求5所述的装置,其中该阻抗存储元件为一相变元件。
10.根据权利要求5所述的装置,其中在该多个可配置交互连结的正常操作包括该阻抗存储元件的编程以及该多个逻辑区块的操作期间,只有该第一晶体管是打开,或者只有该第二晶体管是打开。
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