CN102449760A - 具有阻抗控制接合线和导电参考元件的微电子组件 - Google Patents

具有阻抗控制接合线和导电参考元件的微电子组件 Download PDF

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CN102449760A
CN102449760A CN2010800208512A CN201080020851A CN102449760A CN 102449760 A CN102449760 A CN 102449760A CN 2010800208512 A CN2010800208512 A CN 2010800208512A CN 201080020851 A CN201080020851 A CN 201080020851A CN 102449760 A CN102449760 A CN 102449760A
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microelectronic device
micromodule
contact
conducting
conductive
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贝尔加桑·哈巴
布赖恩·马库茨
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Publication of CN102449760A publication Critical patent/CN102449760A/zh
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Abstract

一种微电子组件可以包括:微电子装置(310),所述微电子装置具有暴露在其表面(328)处的装置触点(312);和互连元件,所述互连元件具有元件触点(340)并且具有与所述微电子装置相邻的面。例如接合线的导电元件(365)将导电触点与元件触点连接,并具有在微电子装置的表面上方的布线中延伸的部分。导电层(360)具有以在导电元件的多个布线上方或下方的至少基本上均匀的距离设置的导电表面(375)。在一些情况下,导电材料(360)可具有沿第一和第二水平方向的、小于所述微电子装置的第一和第二相应尺寸(324,334)的第一和第二尺寸(326,336)。所述导电材料(360)可连接到参考电势源,以对所述导电元件实现所需的阻抗。

Description

具有阻抗控制接合线和导电参考元件的微电子组件
交叉引用
本申请要求2009年9月22日提交的韩国申请No.10-2009-0089470的优先权并且要求2009年3月13日提交的美国临时专利申请No.61/210,063的权益,其公开此处以引用的方式并入。
背景技术
微电子芯片典型地为具有相对面对的、大体为平面的前表面和后表面的扁平体,所述前表面和后表面具有在这些表面之间延伸的边缘。芯片通常在前表面上具有触点,有时也称为焊盘或接合焊盘,在所述触点的前表面上电连接到该芯片之内的电路。典型地,通过将所述芯片使用合适的材料密封来封装所述芯片,以形成具有电连接到芯片触点的的端子的微电子封装。然后,该封装可连接到测试设备,以确定被封装的器件是否符合所需的性能标准。一旦测试时,该封装可通过将封装端子经过例如焊接的合适连接方法连接到印刷电路板(PCB)上的匹配连接盘(land)而连接到更大的电路(例如电子产品中的电路,所述电子产品例如为计算机或移动电话)。
微电子封装可以在晶圆级制造;即,在芯片或管芯仍处于晶圆形式时、制造构成封装的壳体、端点和其他特征。在已经形成管芯之后,使晶圆经受多个附加工艺步骤以在该晶圆上形成封装结构,然后将该晶圆切割以分开单独封装的管芯。晶圆级加工可能是有效的制造方法,因为每个管芯封装的器件封装(footprint)可制成与管芯自身的尺寸相同或几乎相同,由此获得被封装管芯所连接的印刷电路板上的面积的非常有效的利用。
在微电子芯片和一个或多个其他电子部件之间形成导电连接的常用技术是通过线键合(wire bonding)。传统地,线键合工具将线的一端使用热和/或超声能量连接到微电子芯片的焊盘上,然后将该线回线到其他电子部件上的触点,并且使用热和/或超声力形成到其的第二接合点(bond)。
发明内容
本发明人已经意识到,使用线键合技术的问题之一是,沿线的电磁传输可能延伸到围绕该线的空间中,在附近的导体中感应电流,并且造成不期望的辐射和线的失谐。线键合通常还受到自感和外部噪声(例如来自附近的电子部件)的影响。最终,这产生电阻抗问题。这些问题可能由于微电子芯片和其他电子部件上的触点之间的节距变得更小、由于芯片在更高的频率下操作以及由于大量原始焊盘的使用变得更平常而变得更严重。
本文描述了用于微电子组件的多种结构和制造技术。根据一个实施例的微电子组件包括:线键合到一个或多个互连元件的微电子装置,所述互连元件例如为微电子子组件,如基板、芯片载体、带等。所述微电子装置和所述一个或多个其他互连元件之间的接合线在一个实施例中使用绝缘线形成。所述绝缘线可以是设置有绝缘护套的线,例如可通过使用绝缘材料涂布该线来提供。在接合线导电连接到所述微电子装置的触点和互连元件的相应触点之后,可将足够量的绝缘材料分配(或者滴涂;dispensing)到接合线的端部,以绝缘触点的任何暴露部分和在端部处接合线的任何暴露导电部分。
接合线最初形成在芯片上时,接合线的绝缘涂层可较薄。例如,接合线上可得的绝缘包覆层可具有仅约1微米到几微米的厚度。包覆层(sheathing)的厚度可以是使所述包覆层在线键合工具在将那个端头连接到装置或互连元件的触点来形成接合线的一端之前向接合线的暴露的尖部施加热或火焰时很容易地烧掉。在将接合线连接到装置和互连元件的触点之后,可对接合线施加工艺以将绝缘涂层生长到所需的厚度。例如,特定的绝缘材料可对液体组合物中的分子具有亲和力,这样当暴露于这样的液体组合物时,分子可以选择性地聚集在绝缘涂层上,以让绝缘涂层的厚度增加。在一个实施例中,绝缘涂层的厚度可至少为约30微米(百万分之一米),以在绝缘的接合线和将用作用于其的参考导体的导电材料之间获得所需的分开距离。分开距离是与接合线的横截面尺寸(例如直径)一起部分确定接合线结构的阻抗的因素。绝缘涂层的厚度可更大,例如50微米、75微米、100微米或其他值,取决于将要获得的阻抗。
然后,可将导电密封材料(encapsulant)分配(或者滴涂;dispensing)到接合线上,以填充包围具有绝缘涂层的接合线的空间。导电密封材料可电接触微电子装置上的暴露焊盘、相应的互连元件或两者,以连接到参考电压,所述参考电压例如为地、电源或至少与微电子装置的操作重要的频率关联而稳定的其他电压。导电密封材料对微电子组件提供多个优点。例如,所述导电密封材料可提供用于线的屏蔽和机械保护。在一些实施中,额外的层(导电和不导电的)可施加在导电密封材料上。
在另一个实施例中,非绝缘线用于在微电子装置和一个或多个互连元件之间形成接合线。在两端连接接合线之后,介电材料可分配到非绝缘接合线上,以覆盖所述端部和在其间的线长。介电材料可给非绝缘线提供绝缘、屏蔽和机械保护。当介电材料已经分配时,导电层被施加在介电材料之上。可根据传输线的例如根据下面的电路要求要实现的特性阻抗来选择导电层的例如尺寸和表面形状的特性。此外,导电层可连接到微电子装置上的暴露焊盘和/或一个或多个互连元件上,以提供到例如地、电源或至少关于对于所述微电子装置的操作重要的频率稳定的其他电压的参考电压源的连接。
在一个实施例中,在微电子组件中,非绝缘线可直接接触导电层,以进一步提供稳定的例如地或电源等导电层参考和该微电子装置的相应的地或电源触点之间的导电互连。
在一个实施例中,导电层具有在所述导电元件或接合线的布线上方或下方中的至少一个处、以至少基本上均匀的距离设置的导电表面。
根据一个实施例,提供一种微电子组件,所述微电子组件可包括微电子装置,所述微电子装置具有表面和暴露在所述表面处的装置触点。所述表面可具有沿第一方向的第一尺寸和沿横向于所述第一方向的第二方向的第二尺寸。微电子组件还包括互连元件,所述互连元件具有与所述微电子装置相邻的面,并且具有多个元件触点。多个导电元件可将装置触点与元件触点连接,这样的导电元件的主要部分具有以在所述微电子装置的表面上方的布线延伸。具有导电表面的导电材料可以基本上均匀的距离设置在所述多个布线的上方或下方中的至少之一处。包括沿第一方向的第一尺寸和沿第二方向的第二尺寸的导电材料的尺寸可小于所述微电子装置的第一尺寸和第二尺寸。这样的导电材料可连接到参考电势源,以对所述导电元件实现所需的阻抗。
根据一个实施例,提供一种微电子组件,所述微电子组件包括微电子装置,所述微电子装置具有表面和暴露在所述表面处的装置触点。所述组件可还包括互连元件,所述互连元件具有与所述微电子装置相邻的面和多个元件触点。多个导电元件可连接所述装置触点和所述元件触点,所述导电元件具有在所述微电子装置的表面上方延伸的布线。具有导电表面的导电材料可以与导电元件的长度的至少主要的部分以至少基本上均匀的距离沿着所述导电元件上方或所述导电元件下方的方向中的至少一个设置。导电材料可连接到参考电势源,这样对导电元件实现所需的阻抗。所述导电表面可进一步限定这样的平面,所述平面至少基本上平行于其中导电元件行进的平面。
根据一个实施例,所述导电表面可覆盖在所述导电元件的多个布线上面。在特定的实施例中,导电表面可至少大体为平面。在一个实施例中,所述导电表面可相对于所述微电子装置的表面成角度倾斜。
导电元件可布置成使所述多个布线包括至少接合线的部分。在特定的实施例中,导电元件可以是接合线。
在一个实施例中,接合线可以多个被连接的台阶延伸,并且所述导电表面可至少基本上平行于所述接合线的多个台阶以台阶式延伸。
所述互连元件可包括介电元件。在一个实施例中,所述互连元件可包括参考触点,所述参考触点可连接到参考电势源,所述导电材料可与所述参考触点导电连接,以形成导电连接。
在特定的实施例中,介电元件可包括沿远离所述微电子元件的表面的方向确定的、厚度小于200微米的聚合物元件。在一个实施例中,所述聚合物元件可以是片状元件,并且可以是可变形的或不可变形的。在一个实施例中,导电元件可以冶金方式键合到芯片触点。
在一个实施例中,所述导电表面可通过绝缘材料与接合线的多个布线分开。绝缘材料可以例如至少基本上填充空间,在所述空间中,所述接合线的多个布线延伸通过所述空间。
所述导电材料可结合到暴露在所述互连元件的表面处的参考触点,并且在一个实施例中可与所述互连元件的表面相顺应。所述互连元件可包括将所述参考触点电连接到参考电势源的导体。
微电子组件的参考导电元件可具有在沿着所述微电子装置表面的方向上延伸的布线,在一个实施例中,所述导电材料可结合到所述参考导电元件的布线。
在一个实施例中,导电材料可具有至少大体平面的导电表面,并且这样的表面可与所述导电元件由电介质,即绝缘材料以至少基本上均匀的距离分开。导电材料可包括设置在至少大体平面的导电表面下方的连接部。在一个实施例中,所述连接部可具有到所述参考导电元件的机械连接和电连接。
在特定的实施例中,所述参考导电元件的布线可位于至少基本上与所述导电元件的多个布线相同的平面中。
在一个实施例中,绝缘材料可具有外表面和沿其外表面向内延伸的多个凹槽,并且该导电材料可设置在所述凹槽中。这样的凹槽可包括与连接到所述装置触点的接合线的升高部分相邻设置的凹槽。
在特定的实施例中,接合线可包括沿着所述微电子装置的主表面在第一方向上延伸的部分。在该情况下,所述凹槽可包括在所述侧向延伸的接合线部分之间沿所述第一方向延伸的凹槽。
在一个实施例中,导电材料的边缘可与所述互连元件的边缘相邻设置。
在特定的实施例中,装置触点可暴露在所述微电子装置的前表面处,并且所述微电子装置可具有远离所述前表面的后表面,以及在所述前和后表面之间延伸的边缘。所述后表面可安装到所述互连元件,所述导电元件可延伸超出所述微电子装置的边缘。
根据本发明的一个实施例,提供一种微电子组件,所述微电子组件包括微电子装置,所述微电子装置具有前表面、从所述前表面远离的后表面和沿所述前表面延伸的一个或多个表面导电元件,所述微电子装置具有暴露在所述前表面处的装置触点。所述组件的互连元件可包括在所述微电子装置的后表面下面的介电元件,这样的互连元件在其上具有多个元件触点。多个升高的导电元件可连接所述装置触点与所述元件触点。多个升高的导电元件可以将所述装置触点与所述元件触点连接。所述升高的导电元件可具有这样的主要部分,所述主要部分与所述表面导电元件距离第一高度且至少大体上平行于所述一个或者多个表面导电元件的布线延伸。在这样的实施例中,一个或多个表面导电元件可连接到参考电势源,这样对所述升高导电元件实现所需的阻抗。
根据这样的实施例,一个或多个表面导电元件可包括结合到所述微电子装置的前表面的金属层。粘合剂可将一个或多个表面导电元件粘合到所述微电子装置的前表面。在一个实施例中,所述金属层可包括开口,其中所述表面导电元件通过所述金属层中的开口连接到所述装置触点。
根据一个实施例,提供一种微电子组件,所述微电子组件包括微电子装置,所述微电子装置具有表面和暴露在该表面处的装置触点。所述组件的互连元件可具有与所述微电子装置相邻的面,并且具有多个元件触点。多个接合线可连接所述装置触点与所述元件触点。绝缘材料可包覆接合线中的各接合线,这样的绝缘材料通常具有大于约30微米的厚度,这样的厚度至少基本上沿所述导电元件的大部分长度均匀。所述组件可还包括导电材料,所述导电材料与所述绝缘材料的外表面形状一致,并且填充所述绝缘包覆的接合线之间的空间。这样的导电材料可连接到参考电势源,这样对所述导电元件实现所需的阻抗。
在特定的实施例中,可提供绝缘体(insulative masses),所述绝缘体将至少所述装置触点与所述导电材料分开。所述组件可还包括额外的绝缘体,所述额外的绝缘体将至少所述元件触点与所述导电材料分开。
附图说明
图1A是根据一个实施例的微电子组件的剖视图。
图1B是对应于图1A的剖视图的平面视图。
图2是根据图1A中所示实施例的变型的微电子组件的剖视图。
图3A是根据一个实施例的微电子组件的剖视图。
图3B是沿横向于图3A中所示实施例中图3A剖视图的剖切线的剖视图。
图3C是图3A-B中所示的实施例的平面视图。
图3D是示出根据一个实施例的、对不同的结合线直径特性阻抗Z0相对于分开高度H的曲线图。
图4A是示出根据图1A-B中所示实施例的变型的微电子组件的剖视图。
图4B是图4A中所示实施例的沿横向于图4A中剖视图的剖切线的剖视图。
图4C是示出根据图4A-B中所示实施例的变型的微电子组件的剖视图。
图4D是的横向于图4C的剖视图的剖视图,示出根据特定的实施例的微电子组件。
图4E是示出根据图4C中所示实施例的变型的微电子组件的剖视图。
图4F是示出图4E中所示实施例的变型的局部剖视图。
图4G是示出根据图4C中所示实施例的变型的微电子组件的剖视图。
图5是示出图3A-C中所示实施例的变型的剖视图。
图6是示出图3A-C中所示实施例的变型的剖视图。
图7是横向于图6中所示截面的剖视图,示出图3A-C中所示实施例的变型。
图8是示出根据图3A-C中所示实施例的变型的微电子组件的剖视图。
图9是示出根据图3A-C中所示实施例的变型的微电子组件的剖视图。
图10是示出根据图3A-C中所示实施例的变型的微电子组件的剖视图。
图11A是根据另一个实施例的微电子组件的剖视图。
图11B是根据一个实施例的、对应于图11A的剖视图的平面视图。
图12是示出根据图11A-B中所示实施例的变型的微电子组件的平面视图。
具体实施方式
图1A显示了根据一个实施例的、示例微电子组件100的剖视图。图1B是从上面看的相应平面视图,其中,图1A中的视图是穿过图1B的剖切线1A-1A。在该示例中,微电子组件100包括通过接合线165导电连接到互连元件130的微电子装置110。微电子组件100与传统布置不同之处在于,该微电子组件100包括导体166,所述导体166由绝缘(介电)涂层168绝缘包覆(sheathed)的导体166。在介电涂层168之外,导电密封材料160覆盖并且至少基本上包围接合线165。这样,导电密封材料160以距离内部导体166至少相对均匀的距离(可以是均匀的距离)设置,这样使导电密封材料可用作包括中心导体166和导电密封材料160的传输线中的参考导体。
微电子装置110可以是单个“裸芯片(bare)”,即未封装管芯,例如其上具有微电子电路的半导体芯片。在可选实施例中,微电子装置110可包括封装半导体管芯。开始时,多个触点112暴露在微电子装置的表面128处。例如,多个触点112可暴露在半导体管芯的触点承载表面处,并且可以暴露在该表面处的一行或多行布置。
为了易于参考,在本公开中阐述了方向参考“顶部”,即半导体芯片110的触点承载表面128。通常,称为“向上”或“从...升高”的方向应指正交和远离芯片顶面128的方向。称为“向下”的方向应指正交于芯片顶面128并且与向上方向相反的方向。“垂直”方向应指正交于芯片顶面的方向。术语在参考点“上方”应指参考点向上的点,术语在参考点“下方”应指参考点以下的点。任何单独的元件的“顶部”应指元件的沿向上方向延伸最远的一个或多个点,术语任何元件的“底部”应指元件的沿向下方向延伸最远的一个或多个点。
如图1A中所示的互连元件130能够通过导电互连与微电子装置连接。例如,互连元件可以是封装元件,所述封装元件具有多个导电引线或迹线(trace)135;多个第一触点175、180,所述多个第一触点175、180连接到所述引线或迹线,通常布置在第一位置处,用于与所述微电子装置互连;和多个第二触点175’,180’,所述多个第二触点175’,180’通常安置在第二位置处,例如用于互连到另一个元件,例如用于外部互连到印刷电路板。可选地,互连元件可以是另一微电子装置或除此之外包括一个或多个这样的装置的单元。互连元件130可包括焊接掩模或其他介电薄膜150,所述焊接掩模或其他介电薄膜150可至少部分覆盖迹线135,同时暴露用于形成导电互连的触点。
在图1A中示出的示例中,触点175、175’可承载信号,即随时间变化并且典型地传递信息的电压或电流。例如,但是无限制地,信号的示例为随时间变化并且代表状态、变化、测量值、时钟或时间输入或控制或反馈输入的电压或电流。另一方面,触点180、180’可提供到地或电源电压的连接。到地或电源电压的连接典型地在电路中提供关于这样的电压的参考,所述电压至少在对电路操作重要的频率范围随时间相当稳定。在微电子装置和互连元件之间形成导电互连之前,触点175、175’、180、180’在互连元件130的、向外指向的面190处暴露。如本公开中所使用,“暴露在”介电结构处的阐述指示、导电结构可获得用于与沿垂直于该介电结构表面方向从介电结构外朝向介电结构表面移动的假设点接触。这样,暴露在介电结构表面处的端子或其他导电结构可从这样的表面突出;可与这样的表面平齐;或可相对于这样的表面凹入以及通过电介质中的孔或凹入部暴露。
在一个特定的实施例中,互连元件可包括“基板”,例如,承载多个迹线和触点的介电元件。无限制地,基板的一个特定示例可以是片状柔性介电元件,典型地除此之外可以由聚合物制成,例如聚酰胺等,其上具有图案化的金属迹线和触点,该触点在介电元件的至少一个面处暴露。在一个实施例中,介电元件可沿延伸远离微电子装置的表面128的方向具有200微米或更小的厚度。
参照图1A-B,具有介电元件120的互连元件130通过接合线165与微电子装置110导电互连。接合线可使用绝缘线形成。使用绝缘线的接合线可具有优于其他类型接合线的优点。例如,如果线必须交叉,则可防止绝缘线短路,并且可对线提供机械保护或增强,这对于其他方式是不可得的。根据一个实施例,现在将参照图1A-B描述用于将绝缘线从微电子装置连接到互连元件的工艺。
接合线165的绝缘涂层168可具有根据线166的尺寸(例如直径)选择的厚度。绝缘涂层的厚度可确定为该涂层沿着从线的中心导电金属芯的外表面远离的正交方向上的尺寸。在特定的实施例中,线的中心金属芯的直径可以是约1密耳(0.001英寸)或更小,该测量值等同于约30微米或更小(此后参考微米,可使用“微米”、“百万分之一米”或“μm”替代说明)。在一个实施例中,绝缘涂层的厚度可选择成具有在约30微米和约75微米之间的厚度,即在约1密耳和3密耳之间的厚度。线166导电地并且机械地连接到互连元件130的触点175,和触点125(例如微电子装置110上的键合焊盘)。与绝缘线165连接的装置触点可以是微电子装置的信号焊盘或地焊盘。接合线可通过将典型地为金或铜的、具有绝缘涂层的金属线结合到微电子装置110上的触点112,然后拉伸该线,并且将其连接到相应的触点或互连元件130的触点175。可选地,该线可首先结合到子组件130的焊盘,之后结合到微电子装置110的触点。
在一个实施例中,接合线165可使用其上具有预制的绝缘层的线,这样的线设置在用于自动线键合机的进料卷轴上。设置在进料到线键合机的线上的绝缘涂层可具有相当小的厚度,例如一微米到几微米的厚度。在该情况下,当结合绝缘线时,处于线尖部的绝缘涂层可以恰在用每个触点形成接头之前用线键合设备燃烧掉。接合线165的绝缘涂层可能在接合线刚开始形成在芯片上时相对较薄。例如,在接合线上可获得的绝缘涂层可具有仅约1微米到几微米的厚度。包覆层的厚度可以是这样的:在将所述尖部连接到装置或者子组件的触点以形成接合线的一端之前而通过线键合工具向接合线的暴露尖部施加热或火焰时很容易地消耗掉该包覆层。
在将接合线连接到装置和子组件的触点之后,可对接合线应用一个步骤来将另一层绝缘层添加到绝缘涂层,这样该涂层增长到所需的厚度。例如,特定的绝缘材料可在液体组合物中的分子具有亲和力,这样当暴露于这样的液体组合物时,分子可选择地聚集在绝缘涂层上,以让绝缘涂层的厚度增加。在一个实施例中,绝缘涂层的厚度可至少为约30微米,以实现绝缘的接合线和将用作用于其的参考导体的导电材料之间的所需的分开距离。该分开距离是与接合线的横截面尺寸(例如直径)一起部分确定接合线结构的阻抗的因素。绝缘涂层的厚度可大于例如50微米、75微米、100微米或其他值,取决于线166的直径、绝缘涂层的磁导率和将获得的阻抗值。
一旦已经形成到微电子装置触点的接合线165,可沉积介电材料珠169、179来覆盖可能仍暴露的微电子装置触点112和互连元件的触点175的任何部分。介电材料的量可限制到仅对保证触点112和触点175完全对后续工艺处理绝缘所必须的量。因此,介电材料可相对薄,即厚度不需要超过几微米。可例如通过旋涂或喷涂工艺或通过填充到一定高度来沉积这样的绝缘介质材料层。在一个实施例(图2)中,可将绝缘介电材料169’、179’沉积在触点112和元件触点175的暴露部分上达到足够将该触点与后续沉积的导电材料绝缘的深度。
在这样的处理之后,可形成导电层160。在一个示例中,导电密封材料可分配到绝缘线165上,以形成导电层160。在一个实施例中,导电层160可将绝缘线165整体密封。在一个实施例中,导电材料可以是导电膏,例如银膏、焊膏等。在可选实施例中,所述导电材料可以是不同的材料。
在一个实施例中,当导电层160形成时,导电层160与互连元件的触点180形成导电互连。例如,互连元件上的触点180可在导电密封材料设置在该结构上时暴露,这样密封材料然后与触点形成导电接触。当触点180为地触点时,导电密封材料160提供用于传输线的地参考,所述传输线通过绝缘接合线165和穿过导电层160的地参考并置形成。
根据上述结构,实现了用于与互连元件130上的信号触点连接的绝缘接合线165的传输线结构。而且,可选择该结构的参数来实现所需的特性阻抗。例如,在一些电子系统中,可选择50欧姆的特性阻抗来满足信号接口要求,例如当外部接口上的信号在具有50欧姆特性阻抗的传输线上传输时。为了实现所选的阻抗,可选择参数,例如金属导电性能以及线的形状和厚度,介电绝缘材料的厚度、其介电常数,即导磁率,以及导电层160(例如导电密封材料)的特性。
可按所述顺序或可选地不同的顺序执行如上所描述的结构。在一些实施方式中,两个或多个所述步骤可合并为一个步骤。在其他实施方式中,所述步骤可完全从该工艺排除。在其他变型中可能需要额外的工艺步骤。在可替代实施方式(未示出)中,可设置至少一个第二微电子装置来代替互连元件130,并且可通过绝缘线导电连接到互连装置110,从而以与上述微电子组件100中相似的方式实现传输线结构。在另一个可选实施方式中,两个互连元件130的触点可与绝缘接合线导电连接,从而以上面所述方式实现传输线结构。例如,两个或更多电路板或两个或更多其他互连部件的触点可以这样的方式互连。
图3A显示了包括多个阻抗控制接合线的典型微电子组件300的剖视图。图3C显示了从上面看的相应平面视图,其中,图3A是穿过图3C的3A-3A线的视图。图3B是穿过图3C的3B-3B线的沿横向于图3A中示出截面的方向的剖视图。微电子组件300包括微电子装置310和互连元件330。微电子装置310在一个实施例中类似于关于图1A-B中所述的微电子装置110。在一个实施例中,互连元件330类似于关于图1A-B中所述的互连元件130。
如图所示,例如半导体管芯的微电子装置310表面328处的触点312使用线365线键合到互连元件330。线365典型地不绝缘。如图3B中所示,典型地多个这样的线365使用传统的线键合技术接合到微电子装置310和互连元件330。在一个实施例中,线365可能与上面所述的绝缘线165不同。在一个实施例中,线365可典型地为用于传统线键合工艺中的线的类型。例如,线365可主要包括铜、金、金-银合金或一些其他金属或金属与一种或多种其他金属和一种或多种其他材料的合金。
接合线可以相对精确的放置和在期望公差范围内形成,这样可实现平行的近距离间隔开的布线,所述布线平行于管芯的表面328行进。如本文所用,“平行“表示在制造公差范围内平行于另一个结构的结构。例如,可使用得自Kulicke和Soffa(此后称为“K&S”)的线键合设备实现精确的接合线。这样,可形成接合线365,所述接合线365在芯片表面的横向方向上是完美的直线或者接近于直线地行进。虽然这样的精度可在形成接合线中实现,但是不意味着需要精确地形成平行且直的接合线,除非如所附权利要求中所阐述。
如图3A-C中所示,在一个实施例中,一旦线365已经线接合到微电子装置310和互连元件330,形成介电层350来覆盖接合线并且使接合线绝缘。在这种情况下,介电层350可以是多种不同材料中的一种,例如为聚合物,如环氧树脂,或另一种介电材料等。在一个实施例中,介电材料350填充互连元件330和微电子组件310之间的全部空隙。
如图3B中所示,接合线365具有沿着进出图3B所打印的纸张的方向上延伸的布线。这样,接合线的布线限定在如图3A-B中所示的方向上延伸的平面377。在一个实施例中,介电材料可通过模制而形成在互连元件330和微电子装置310上,以形成具有远离微电子装置表面328的模制介电区域,并且形成至少基本上为平面的表面。这样的介电层的远离表面可以与接合线365所行进的平面377在垂直方向上分开至少基本上均匀的距离“D”。这样,模制的的介电区域可以这样的方式形成:其远离微电子装置表面328的表面在接合线365长度的至少约50%上平行于接合线365的布线。
此后,在介电层350上形成导电层360。导电层360可以多种方式中的任何一种提供。导电层360可沿并且围绕图3A-B中所示的介电层350的表面延伸,以具有与介电层的上述表面接触的导电表面375。在一个示例中,导电层可通过电镀、溅射或其他方式在介电层表面上沉积金属层形成。在另一个实施例中,导电层360可由导电颗粒填充的热固性树脂形成,所述热固性树脂在成形腔之内、在接合线365之上真空成形至所选择的形状和距离。
在特定的实施例中,导电层通过将导电膏,例如银导电膏、焊膏或其他导电填充膏涂敷到介电层的暴露表面形成,例如通过滴涂(dispensing)、模制、丝网印刷或模板印刷工艺。导电膏的其他示例可包括导电聚合物或与宿主树脂(host resin)合金化的聚合物。在特定的示例中,导电膏可包括导电粉末、有机粘合剂(例如聚羟基苯乙烯衍生物)和热固性树脂。使用导电膏的一个可能的益处在于可以是获得重量可能更轻的成品。如果所述导电膏可以导致消除辅助工艺,则还可能更容易并且更廉价地制造。在一个实施例中,导电层360接触互连元件130上的焊盘370。焊盘可以是地或电源焊盘。通过与触点180接触和形成接合,导电层电连接到互连元件。
在一个实施例中,导电层360沿相对于微电子装置310的表面328水平地取向的方向的尺寸可以小于微电子装置表面328的相应尺寸。如图3A-B中所示,微电子装置的表面328具有沿第一方向延伸的第一尺寸324,并且具有沿横向于第一方向的第二方向延伸的第二尺寸334。第一和第二方向相对于微电子装置表面328水平延伸,即在沿着该表面的方向上。在这样的实施例中,导电层360可具有沿第一方向的尺寸326,所述尺寸326小于微电子装置表面328的相应的第一尺寸324。类似地,导电层360可具有沿第二方向的尺寸336,所述第二尺寸336小于微电子装置表面328的对应第二尺寸334。
在一个实施例中,导电层360可具有这样的表面375,所述表面375以大体均匀的距离设置在接合线的长度的至少大部分的上方,这样结合到参考电压源的每一个接合线和相邻的导电层形成具有所需特性阻抗的传输线结构。在一个实施例中,导电表面可以距离接合线长度的50%或更多之上延伸的接合线的布线以这样的基本上均匀的距离设置。为了实现所需的特性阻抗,可选择参数,例如用于线中的金属的导电性能,以及线的形状和厚度,线和导电层360之间的绝缘材料350的厚度,绝缘材料的介电常数,即导磁率,以及导电层360的厚度和性能。
图3D图示了以欧姆为单位的特性阻抗Z0相对以英寸为单位的信号导体(例如圆柱形横截面的电线)和参考导体(例如“地平面”)之间的分开距离。参考导体假设为平面结构,所述平面结构与信号导体的直径相比很大。图3D绘出两根不同直径的线的特性阻抗。图3D中的曲线可从决定现有几何形状的布置中的特性阻抗的公式获得。在这样的公式中,特性阻抗Z0由以下方程给出:
Figure BDA0000107913520000131
其中H为该线和导电平面之间的分开距离,d为线的直径,εR为将该线与导电平面分开的介电材料的磁导率。该分开距离H是可以至少由通过用于制造微电子组件的工艺所确定的因素。所述线直径可以通过用于制造微电子组件的工艺至少部分确定。
在图3D中,下部曲线320绘出当用于形成接合线的线具有1密耳、即0.001英寸厚度时的特性阻抗。上部曲线322绘出用于形成接合线的电线的厚度为0.7密耳,即0.0007英寸时的特性阻抗。如图3D中所示,当电线和导电平面之间的分开距离H小于或等于约0.002英寸(2密耳)、即约50微米时,得到低于约70欧姆的特性阻抗。图3B显示了微电子组件300的横截面。该图显示出,多个接合线可从互连元件330接合到微电子装置310,并且在组件300中因而形成的接合线中的每一个由介电材料350包围。如图所示的导电绝缘材料可覆盖整个子组件。在可选的实施例中,导电绝缘材料可仅覆盖介电材料350的一部分,例如介电材料350的顶部表面。
图4A-4B显示了代表图3中所示组件300的变型的可选组件400。图4A是正视图,图4B是沿横向于图4A中示出的视图的方向的相应剖视图。如图所示,两根线465和466线键合在互连元件430和微电子装置410的各对触点之间。在一个实施例中,线465是信号线(例如,用于在互连元件430和微电子装置410之间传输信号),另一个线466是地线或电源线,即,接合到互连元件430的地或电源触点的线。
在一个实施例中,参考接合线466形成为使参考接合线466延伸到在微电子装置410的触点承载表面428上方的比线465更高的位置。相应地,当介电材料450设置在电线465和466上方时,线466没有由介电材料450完全覆盖。结果,电线466在形成导电层460时保持至少部分暴露。然后,当形成导电层460时,导电层460接触电线466,并且形成与该线的导电连接。线466可连接到微电子装置和互连元件上的各的参考触点(例如地触点或电源触点)。如图4A中进一步所示,导电层连接到互连元件的参考触点480(例如,地或电源触点焊盘)。这样,导电层可用作用于传输线的参考导体,所述传送线包括信号线465和参考线466,并且可还包括作为传输线的一部分的导电层460。由于参考线466也连接到微电子装置410上的触点,因此由信号和参考线465、466形成的传输线延伸到微电子装置上的触点。
图4C是示出图4A-B中所示的实施例的变型的剖视图。如图4C中所示,如在上面讨论的图4A-B中,参考线476延伸到微电子装置的表面428上方比信号线475更高的位置。也如图4C中所示,导电层462,类似于图4A-B的导电层460,具有与绝缘介电层450接触的至少大体为平面的表面464。导电层462另外具有接触部478,所述接触部478向下远离表面464朝向微电子装置410延伸。这样的接触部478具有与参考线466的导电连接,但是与信号线475绝缘。
具有如图4C中所示的接触部478的导电层462可按照以下步骤形成。形成信号线和参考线,并且可在其上形成介电密封材料层450,所述介电密封材料层450具有至少足够的硬度来抵抗在后续工艺处理中的流动。然后形成从暴露参考线476的介电密封材料的外表面向下延伸的沟槽。例如,可使用机械或激光工艺来从密封材料层去除材料。随后,当形成导电层462时,导电材料向下延伸到沟槽中,并且在导电层462和参考线466之间形成导电连接。
图4D示出相对于图4C描述的实施例的变型。图4D是沿对应于图4C的方向线4D-4D的方向截取的剖视图,这样信号线485和参考线486显示为进出沿图4D被打印的纸张平面的方向上行进。在图4D中所示的变型中,参考线486的布线基本上位于与信号线485的布线相同的平面中。接触部488以从至少导电层的大体为平面的表面464向下朝向微电子装置410延伸的沟槽设置,这样参考线设置成与接触部的导电材料接触,而信号线485设置成与介电密封材料450接触。
图4E示出该实施例(图4D)的变型,其中,参考线496和信号线495具有至少基本上设置在微电子装置410的表面428上方的相同平面中的布线,但是其中,参考线496沿与信号线延伸的方向495相反的方向延伸。参考线496和导电层460之间的触点可用于沿参考线496的长度并且在导电层的表面464上建立稳定的参考电压。结果,参考线496对从微电子装置410在向上的方向上延伸的信号线495的部分491用作用于信号线的参考导体。另一方面,导电层460用作用于信号线的、在沿着微电子装置的表面428的方向并且至少大体延伸到导电层460的表面464的其他部分的参考导体。
在图4F中所示的变型中,参考线496’可包括向上延伸部497或弯折部(kinked portion),而不是仅沿通常平行于微电子装置410的表面428的方向延伸。这样的形状可有助于确保在参考线496’和导电层的连接部498之间简历良好的导电连接。
在图4G中所示的变型中,参考线508在每一端具有到基板或互连元件的导电连接部。该变型的其他结构如上面参照图4A-F中的一个或多个所述。
图5示出微电子组件300的可选实施例。这里,微电子组件500包括微电子装置510和互连元件530。在该实施例中,介电材料550包括凹槽570。该凹槽可在形成介电层550时成形到该组件中。可选地,凹槽570在电介质已经固化之后切割掉。凹槽570可通过钻、锯或一些其他技术切割。在该实施例中,当形成导电层560时,导电层延伸到凹槽570中。然后,导电层可以包括在凹槽中与接合线的升高部分相邻设置、即与沿垂直方向远离微电子装置表面升高的多个导线的部分相邻设置的导电材料,如图5中所示。
图6示出互连元件300的另一可选实施例。这里,导电层660延伸以覆盖在互连元件630上的迹线635的上面,迹线635由例如诸如焊接掩模的图案化介电层的介电层670与其绝缘。这样将阻抗控制和屏蔽延伸到迹线。
图7示出根据另一可选实施例的微电子组件700。这里,介电层750包括从其顶面向下延伸的槽或凹槽770。凹槽可沿平行于接合线765的布线的方向,即沿由图7打印其上的纸页限定的平面的进出方向延伸。可在例如形成介电层时,例如在分配介电材料时形成所述凹槽。可选地,所述凹槽可在介电材料已经分配或固化之后形成。当形成导电层760时,导电层760可延伸到凹槽770中,并且可在线之间提供屏蔽。
图8示出根据另一个可选实施例的微电子组件800。这里,微电子装置810沿面向上方向与互连元件830线键合。这里,微电子装置的后面连接到互连元件,并且接合线从微电子装置上的触点815延伸到互连元件的相应触点875,所述子组件触点875设置成超出微电子装置的边缘812。
在一个实施例中,一叠微电子装置810可一个叠置在另一个的顶部上。接合线可形成在微电子装置810和相应的互连元件830之间。然后,可形成介电层850,并且然后可形成导电层860。这样的层可成形为堆叠的互连端点,例如暴露在互连元件830上的堆叠触点(未示出)。然后,第二个完成的微电子组件800可堆叠在第二介电层的顶部上,例如这样每个组件800中的微电子装置处于面向上方向。第二微电子组件可与第一微电子组件通过在堆叠的互连端点之间延伸的导电元件导电互连。
图9示出上述实施例(图3A-B)的变型,其中,信号线1065以沿微电子装置1010的表面1028的布线延伸,其中,布线1067不与表面1028的平面平行。相反,接合线的布线1067相对于表面1028成角度倾斜。在该情况下,导电层1060可以间距1061平行于布线1067延伸,间距1061沿接合线的长度的50%或更多均匀或至少基本上均匀。以该方式,实现具有有益的特性阻抗的传输线结构。该制造方法可以与关于上面图3A-B所述的方法相同,不同之处在于,在形成导电层之前,具有人字形状的模具可用于模制介电密封材料层1050。
图10示出另一个变型,其中,接合线1085不以均匀的线性布线延伸。相反,接合线具有台阶形状,所述台阶形状包括大部分向下延伸的相对较短的凸出部1082,和沿横跨微电子装置1010的表面1028的方向延伸的较长一些的凸出部或台阶1084。同样,在该情况下,导电层可布置成具有与接合线1084相邻的台阶状内表面,这样的内表面由顺应接合线外形的一系列相似的台阶限定。结果,导电层1080的内表面可平行于接合线的突出部1084以间距1081平行于接合线的凸出部1084,间距1081沿接合线长度的50%或更多是均匀的或至少基本上是均匀的。再次地,可使用上面描述的相同的方法(图3A-B)来制造该结构,不同之处在于,可使用具有不同形状的模具来形成台阶状导电层。
在图11A-11B中示出的实施例中,导电平面960沿微电子装置910的表面928延伸,并且连接到微电子装置的触点912的接合线965以与导电平面960分开的距离平行于表面928延伸。图11A是示出包括微电子装置910和与该微电子装置910连接的互连元件的微电子组件900。图11B是从表面928上面并且朝向面朝触点912的表面看的平面视图。如图11A-B中所示,导电平面可包括开口964,开口964暴露触点912中的各触点。可选地,导电平面可包括一个或多个更大的开口,所述开口暴露微电子装置的触点中的一些或全部。
在一个实施例中,导电平面可在装置处于包括多个相连装置的晶圆或面板形式时或在该装置已经从其他这样的装置分开之后,通过应用到微电子装置的表面928的工艺处理,例如应用到该装置的金属沉积或电镀工艺形成。可选地,导电平面可通过预处理例如铜箔的金属片来提供,以在金属薄片中形成开口964。然后,金属薄片可例如通过使用粘合剂结合到微电子装置的表面928。
然后形成接合线965,所述接合线965连接微电子装置的触点912和微电子装置910上的触点975。如图11A中所示,接合线965具有升高到微电子装置的表面928上方的布线。在形成接合线之后,可形成介电层950,例如用于机械地支撑接合线。接合线965的布线可沿水平方向平行于或至少大体平行于微电子装置表面928延伸,如图11A中所示。在该情况下,布线在其制造公差内是平行的。这样的水平布线通常为接合线的大部分,即接合线的长度的50%或更大。布线可以在导电平面上方间隔开基本上均匀的高度,例如典型地以距离表面928约50微米的高度到距离表面928约100微米的高度。以该方式,可对接合线实现所需的阻抗。以该方式,到并且来自微电子装置的信号可以进入承载该信号的连接(例如接合线)更小的噪音来传输。
图12中所示的变型说明导电层不必是完整的金属薄片。相反,如图12中所示,导电层可以多个导电带980的形式设置,所述多个导电带980沿微电子装置910的表面以平行于装置触点912和微电子元件930的触点975之间的信号接合线965的布线的方向延伸。导电带可通过支撑部982机械支撑或保持在一起。在一个实施例中,导电带和支撑部通过以去除方式图案化铜箔或薄片的金属结构,并且例如通过粘合材料962将剩余金属结构粘合到微电子装置的表面928形成。
已经相对于单独的微电子装置(例如半导体芯片)的互连描述了前面的实施例。但是,应可理解,本文所述的方法可用于晶圆级制造方法中,所述晶圆级制造方法同时应用到在芯片边缘处连接在一起的多个芯片,例如以单元、面板、晶圆或晶圆的一部分的形式在边缘处连接在一起的多个芯片。
在上述实施例的特定变型中,导电材料不必顺应围绕接合线的介电区域的形状。例如,代替在模制的介电区域上形成导电层,而是可通过连接金属罐(metal can)来覆盖在接合线和介电区域350的上面来实现,以将金属罐的内表面以距离微电子组件的接合线365的所需的间距放置金属罐的内表面。
虽然上面的描述参考了用于特定应用的示例性实施例中,但是应可理解,要求保护的本发明不限于此。本领域的和获知本文提供技术的普通技术人员将意识到在所附权利要求范围内的另外的修改形式、应用和实施例。

Claims (31)

1.一种微电子组件,包括:
微电子装置,所述微电子装置具有表面和在所述表面处暴露的装置触点,所述表面具有沿第一方向的第一尺寸和沿横向于所述第一方向的第二方向的第二尺寸;
互连元件,所述互连元件具有与所述微电子装置相邻的面,并且具有多个元件触点;
多个导电元件,所述多个导电元件连接所述装置触点和所述元件触点,所述导电元件具有主要部分,所述主要部分以在所述微电子装置的表面上方的布线延伸;和
导电材料,所述导电材料具有以至少基本上均匀的距离布置在所述多个布线的至少上方或下方至少之一处的导电表面,所述导电材料具有沿所述第一方向的第一尺寸,和沿所述第二方向的第二尺寸,其中,所述导电材料的第一和第二尺寸中的每一个小于所述微电子装置的第一尺寸和第二尺寸,
其中,所述导电材料可连接到参考电势源,这样对所述导电元件实现所需的阻抗。
2.一种微电子组件,包括:
微电子装置,所述微电子装置具有表面和在所述表面处暴露的装置触点;
互连元件,所述互连元件具有与所述微电子装置相邻的表面,并且具有多个元件触点;
多个导电元件,所述多个导电元件连接所述装置触点和所述元件触点,所述导电元件具有在所述微电子装置表面上方延伸的布线;和
导电材料,所述导电材料具有导电表面,所述导电表面以距离所述导电元件的长度的至少主要部分基本上均匀的距离布置在所述导电元件上方或所述导电元件下方的方向中的至少一个,所述导电材料可连接到参考电势源,这样对所述导电元件实现所需的阻抗,所述导电表面限定至少基本上平行于所述导电元件在其中行进的平面。
3.根据权利要求1或2所述的微电子组件,其中,所述导电平面覆盖在所述导电元件的多个布线上面。
4.根据权利要求3所述的微电子组件,其中,所述导电表面至少大体为平面。
5.根据权利要求4所述的微电子组件,其中,所述导电表面相对于所述微电子装置的表面成角度倾斜。
6.根据权利要求1或2所述的微电子组件,其中,所述多个布线包括接合线的至少部分。
7.根据权利要求1或2所述的微电子组件,其中,所述导电元件为接合线。
8.根据权利要求7所述的微电子组件,其中,所述接合线以多个连接的台阶延伸,其中,所述导电表面至少基本上平行于所述接合线的多个台阶而以台阶形式延伸。
9.根据权利要求1或2所述的微电子组件,其中,所述互连元件包括介电元件。
10.根据权利要求1或2所述的微电子组件,其中,所述互连元件包括可连接到所述参考电势源的参考触点,其中,所述导电材料可与所述参考触点导电连接。
11.根据权利要求9所述的微电子组件,其中,所述介电元件包括聚合物元件,所述聚合物元件具有在沿远离所述微电子元件表面的方向小于200微米的厚度。
12.根据权利要求11所述的微电子组件,其中,所述聚合物元件为片状。
13.根据权利要求1或2所述的微电子组件,其中,所述导电元件以冶金方式键合到所述装置触点。
14.根据权利要求6所述的微电子组件,其中,所述导电表面通过绝缘材料与所述接合线的多个布线分开。
15.根据权利要求14所述的微电子组件,其中,所述绝缘材料至少基本上填充空间,并且所述接合线的多个布线延伸通过所述空间。
16.根据权利要求14所述的微电子组件,其中,所述导电材料结合到在所述互连元件表面处暴露的参考触点,所述导电材料与所述互连元件的表面相顺应,并且所述互连元件包括用于将所述参考触点连接到参考电势源的导体。
17.根据权利要求16所述的微电子组件,还包括参考导电元件,所述参考导电元件具有在沿着所述微电子装置的表面的方向上延伸的布线,其中,所述导电材料结合到所述参考导电元件的布线。
18.根据权利要求16所述的微电子组件,其中,所述导电材料具有至少大体平面的导电表面,所述绝缘材料将所述导电平面与所述导电元件以至少基本上均匀的距离分开,并且所述导电材料包括在所述至少大体平面的导电表面下方设置的连接部,其中,所述连接部具有至所述参考导电元件的机械和电导电连接。
19.根据权利要求16所述的微电子组件,其中,所述参考导电元件的布线位于至少基本上与所述导电元件的多个布线相同的平面中。
20.根据权利要求16所述的微电子组件,其中,所述绝缘材料具有外表面和沿所述外表面向内延伸的多个凹槽,所述导电材料设置在所述凹槽中。
21.根据权利要求20所述的微电子组件,其中,所述凹槽包括与连接到所述装置触点的所述接合线的升高部分相邻设置的凹槽。
22.根据权利要求20所述的微电子组件,其中,所述接合线包括沿着所述微电子装置的主表面在第一方向上延伸的部分,其中,所述凹槽包括在所述侧向延伸的接合线部分之间沿所述第一方向延伸的凹槽。
23.根据权利要求1或2所述的微电子组件,其中,所述导电材料的边缘与所述互连元件的边缘相邻设置。
24.根据权利要求1或2所述的微电子组件,其中,所述装置触点在所述微电子装置的前表面处暴露,所述微电子装置具有远离所述前表面的后表面和在所述前表面和后表面之间延伸的边缘,所述后表面安装到所述互连元件,这样所述导电元件延伸超出所述微电子装置的边缘。
25.一种微电子组件,包括:
微电子装置,所述微电子装置具有前表面和远离所述前表面的后表面,沿着所述前表面延伸的一个或多个表面导电元件,和在所述前表面处暴露的装置触点;
互连元件,所述互连元件包括在所述微电子装置的后表面下面的介电元件,所述互连元件在其上具有多个元件触点;
多个升高的导电元件,所述多个升高的导电元件连接所述装置触点和所述元件触点,所述升高的导电元件具有与所述一个或多个表面导电元件距离第一高度且至少大体平行于所述一个或多个表面导电元件的布线延伸的主要部分,
其中,所述一个或多个表面导电元件可连接到参考电势源,这样对所述升高导电元件实现所需的阻抗。
26.根据权利要求25所述的微电子组件,其中,所述一个或多个表面导电元件包括接合到所述微电子装置的前表面的金属层。
27.根据权利要求26所述的微电子组件,其中,粘合剂将所述一个或多个表面导电元件接合到所述微电子装置的前表面。
28.根据权利要求26所述的微电子组件,其中,所述金属层包括开口,其中,所述表面导电元件通过所述金属层中的开口连接到所述装置触点。
29.一种微电子组件,包括:
微电子装置,所述微电子装置具有表面和在所述表面处暴露的装置触点;
互连元件,所述互连元件具有与所述微电子装置相邻的面,并且具有多个元件触点;
多个接合线,所述多个接合线连接所述装置触点和所述元件触点;
绝缘材料,所述绝缘材料包覆所述接合线中的每一个,所述绝缘材料具有大于约30微米的厚度,所述厚度沿所述导电元件的大部分长度是至少基本上均匀的;和
导电材料,所述导电材料与所述绝缘材料的外表面相顺应,并且填充所述绝缘包覆的接合线之间的空间,所述导电材料可连接到参考电势源,以对所述导电元件实现所需的阻抗。
30.根据权利要求29所述的微电子组件,还包括:将至少所述装置触点与所述导电材料分开的绝缘体。
31.根据权利要求30所述的微电子组件,其中,所述绝缘体为第一绝缘体,所述组件还包括将至少所述元件触点与所述导电材料分开的第二绝缘体。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022909A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 在电子芯片与载体衬底之间形成电连接的方法和电子器件
CN108022910A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 用于在电子芯片与载体衬底之间形成电连接的方法以及电子器件
US11557566B2 (en) 2016-11-03 2023-01-17 Stmicroelectronics (Grenoble 2) Sas Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100950511B1 (ko) * 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
KR100935854B1 (ko) * 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
US8222725B2 (en) 2010-09-16 2012-07-17 Tessera, Inc. Metal can impedance control structure
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control
US9136197B2 (en) 2010-09-16 2015-09-15 Tessera, Inc. Impedence controlled packages with metal sheet or 2-layer RDL
WO2012071325A1 (en) 2010-11-24 2012-05-31 Tessera, Inc. Lead structures with vertical offsets
KR101118711B1 (ko) 2010-12-17 2012-03-12 테세라, 인코포레이티드 중앙 콘택을 구비한 적층형 마이크로전자 조립체
KR101061531B1 (ko) * 2010-12-17 2011-09-01 테세라 리써치 엘엘씨 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체
FR2980101A1 (fr) 2011-09-20 2013-03-22 Tornier Inc Bande de renfort pour la restauration d'un tissu mou
US9548599B2 (en) * 2013-08-27 2017-01-17 Labinal, Llc Thermally managed load module with embedded conductors
KR20190057136A (ko) * 2016-10-04 2019-05-27 더 차레스 스타크 드레이퍼 래보레이토리, 인코포레이티드 와이어링 시스템
TWI780576B (zh) * 2020-12-28 2022-10-11 抱樸科技股份有限公司 具有包覆層之導線的半導體元件及其製作方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268100A (ja) * 1993-03-12 1994-09-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の封止構造および封止方法
JP2001339016A (ja) * 2000-05-30 2001-12-07 Alps Electric Co Ltd 面実装型電子回路ユニット
US20030090001A1 (en) * 2001-11-13 2003-05-15 Kulicke And Soffa Investments, Inc. Wirebonded semiconductor package structure and method of manufacture
US6812580B1 (en) * 2003-06-09 2004-11-02 Freescale Semiconductor, Inc. Semiconductor package having optimized wire bond positioning
US20050116013A1 (en) * 2003-11-28 2005-06-02 International Business Machines Corporation Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers
US20060049505A1 (en) * 2002-12-10 2006-03-09 Koninklijke Philips Electronics N.V. High density interconnect power and ground strap and method therefor
US20060180916A1 (en) * 2003-07-30 2006-08-17 Koninklijke Philips Electronics N.V. Ground arch for wirebond ball grid arrays
US20070170601A1 (en) * 2003-12-26 2007-07-26 Yoshinori Miyaki Semiconductor device and manufacturing method of them

Family Cites Families (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680613A (en) * 1983-12-01 1987-07-14 Fairchild Semiconductor Corporation Low impedance package for integrated circuit die
US5065282A (en) 1986-10-17 1991-11-12 Polonio John D Interconnection mechanisms for electronic components
US5028983A (en) 1988-10-28 1991-07-02 International Business Machines Corporation Multilevel integrated circuit packaging structures
US4980753A (en) * 1988-11-21 1990-12-25 Honeywell Inc. Low-cost high-performance semiconductor chip package
US5471151A (en) 1990-02-14 1995-11-28 Particle Interconnect, Inc. Electrical interconnect using particle enhanced joining of metal surfaces
JPH04284661A (ja) * 1991-03-13 1992-10-09 Toshiba Corp 半導体装置
JPH0653277A (ja) 1992-06-04 1994-02-25 Lsi Logic Corp 半導体装置アセンブリおよびその組立方法
US5880403A (en) * 1994-04-01 1999-03-09 Space Electronics, Inc. Radiation shielding of three dimensional multi-chip modules
JPH0758138A (ja) * 1993-08-16 1995-03-03 Nec Corp ワイヤボンディング構造およびそのボンディング方法
US6326678B1 (en) * 1993-09-03 2001-12-04 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US6552417B2 (en) * 1993-09-03 2003-04-22 Asat, Limited Molded plastic package with heat sink and enhanced electrical performance
US5343074A (en) * 1993-10-04 1994-08-30 Motorola, Inc. Semiconductor device having voltage distribution ring(s) and method for making the same
US5639989A (en) * 1994-04-19 1997-06-17 Motorola Inc. Shielded electronic component assembly and method for making the same
JP3034180B2 (ja) 1994-04-28 2000-04-17 富士通株式会社 半導体装置及びその製造方法及び基板
JP2938344B2 (ja) * 1994-05-15 1999-08-23 株式会社東芝 半導体装置
US5468999A (en) * 1994-05-26 1995-11-21 Motorola, Inc. Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding
JPH0927512A (ja) * 1995-07-10 1997-01-28 Mitsubishi Electric Corp 半導体装置
KR0156334B1 (ko) 1995-10-14 1998-10-15 김광호 차폐 본딩 와이어를 구비하는 고주파, 고밀도용 반도체 칩 패키지
US7166495B2 (en) 1996-02-20 2007-01-23 Micron Technology, Inc. Method of fabricating a multi-die semiconductor package assembly
JPH09260568A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6001671A (en) * 1996-04-18 1999-12-14 Tessera, Inc. Methods for manufacturing a semiconductor package having a sacrificial layer
KR100270817B1 (ko) 1997-05-22 2000-11-01 이해영 초고주파소자 실장 패키지 및 그 패키지에 사용되는 본딩와이어의 기생효과 감소방법
TW473882B (en) 1998-07-06 2002-01-21 Hitachi Ltd Semiconductor device
JP3946874B2 (ja) 1998-07-06 2007-07-18 株式会社ルネサステクノロジ 半導体装置
JP3662461B2 (ja) * 1999-02-17 2005-06-22 シャープ株式会社 半導体装置、およびその製造方法
JP3483132B2 (ja) 1999-04-23 2004-01-06 シャープ株式会社 高周波半導体装置
JP2000332160A (ja) 1999-05-24 2000-11-30 Sumitomo Metal Electronics Devices Inc キャビティダウン型半導体パッケージ
US6822635B2 (en) 2000-01-19 2004-11-23 Immersion Corporation Haptic interface for laptop computers and other portable devices
JP2001223324A (ja) * 2000-02-10 2001-08-17 Mitsubishi Electric Corp 半導体装置
US6518659B1 (en) * 2000-05-08 2003-02-11 Amkor Technology, Inc. Stackable package having a cavity and a lid for an electronic device
US6538336B1 (en) * 2000-11-14 2003-03-25 Rambus Inc. Wirebond assembly for high-speed integrated circuits
US7161239B2 (en) 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US6770963B1 (en) 2001-01-04 2004-08-03 Broadcom Corporation Multi-power ring chip scale package for system level integration
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
TW510034B (en) * 2001-11-15 2002-11-11 Siliconware Precision Industries Co Ltd Ball grid array semiconductor package
US6770822B2 (en) 2002-02-22 2004-08-03 Bridgewave Communications, Inc. High frequency device packages and methods
JP2004079886A (ja) * 2002-08-21 2004-03-11 Toshiba Corp 実装体の製造方法、半導体装置及び実装体
JP2004112143A (ja) 2002-09-17 2004-04-08 Sumitomo Metal Electronics Devices Inc 高周波信号用導体の接続構造、および半導体集積回路パッケージ
EP1573814A1 (en) 2002-12-10 2005-09-14 Koninklijke Philips Electronics N.V. High density package interconnect wire bond strip line and method therefor
TWI226689B (en) * 2003-02-25 2005-01-11 Via Tech Inc Chip package and process for forming the same
JP4106039B2 (ja) * 2003-06-27 2008-06-25 株式会社新川 ワイヤボンディング方法
JP2005026263A (ja) 2003-06-30 2005-01-27 Nec Compound Semiconductor Devices Ltd 混成集積回路
DE10339770B4 (de) * 2003-08-27 2007-08-30 Infineon Technologies Ag Verfahren zum Herstellen einer FBGA-Anordnung
US7071421B2 (en) 2003-08-29 2006-07-04 Micron Technology, Inc. Stacked microfeature devices and associated methods
US7466021B2 (en) * 2003-11-17 2008-12-16 Interconnect Portfolio, Llp Memory packages having stair step interconnection layers
US7205651B2 (en) 2004-04-16 2007-04-17 St Assembly Test Services Ltd. Thermally enhanced stacked die package and fabrication method
KR100640580B1 (ko) * 2004-06-08 2006-10-31 삼성전자주식회사 측면이 봉지재로 감싸진 반도체 패키지 및 그 제조방법
US7151309B2 (en) * 2004-08-27 2006-12-19 Texas Instruments Incorporated Apparatus for improved power distribution in wirebond semiconductor packages
TWI393228B (zh) 2004-12-14 2013-04-11 Freescale Semiconductor Inc 覆晶及焊線封裝半導體
TWM269568U (en) * 2004-12-16 2005-07-01 Domintech Co Ltd Chip package capable of reducing characteristic resistance
US7566952B2 (en) 2005-01-05 2009-07-28 International Business Machines Corporation On-chip circuit pad structure
DE102005002707B4 (de) * 2005-01-19 2007-07-26 Infineon Technologies Ag Verfahren zur Herstellung elektrischer Verbindungen in einem Halbleiterbauteil mittels koaxialer Mikroverbindungselemente
JP4428248B2 (ja) * 2005-02-04 2010-03-10 エルピーダメモリ株式会社 半導体装置の製造方法
US20060175712A1 (en) 2005-02-10 2006-08-10 Microbonds, Inc. High performance IC package and method
KR100702970B1 (ko) 2005-07-06 2007-04-03 삼성전자주식회사 이원 접속 방식을 가지는 반도체 패키지 및 그 제조 방법
US7456505B2 (en) * 2005-07-29 2008-11-25 Infineon Technologies Ag Integrated circuit chip and integrated device
SG130061A1 (en) * 2005-08-24 2007-03-20 Micron Technology Inc Microelectronic devices and microelectronic support devices, and associated assemblies and methods
US8026129B2 (en) 2006-03-10 2011-09-27 Stats Chippac Ltd. Stacked integrated circuits package system with passive components
CN101410974B (zh) 2006-03-23 2013-02-20 台湾积体电路制造股份有限公司 增强型电子键合引线封装
US20080014678A1 (en) * 2006-07-14 2008-01-17 Texas Instruments Incorporated System and method of attenuating electromagnetic interference with a grounded top film
US7777353B2 (en) * 2006-08-15 2010-08-17 Yamaha Corporation Semiconductor device and wire bonding method therefor
DE102006042775B3 (de) 2006-09-12 2008-03-27 Qimonda Ag Schaltungsmodul und Verfahren zur Herstellung eines Schaltungsmoduls
US7537962B2 (en) * 2006-12-22 2009-05-26 Stats Chippac Ltd. Method of fabricating a shielded stacked integrated circuit package system
US7875985B2 (en) 2006-12-22 2011-01-25 Qimonda Ag Memory device
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7843021B2 (en) 2008-02-28 2010-11-30 Shandong Gettop Acoustic Co. Ltd. Double-side mountable MEMS package
US8159052B2 (en) * 2008-04-10 2012-04-17 Semtech Corporation Apparatus and method for a chip assembly including a frequency extending device
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US8294249B2 (en) * 2008-08-05 2012-10-23 Integrated Device Technology Inc. Lead frame package
US20100044850A1 (en) 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
KR101257737B1 (ko) 2008-08-22 2013-04-25 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 메타 물질을 사용하는 임피던스 제어 전기 상호접속
JP2010192680A (ja) 2009-02-18 2010-09-02 Elpida Memory Inc 半導体装置
KR100950511B1 (ko) * 2009-09-22 2010-03-30 테세라 리써치 엘엘씨 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리
KR100935854B1 (ko) 2009-09-22 2010-01-08 테세라 리써치 엘엘씨 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리
JP5590814B2 (ja) 2009-03-30 2014-09-17 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US8916958B2 (en) * 2009-04-24 2014-12-23 Infineon Technologies Ag Semiconductor package with multiple chips and substrate in metal cap
US8786083B2 (en) 2010-09-16 2014-07-22 Tessera, Inc. Impedance controlled packages with metal sheet or 2-layer RDL
US8222725B2 (en) 2010-09-16 2012-07-17 Tessera, Inc. Metal can impedance control structure
US8853708B2 (en) 2010-09-16 2014-10-07 Tessera, Inc. Stacked multi-die packages with impedance control
US8581377B2 (en) 2010-09-16 2013-11-12 Tessera, Inc. TSOP with impedance control

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06268100A (ja) * 1993-03-12 1994-09-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置の封止構造および封止方法
JP2001339016A (ja) * 2000-05-30 2001-12-07 Alps Electric Co Ltd 面実装型電子回路ユニット
US20030090001A1 (en) * 2001-11-13 2003-05-15 Kulicke And Soffa Investments, Inc. Wirebonded semiconductor package structure and method of manufacture
US20060049505A1 (en) * 2002-12-10 2006-03-09 Koninklijke Philips Electronics N.V. High density interconnect power and ground strap and method therefor
US6812580B1 (en) * 2003-06-09 2004-11-02 Freescale Semiconductor, Inc. Semiconductor package having optimized wire bond positioning
US20060180916A1 (en) * 2003-07-30 2006-08-17 Koninklijke Philips Electronics N.V. Ground arch for wirebond ball grid arrays
US20050116013A1 (en) * 2003-11-28 2005-06-02 International Business Machines Corporation Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers
US20070170601A1 (en) * 2003-12-26 2007-07-26 Yoshinori Miyaki Semiconductor device and manufacturing method of them

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108022909A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 在电子芯片与载体衬底之间形成电连接的方法和电子器件
CN108022910A (zh) * 2016-11-03 2018-05-11 意法半导体(格勒诺布尔2)公司 用于在电子芯片与载体衬底之间形成电连接的方法以及电子器件
US11557566B2 (en) 2016-11-03 2023-01-17 Stmicroelectronics (Grenoble 2) Sas Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device

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TWI431748B (zh) 2014-03-21
KR100950511B1 (ko) 2010-03-30

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