JP2012520573A - インピーダンス制御されたワイヤ・ボンド及び導電性基準部品を有するマイクロ電子アセンブリ - Google Patents
インピーダンス制御されたワイヤ・ボンド及び導電性基準部品を有するマイクロ電子アセンブリ Download PDFInfo
- Publication number
- JP2012520573A JP2012520573A JP2011554234A JP2011554234A JP2012520573A JP 2012520573 A JP2012520573 A JP 2012520573A JP 2011554234 A JP2011554234 A JP 2011554234A JP 2011554234 A JP2011554234 A JP 2011554234A JP 2012520573 A JP2012520573 A JP 2012520573A
- Authority
- JP
- Japan
- Prior art keywords
- conductive
- component
- microelectronic
- microelectronic assembly
- microelectronic device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6611—Wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0613—Square or rectangular array
- H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
- H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45139—Silver (Ag) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/4556—Disposition, e.g. coating on a part of the core
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45565—Single coating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/4554—Coating
- H01L2224/45599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
- H01L2224/49052—Different loop heights
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/4909—Loop shape arrangement
- H01L2224/49095—Loop shape arrangement parallel in plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
- H01L2224/49176—Wire connectors having the same loop shape and height
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85009—Pre-treatment of the connector or the bonding area
- H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
- H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
- H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
【選択図】図3A
Description
本願は、2009年9月22日に出願された韓国特許出願第10−2009−0089470号の優先権を主張すると共に、2009年3月13日に出願された米国仮特許出願第61/210,063号の利点を請求する。これらの特許の開示内容は、参照することによって本願に組み込まれるものとする。
図1Aは、1つの実施形態に基づいて、マイクロ電子アセンブリ100の実施例の断面図を示している。図1Bは上から見た対応する平面図であり、図1Aは図1Bの断面線1A−1Aにおける図である。この実施例では、マイクロ電子アセンブリ100はワイヤ・ボンド165を通して相互接続部品130に導電接続されるマイクロ電子デバイス110を備えている。このマイクロ電子アセンブリ100は、絶縁(誘電体)コーティング168によって絶縁被覆されている導体166を有していることで、従来の構成とは異なっている。誘電体コーティング168を越えて、導電性カプセル材料160がワイヤ・ボンド165を被覆しかつ少なくとも実質的に取り囲む。このため、導電性カプセル材料160が、内部導体166から少なくとも比較的均一な距離(均一な距離とすることができる)に配置され、導電性カプセル材料が中央導体166及び導電性カプセル材料160を含む伝送線路の中で基準導体として動作することができる。
312:デバイス接点
340:部品接点
360:導電層
365:導電性部品
375:導電面
Claims (31)
- 表面と該表面において露出したデバイス接点とを有するマイクロ電子デバイスであって、 前記表面は、第1の方向における第1の寸法と、該第1の方向を横切る第2の方向における第2の寸法とを有する、マイクロ電子デバイスと、
前記マイクロ電子デバイスに隣接した面と、複数の部品接点と、を有する相互接続部品と、
前記デバイス接点を前記部品接点に接続し、前記マイクロ電子デバイスの表面上の配線にて延長するかなりの部分を有する複数の導電性部品と、
複数の配線の上又は下の少なくとも一方において、少なくとも実質的に均一な距離で配置された導電面を有する導電性材料であって、前記第1の方向における第1の寸法と、前記第2の方向における第2の寸法と、を有し、前記導電性材料の前記第1及び第2の寸法のそれぞれは、前記マイクロ電子デバイスの前記第1及び第2の寸法よりも小さい、導電性材料と、
を具備し、
前記導電性材料は、所望のインピーダンスが前記導電性部品に対して得られるように、基準電位源に対して接続可能である、マイクロ電子アセンブリ。 - 表面と、該表面にて露出されたデバイス接点と、を有するマイクロ電子デバイスと、
前記マイクロ電子デバイスに隣接する面と、複数の部品接点と、を有する相互接続部品と、
前記デバイス接点を前記部品接点に接続し、前記マイクロ電子デバイスの表面上に延長する配線を有する複数の導電性部品と、
前記導電性部品の上又は下の少なくとも一方の方向で、前記導電性部品の長さの少なくともかなりな部分から、少なくとも実質的に均一な距離で配置される導電面を有する導電性材料であって、所望のインピーダンスが前記導電性部品に対して得られるように、基準電位源に対して接続可能であり、前記導電面は、前記導電性部品が並ぶ面に少なくとも実質的に平行な平面を画定する、導電性材料と、
を具備するマイクロ電子アセンブリ。 - 前記導電面が前記導電性部品の複数の配線の上に重なる、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記導電面が、少なくとも概して平坦である、請求項3に記載のマイクロ電子アセンブリ。
- 前記導電面が、前記マイクロ電子デバイスの表面に対してある角度で傾斜される、請求項4に記載のマイクロ電子アセンブリ。
- 前記複数の配線が複数のボンド・ワイヤのうちの少なくとも一部を含む、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記導電性部品がボンド・ワイヤである、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記ボンド・ワイヤが複数の接続された階段として延長し、前記導電面は、前記ボンド・ワイヤの複数の階段に対して少なくとも実質的に平行に一段づつ延長する、請求項7に記載のマイクロ電子アセンブリ。
- 前記相互接続部品が誘電体部品を含む、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記相互接続部品が基準電位源に接続可能な基準接点を含み、前記導電性材料は、前記基準接点に導電接続される、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記誘電体部品が、前記マイクロ電子部品の表面から離れる方向に、厚さが200マイクロメートル未満のポリマー部品を含む、請求項9に記載のマイクロ電子アセンブリ。
- 前記ポリマー部品がシート状である、請求項11に記載のマイクロ電子アセンブリ。
- 前記導電性部品が前記デバイス接点に金属結合される、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記導電面が絶縁材料によって前記ボンド・ワイヤの複数の配線から分離される、請求項6に記載のマイクロ電子アセンブリ。
- 前記絶縁材料が、前記ボンド・ワイヤの複数の配線が貫通する容積を少なくとも実質的に充填する、請求項14に記載のマイクロ電子アセンブリ。
- 前記導電性材料が、前記相互接続部品の表面にて露出された基準接点に結合され、前記相互接続部品の表面に沿い、前記相互接続部品は、前記基準接点を基準電位源に接続する導体を含む、請求項14に記載のマイクロ電子アセンブリ。
- 前記マイクロ電子デバイスの表面に沿った方向に延長する配線を有する基準導電性部品をさらに含み、前記導電性材料は、前記基準導電性部品の配線に結合される、請求項16に記載のマイクロ電子アセンブリ。
- 前記導電性材料が、前記絶縁材料によって前記導電性部品から少なくとも実質的に均一な距離だけ離間された、少なくとも概して平坦な導電面を有し、前記導電性材料は、少なくとも概して平坦な導電面の下に配置された接続部分を含み、前記接続部分は、前記基準導電性部品に対して機械的及び導電性の電気的接続を有する、請求項16に記載のマイクロ電子アセンブリ。
- 前記基準導電性部品の配線が、前記導電性部品の複数の配線と同じ平面内に少なくとも実質的に存在する、請求項16に記載のマイクロ電子アセンブリ。
- 前記絶縁材料が、外面と、該外面に沿って複数の内側に延びる溝とを有し、前記導電性材料は、前記溝の中に配置される、請求項16に記載のマイクロ電子アセンブリ。
- 前記溝が、前記デバイス接点に接続されたボンド・ワイヤの立ち上がり部分に隣接して配置された溝を含む、請求項20に記載のマイクロ電子アセンブリ。
- 前記ボンド・ワイヤが前記マイクロ電子デバイスの主面に沿って第1の方向に延長する部分を含み、前記溝は、横方向に延びるボンド・ワイヤの部分間の前記第1の方向に延長する溝を含む、請求項20に記載のマイクロ電子アセンブリ。
- 前記導電性材料の端部が、前記相互接続部品の端部に隣接して配置される、請求項1又は2に記載のマイクロ電子アセンブリ。
- 前記デバイス接点が前記マイクロ電子デバイスの前面にて露出され、前記マイクロ電子デバイスが前記前面から離れた裏面と、前記前面と裏面との間に延びる端部とを有し、前記裏面は、前記導電性部品が前記マイクロ電子デバイスの端部を越えて延びるように、前記相互接続部品に装着される請求項1又は2に記載のマイクロ電子アセンブリ。
- 前面と、該前面から離れた裏面と、前記前面に沿って延びる1つ以上の表面導電性部品と、前記前面にて露出されたデバイス接点と、を有するマイクロ電子デバイスと、
前記マイクロ電子デバイスの裏面の下にある誘電体部品を含み、複数の部品接点を上に有する相互接続部品と、
前記デバイス接点を前記部品接点に接続し、1つ以上の表面導電性部品から第1の高さに離間され、かつ該1つ以上の表面導電性部品に対して少なくとも概して平行な配線において延長するかなりの部分を有する複数の立ち上がった導電性部品と、
を具備し、
前記1つ以上の表面導電性部品は、所望のインピーダンスが前記立ち上がった導電性部品に対して実現されるように、基準電位源に対して接続可能である、マイクロ電子アセンブリ。 - 前記1つ以上の表面導電性部品が、前記マイクロ電子デバイスの前面に結合された金属層を含む、請求項25に記載のマイクロ電子アセンブリ。
- 接着剤が、前記1つ以上の表面導電性部品を前記マイクロ電子デバイスの前面に結合する、請求項26に記載のマイクロ電子アセンブリ。
- 前記金属層が開口を有し、前記表面導電性部品が前記金属層内の開口を通って前記デバイス接点に接続される、請求項26に記載のマイクロ電子アセンブリ。
- 表面と、該表面にて露出されたデバイス接点と、を有するマイクロ電子デバイスと、
前記マイクロ電子デバイスに隣接する面と複数の部品接点とを有する相互接続部品と、
前記デバイス接点を前記部品接点に接続する複数のボンド・ワイヤと、
個々の前記ボンド・ワイヤを被覆し、厚さが約30ミクロンよりも厚く、該厚さは、導電性部品のかなりの長さに沿って少なくとも実質的に均一である絶縁材料と、
前記絶縁材料の外面に沿い、絶縁被覆されたボンド・ワイヤ間の容積を充填し、所望のインピーダンスが前記導電性部品に対して実現されるように、基準電位源に接続可能である導電性材料と、
を具備するマイクロ電子アセンブリ。 - 少なくとも前記デバイス接点を前記導電性材料から分離する絶縁性の塊をさらに含む、請求項29に記載のマイクロ電子アセンブリ。
- 前記絶縁性の塊が第1の絶縁性の塊であり、前記アセンブリは、少なくとも前記部品接点を前記導電性材料から分離する第2の絶縁性の塊をさらに含む、請求項30に記載のマイクロ電子アセンブリ。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US21006309P | 2009-03-13 | 2009-03-13 | |
US61/210,063 | 2009-03-13 | ||
KR10-2009-0089470 | 2009-09-22 | ||
KR1020090089470A KR100950511B1 (ko) | 2009-09-22 | 2009-09-22 | 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리 |
PCT/US2010/027141 WO2010105157A2 (en) | 2009-03-13 | 2010-03-12 | Microelectronic assembly with impedance controlled wirebond and conductive reference element |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2012520573A true JP2012520573A (ja) | 2012-09-06 |
JP5651608B2 JP5651608B2 (ja) | 2015-01-14 |
Family
ID=42183995
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011554234A Expired - Fee Related JP5651608B2 (ja) | 2009-03-13 | 2010-03-12 | インピーダンス制御されたワイヤ・ボンド及び導電性基準部品を有するマイクロ電子アセンブリ |
Country Status (7)
Country | Link |
---|---|
US (4) | US7923851B2 (ja) |
EP (1) | EP2406823A2 (ja) |
JP (1) | JP5651608B2 (ja) |
KR (1) | KR100950511B1 (ja) |
CN (1) | CN102449760A (ja) |
TW (1) | TWI431748B (ja) |
WO (1) | WO2010105157A2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012520572A (ja) * | 2009-03-13 | 2012-09-06 | テッセラ,インコーポレイテッド | インピーダンス制御ワイヤーボンド及び基準ワイヤーボンドを有するマイクロ電子アセンブリ |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100950511B1 (ko) * | 2009-09-22 | 2010-03-30 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리 |
US8222725B2 (en) | 2010-09-16 | 2012-07-17 | Tessera, Inc. | Metal can impedance control structure |
US8786083B2 (en) | 2010-09-16 | 2014-07-22 | Tessera, Inc. | Impedance controlled packages with metal sheet or 2-layer RDL |
US8853708B2 (en) | 2010-09-16 | 2014-10-07 | Tessera, Inc. | Stacked multi-die packages with impedance control |
US8581377B2 (en) | 2010-09-16 | 2013-11-12 | Tessera, Inc. | TSOP with impedance control |
US9136197B2 (en) | 2010-09-16 | 2015-09-15 | Tessera, Inc. | Impedence controlled packages with metal sheet or 2-layer RDL |
WO2012071325A1 (en) | 2010-11-24 | 2012-05-31 | Tessera, Inc. | Lead structures with vertical offsets |
KR101118711B1 (ko) | 2010-12-17 | 2012-03-12 | 테세라, 인코포레이티드 | 중앙 콘택을 구비한 적층형 마이크로전자 조립체 |
KR101061531B1 (ko) * | 2010-12-17 | 2011-09-01 | 테세라 리써치 엘엘씨 | 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체 |
FR2980101A1 (fr) | 2011-09-20 | 2013-03-22 | Tornier Inc | Bande de renfort pour la restauration d'un tissu mou |
US9548599B2 (en) * | 2013-08-27 | 2017-01-17 | Labinal, Llc | Thermally managed load module with embedded conductors |
KR20190057136A (ko) * | 2016-10-04 | 2019-05-27 | 더 차레스 스타크 드레이퍼 래보레이토리, 인코포레이티드 | 와이어링 시스템 |
US10224306B2 (en) | 2016-11-03 | 2019-03-05 | Stmicroelectronics (Grenoble 2) Sas | Method for forming an electrical connection between an electronic chip and a carrier substrate and electronic device |
FR3058259A1 (fr) * | 2016-11-03 | 2018-05-04 | Stmicroelectronics (Grenoble 2) Sas | Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique |
FR3058261A1 (fr) * | 2016-11-03 | 2018-05-04 | Stmicroelectronics (Grenoble 2) Sas | Procede de realisation d'une connexion electrique entre une puce electronique et une plaque de support et dispositif electronique |
TWI780576B (zh) * | 2020-12-28 | 2022-10-11 | 抱樸科技股份有限公司 | 具有包覆層之導線的半導體元件及其製作方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268100A (ja) * | 1993-03-12 | 1994-09-22 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の封止構造および封止方法 |
JP2001339016A (ja) * | 2000-05-30 | 2001-12-07 | Alps Electric Co Ltd | 面実装型電子回路ユニット |
WO2005010989A1 (en) * | 2003-07-30 | 2005-02-03 | Koninklijke Philips Electronics, N.V. | Ground arch for wirebond ball grid arrays |
JP2005354068A (ja) * | 2004-06-08 | 2005-12-22 | Samsung Electronics Co Ltd | 側面が封止材で取り囲まれた半導体パッケージ、それを製造するのに利用されるモールド、及びそれを利用した半導体パッケージの製造方法 |
JP2006216823A (ja) * | 2005-02-04 | 2006-08-17 | Akita Denshi Systems:Kk | 半導体装置及びその製造方法並びに電子装置 |
Family Cites Families (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4680613A (en) * | 1983-12-01 | 1987-07-14 | Fairchild Semiconductor Corporation | Low impedance package for integrated circuit die |
US5065282A (en) | 1986-10-17 | 1991-11-12 | Polonio John D | Interconnection mechanisms for electronic components |
US5028983A (en) | 1988-10-28 | 1991-07-02 | International Business Machines Corporation | Multilevel integrated circuit packaging structures |
US4980753A (en) * | 1988-11-21 | 1990-12-25 | Honeywell Inc. | Low-cost high-performance semiconductor chip package |
US5471151A (en) | 1990-02-14 | 1995-11-28 | Particle Interconnect, Inc. | Electrical interconnect using particle enhanced joining of metal surfaces |
JPH04284661A (ja) * | 1991-03-13 | 1992-10-09 | Toshiba Corp | 半導体装置 |
JPH0653277A (ja) | 1992-06-04 | 1994-02-25 | Lsi Logic Corp | 半導体装置アセンブリおよびその組立方法 |
US5880403A (en) * | 1994-04-01 | 1999-03-09 | Space Electronics, Inc. | Radiation shielding of three dimensional multi-chip modules |
JPH0758138A (ja) * | 1993-08-16 | 1995-03-03 | Nec Corp | ワイヤボンディング構造およびそのボンディング方法 |
US6326678B1 (en) * | 1993-09-03 | 2001-12-04 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
US6552417B2 (en) * | 1993-09-03 | 2003-04-22 | Asat, Limited | Molded plastic package with heat sink and enhanced electrical performance |
US5343074A (en) * | 1993-10-04 | 1994-08-30 | Motorola, Inc. | Semiconductor device having voltage distribution ring(s) and method for making the same |
US5639989A (en) * | 1994-04-19 | 1997-06-17 | Motorola Inc. | Shielded electronic component assembly and method for making the same |
JP3034180B2 (ja) | 1994-04-28 | 2000-04-17 | 富士通株式会社 | 半導体装置及びその製造方法及び基板 |
JP2938344B2 (ja) * | 1994-05-15 | 1999-08-23 | 株式会社東芝 | 半導体装置 |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
JPH0927512A (ja) * | 1995-07-10 | 1997-01-28 | Mitsubishi Electric Corp | 半導体装置 |
KR0156334B1 (ko) | 1995-10-14 | 1998-10-15 | 김광호 | 차폐 본딩 와이어를 구비하는 고주파, 고밀도용 반도체 칩 패키지 |
US7166495B2 (en) | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
JPH09260568A (ja) * | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
KR100270817B1 (ko) | 1997-05-22 | 2000-11-01 | 이해영 | 초고주파소자 실장 패키지 및 그 패키지에 사용되는 본딩와이어의 기생효과 감소방법 |
TW473882B (en) | 1998-07-06 | 2002-01-21 | Hitachi Ltd | Semiconductor device |
JP3946874B2 (ja) | 1998-07-06 | 2007-07-18 | 株式会社ルネサステクノロジ | 半導体装置 |
JP3662461B2 (ja) * | 1999-02-17 | 2005-06-22 | シャープ株式会社 | 半導体装置、およびその製造方法 |
JP3483132B2 (ja) | 1999-04-23 | 2004-01-06 | シャープ株式会社 | 高周波半導体装置 |
JP2000332160A (ja) | 1999-05-24 | 2000-11-30 | Sumitomo Metal Electronics Devices Inc | キャビティダウン型半導体パッケージ |
US6822635B2 (en) | 2000-01-19 | 2004-11-23 | Immersion Corporation | Haptic interface for laptop computers and other portable devices |
JP2001223324A (ja) * | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
US6518659B1 (en) * | 2000-05-08 | 2003-02-11 | Amkor Technology, Inc. | Stackable package having a cavity and a lid for an electronic device |
US6538336B1 (en) * | 2000-11-14 | 2003-03-25 | Rambus Inc. | Wirebond assembly for high-speed integrated circuits |
US7161239B2 (en) | 2000-12-22 | 2007-01-09 | Broadcom Corporation | Ball grid array package enhanced with a thermal and electrical connector |
US6770963B1 (en) | 2001-01-04 | 2004-08-03 | Broadcom Corporation | Multi-power ring chip scale package for system level integration |
US6476506B1 (en) * | 2001-09-28 | 2002-11-05 | Motorola, Inc. | Packaged semiconductor with multiple rows of bond pads and method therefor |
US6608390B2 (en) * | 2001-11-13 | 2003-08-19 | Kulicke & Soffa Investments, Inc. | Wirebonded semiconductor package structure and method of manufacture |
TW510034B (en) * | 2001-11-15 | 2002-11-11 | Siliconware Precision Industries Co Ltd | Ball grid array semiconductor package |
US6770822B2 (en) | 2002-02-22 | 2004-08-03 | Bridgewave Communications, Inc. | High frequency device packages and methods |
JP2004079886A (ja) * | 2002-08-21 | 2004-03-11 | Toshiba Corp | 実装体の製造方法、半導体装置及び実装体 |
JP2004112143A (ja) | 2002-09-17 | 2004-04-08 | Sumitomo Metal Electronics Devices Inc | 高周波信号用導体の接続構造、および半導体集積回路パッケージ |
EP1573814A1 (en) | 2002-12-10 | 2005-09-14 | Koninklijke Philips Electronics N.V. | High density package interconnect wire bond strip line and method therefor |
EP1573812A1 (en) * | 2002-12-10 | 2005-09-14 | Koninklijke Philips Electronics N.V. | High density package interconnect power and ground strap and method therefor |
TWI226689B (en) * | 2003-02-25 | 2005-01-11 | Via Tech Inc | Chip package and process for forming the same |
US6812580B1 (en) * | 2003-06-09 | 2004-11-02 | Freescale Semiconductor, Inc. | Semiconductor package having optimized wire bond positioning |
JP4106039B2 (ja) * | 2003-06-27 | 2008-06-25 | 株式会社新川 | ワイヤボンディング方法 |
JP2005026263A (ja) | 2003-06-30 | 2005-01-27 | Nec Compound Semiconductor Devices Ltd | 混成集積回路 |
DE10339770B4 (de) * | 2003-08-27 | 2007-08-30 | Infineon Technologies Ag | Verfahren zum Herstellen einer FBGA-Anordnung |
US7071421B2 (en) | 2003-08-29 | 2006-07-04 | Micron Technology, Inc. | Stacked microfeature devices and associated methods |
US7466021B2 (en) * | 2003-11-17 | 2008-12-16 | Interconnect Portfolio, Llp | Memory packages having stair step interconnection layers |
US7303113B2 (en) * | 2003-11-28 | 2007-12-04 | International Business Machines Corporation | Method and structure for controlled impedance wire bonds using co-dispensing of dielectric spacers |
JP4570868B2 (ja) * | 2003-12-26 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7205651B2 (en) | 2004-04-16 | 2007-04-17 | St Assembly Test Services Ltd. | Thermally enhanced stacked die package and fabrication method |
US7151309B2 (en) * | 2004-08-27 | 2006-12-19 | Texas Instruments Incorporated | Apparatus for improved power distribution in wirebond semiconductor packages |
TWI393228B (zh) | 2004-12-14 | 2013-04-11 | Freescale Semiconductor Inc | 覆晶及焊線封裝半導體 |
TWM269568U (en) * | 2004-12-16 | 2005-07-01 | Domintech Co Ltd | Chip package capable of reducing characteristic resistance |
US7566952B2 (en) | 2005-01-05 | 2009-07-28 | International Business Machines Corporation | On-chip circuit pad structure |
DE102005002707B4 (de) * | 2005-01-19 | 2007-07-26 | Infineon Technologies Ag | Verfahren zur Herstellung elektrischer Verbindungen in einem Halbleiterbauteil mittels koaxialer Mikroverbindungselemente |
US20060175712A1 (en) | 2005-02-10 | 2006-08-10 | Microbonds, Inc. | High performance IC package and method |
KR100702970B1 (ko) | 2005-07-06 | 2007-04-03 | 삼성전자주식회사 | 이원 접속 방식을 가지는 반도체 패키지 및 그 제조 방법 |
US7456505B2 (en) * | 2005-07-29 | 2008-11-25 | Infineon Technologies Ag | Integrated circuit chip and integrated device |
SG130061A1 (en) * | 2005-08-24 | 2007-03-20 | Micron Technology Inc | Microelectronic devices and microelectronic support devices, and associated assemblies and methods |
US8026129B2 (en) | 2006-03-10 | 2011-09-27 | Stats Chippac Ltd. | Stacked integrated circuits package system with passive components |
CN101410974B (zh) | 2006-03-23 | 2013-02-20 | 台湾积体电路制造股份有限公司 | 增强型电子键合引线封装 |
US20080014678A1 (en) * | 2006-07-14 | 2008-01-17 | Texas Instruments Incorporated | System and method of attenuating electromagnetic interference with a grounded top film |
US7777353B2 (en) * | 2006-08-15 | 2010-08-17 | Yamaha Corporation | Semiconductor device and wire bonding method therefor |
DE102006042775B3 (de) | 2006-09-12 | 2008-03-27 | Qimonda Ag | Schaltungsmodul und Verfahren zur Herstellung eines Schaltungsmoduls |
US7537962B2 (en) * | 2006-12-22 | 2009-05-26 | Stats Chippac Ltd. | Method of fabricating a shielded stacked integrated circuit package system |
US7875985B2 (en) | 2006-12-22 | 2011-01-25 | Qimonda Ag | Memory device |
US7723852B1 (en) | 2008-01-21 | 2010-05-25 | Amkor Technology, Inc. | Stacked semiconductor package and method of making same |
US7843021B2 (en) | 2008-02-28 | 2010-11-30 | Shandong Gettop Acoustic Co. Ltd. | Double-side mountable MEMS package |
US8159052B2 (en) * | 2008-04-10 | 2012-04-17 | Semtech Corporation | Apparatus and method for a chip assembly including a frequency extending device |
US7768135B1 (en) | 2008-04-17 | 2010-08-03 | Amkor Technology, Inc. | Semiconductor package with fast power-up cycle and method of making same |
US8294249B2 (en) * | 2008-08-05 | 2012-10-23 | Integrated Device Technology Inc. | Lead frame package |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
KR101257737B1 (ko) | 2008-08-22 | 2013-04-25 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 메타 물질을 사용하는 임피던스 제어 전기 상호접속 |
JP2010192680A (ja) | 2009-02-18 | 2010-09-02 | Elpida Memory Inc | 半導体装置 |
KR100950511B1 (ko) * | 2009-09-22 | 2010-03-30 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 도전성 기준 소자에 의해 제어되는 임피던스를 포함하는 마이크로전자 어셈블리 |
KR100935854B1 (ko) | 2009-09-22 | 2010-01-08 | 테세라 리써치 엘엘씨 | 와이어 본딩 및 기준 와이어 본딩에 의해 제어되는 임피던스를 가진 마이크로전자 어셈블리 |
JP5590814B2 (ja) | 2009-03-30 | 2014-09-17 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置及びその製造方法 |
US8916958B2 (en) * | 2009-04-24 | 2014-12-23 | Infineon Technologies Ag | Semiconductor package with multiple chips and substrate in metal cap |
US8786083B2 (en) | 2010-09-16 | 2014-07-22 | Tessera, Inc. | Impedance controlled packages with metal sheet or 2-layer RDL |
US8222725B2 (en) | 2010-09-16 | 2012-07-17 | Tessera, Inc. | Metal can impedance control structure |
US8853708B2 (en) | 2010-09-16 | 2014-10-07 | Tessera, Inc. | Stacked multi-die packages with impedance control |
US8581377B2 (en) | 2010-09-16 | 2013-11-12 | Tessera, Inc. | TSOP with impedance control |
-
2009
- 2009-09-22 KR KR1020090089470A patent/KR100950511B1/ko not_active IP Right Cessation
-
2010
- 2010-03-12 US US12/722,784 patent/US7923851B2/en active Active
- 2010-03-12 JP JP2011554234A patent/JP5651608B2/ja not_active Expired - Fee Related
- 2010-03-12 WO PCT/US2010/027141 patent/WO2010105157A2/en active Application Filing
- 2010-03-12 CN CN2010800208512A patent/CN102449760A/zh active Pending
- 2010-03-12 EP EP10714122A patent/EP2406823A2/en not_active Withdrawn
- 2010-03-12 TW TW099107377A patent/TWI431748B/zh not_active IP Right Cessation
-
2011
- 2011-01-07 US US12/986,601 patent/US8269357B2/en active Active
- 2011-01-07 US US12/986,556 patent/US8575766B2/en not_active Expired - Fee Related
-
2013
- 2013-11-04 US US14/071,055 patent/US8994195B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06268100A (ja) * | 1993-03-12 | 1994-09-22 | Nippon Telegr & Teleph Corp <Ntt> | 半導体装置の封止構造および封止方法 |
JP2001339016A (ja) * | 2000-05-30 | 2001-12-07 | Alps Electric Co Ltd | 面実装型電子回路ユニット |
WO2005010989A1 (en) * | 2003-07-30 | 2005-02-03 | Koninklijke Philips Electronics, N.V. | Ground arch for wirebond ball grid arrays |
JP2005354068A (ja) * | 2004-06-08 | 2005-12-22 | Samsung Electronics Co Ltd | 側面が封止材で取り囲まれた半導体パッケージ、それを製造するのに利用されるモールド、及びそれを利用した半導体パッケージの製造方法 |
JP2006216823A (ja) * | 2005-02-04 | 2006-08-17 | Akita Denshi Systems:Kk | 半導体装置及びその製造方法並びに電子装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012520572A (ja) * | 2009-03-13 | 2012-09-06 | テッセラ,インコーポレイテッド | インピーダンス制御ワイヤーボンド及び基準ワイヤーボンドを有するマイクロ電子アセンブリ |
Also Published As
Publication number | Publication date |
---|---|
EP2406823A2 (en) | 2012-01-18 |
JP5651608B2 (ja) | 2015-01-14 |
US20100230828A1 (en) | 2010-09-16 |
US8575766B2 (en) | 2013-11-05 |
US8269357B2 (en) | 2012-09-18 |
WO2010105157A2 (en) | 2010-09-16 |
US20140103500A1 (en) | 2014-04-17 |
US7923851B2 (en) | 2011-04-12 |
TW201044536A (en) | 2010-12-16 |
US20110095408A1 (en) | 2011-04-28 |
WO2010105157A3 (en) | 2012-02-23 |
US8994195B2 (en) | 2015-03-31 |
CN102449760A (zh) | 2012-05-09 |
US20110101535A1 (en) | 2011-05-05 |
TWI431748B (zh) | 2014-03-21 |
KR100950511B1 (ko) | 2010-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5651608B2 (ja) | インピーダンス制御されたワイヤ・ボンド及び導電性基準部品を有するマイクロ電子アセンブリ | |
US8415789B2 (en) | Three-dimensionally integrated semicondutor device and method for manufacturing the same | |
KR101734882B1 (ko) | 영역 어레이 유닛 컨넥터를 갖는 적층 가능한 몰딩된 마이크로전자 패키지 | |
US8253259B2 (en) | Microelectronic assembly with impedance controlled wirebond and reference wirebond | |
US7968369B2 (en) | Microelectronic devices and microelectronic support devices, and associated assemblies and methods | |
CN202042472U (zh) | 具有用于高电流、高频和热量耗散的穿透硅通孔的半导体器件 | |
JP2002184934A (ja) | 半導体装置及びその製造方法 | |
US8222725B2 (en) | Metal can impedance control structure | |
JPH11163217A (ja) | 半導体装置 | |
US20070145607A1 (en) | System to wirebond power signals to flip-chip core | |
KR20230019926A (ko) | 반도체 장치 및 반도체 장치의 제조 방법 | |
CN116130444A (zh) | 半导体封装装置及其制造方法 | |
JPH09199534A (ja) | 半導体装置及びその製造方法、半導体装置用テープキャリア |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20130312 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130709 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130712 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20131011 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20131021 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20140711 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20141009 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141031 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20141117 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5651608 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |