CN101432868A - 用于使用牺牲金属基础的封装类型的三维封装方案 - Google Patents

用于使用牺牲金属基础的封装类型的三维封装方案 Download PDF

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CN101432868A
CN101432868A CNA200780014844XA CN200780014844A CN101432868A CN 101432868 A CN101432868 A CN 101432868A CN A200780014844X A CNA200780014844X A CN A200780014844XA CN 200780014844 A CN200780014844 A CN 200780014844A CN 101432868 A CN101432868 A CN 101432868A
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small pieces
tunnel
circuit small
line joint
metal base
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肯·M·兰姆
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Atmel Corp
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Atmel Corp
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Abstract

一种用于封装半导体装置的设备及方法。所述设备可应用于使用牺牲金属基础条的许多种类型的现代封装方案。穿过包围装置(207)及相关联的接合线(211)的囊封区域(215)形成的隧道(213)通过(举例来说)电镀填充有金属导体并从底部接触垫(205)延伸到经囊封区域(215)的最高部分。牺牲金属基础条(201)充当镀敷汇流条且在镀敷之后被蚀刻移除。经填充的隧道(213)允许组件以三维配置进行堆叠。

Description

用于使用牺牲金属基础的封装类型的三维封装方案
技术领域
本发明涉及三维可堆叠半导体封装，且更特定来说涉及用于具有牺牲金属基础的封装类型的三维可堆叠半导体封装。
背景技术
随着半导体集成电路芯片变得更加多功能性及高集成性，所述芯片包括更多接合垫(或端子垫)，且因此用于所述芯片的封装具有更多的外部端子(或引线)。当使其引线沿封装周长的常规塑料封装必须容纳大数量的引线时，所述封装的覆盖范围增大。然而，许多电子系统的目标是使所述系统的总大小降到最低。因此，为容纳大数量的引脚而不增大封装的覆盖范围，那么必须减小所述封装的引脚间距(或引线间距)。然而，小于约0.4mm的引脚间距导致许多技术关注。举例来说，修整具有小于0.4mm的引脚间距的封装需要昂贵的修整工具，且引线易于在处置所述封装期间弯曲。此外，由于所需要的关键对准步骤，此类封装的表面安装需要成本高且复杂的表面安装工艺。
因此，为避免与常规微间距封装相关联的技术问题，已提出具有面积阵列外部端子的封装。这些封装包括球栅阵列封装及芯片级封装。半导体工业目前使用多个芯片级封装。微球栅阵列封装(μBGA)及凸块芯片载体(BCC)为芯片级封装的实例。所述μBGA封装包括其上形成有导电图案的聚酰亚胺带并采用与常规塑料封装完全不同的制造工艺。所述凸块芯片载体封装包括具有在铜合金板的顶表面的中心部分周围形成的槽的衬底及在所述槽中形成的电镀层。因此，芯片级封装使用增加封装制造成本的专门封装材料及工艺。
图1A至1C图解说明用于制造无铅BCC封装的常规设备的平面图及截面图。参照图1A的平面图，常规金属载体矩阵阵列101具有上表面103，所述上表面包括具有多个锯割线107的囊封矩阵105。
图1B的截面图包括在金属载体101的上表面103上通过镀敷形成的多个凸块垫109及多个电路小片垫111。集成电路电路小片113的下表面附装到对应的电路小片垫111，且多个接合线115将电路小片113的有源表面上的多个接合垫117连接到对应的凸块垫109。囊封剂119囊封包括电路小片113及接合线115的矩阵105。
参照图1C的下侧平面图，在蚀刻掉金属载体101(未在图1C中显示)之后，凸块垫109及电路小片垫111从囊封剂119的底表面121暴露。然后，通过沿锯割线107锯割来将囊封剂119单个化以形成多个个别BCC封装。
因此，可仅接触使用常规封装材料及工艺的集成电路封装以通过所述封装的底表面121上的凸块垫电互连(举例来说)到印刷电路板。因此，提供封装到给定印刷电路板覆盖范围中的更高密度的集成电路需要的是一种允许以一者在另一者顶部上的形式堆叠所述集成电路封装的方法。
发明内容
本发明是一种用于封装半导体装置的设备及方法。所述设备可应用于使用牺牲金属基础条的许多种类型的现代封装方案。穿过包围装置及相关联的接合线的囊封体积而形成的隧道通过(举例来说)电镀由金属导体填充。经填充的隧道从底部接触垫延伸到经囊封区域的最高部分。所述牺牲金属基础条充当镀敷汇流条且在镀敷之后被蚀刻移除。所述经填充的隧道允许组件以三维配置进行堆叠。在具体实例性实施例中，可将本发明应用于多个电路小片或可堆叠封装内电路与电路小片的组合。然后，可以三维方式堆叠所述可堆叠封装中的每一者而不增大(举例来说)印刷电路板上的安装区域的总覆盖范围大小。
因此，在一个实例性实施例中，本发明为半导体封装矩阵。所述半导体封装矩阵包括在所述矩阵内并排布置成阵列且由锯缝区域隔开的多个三维可堆叠半导体封装。所述锯缝区域定位于所述多个三维可堆叠半导体封装中的每一者的最外围处。所述多个三维可堆叠半导体封装中的每一者包括用于安装集成电路电路小片及/或一个或一个以上离散电组件及的区域及与电路小片安装区域大致共面的多个线接合垫。所述多个线接合垫中的每一者允许接合线提供从所述集成电路电路小片及/或所述一个或一个以上离散电组件到所述经封装装置的外部的电连通。
制模帽具有最低部分及最高部分。所述最低部分处于与所述电路小片安装区域及所述多个线接合垫大致共面的水平。所述制模帽具有多个导电接触隧道，所述导电接触隧道中的每一者相关联且经布置以在导电材料填充所述导电接触隧道的情况下与所述多个线接合垫中的对应一者电连通。所述多个导电接触隧道从所述多个线接合垫的最高部分延伸到所述制模帽的最高部分。
本发明还是一种封装半导体装置(或单个封装中的多个装置)的方法。所述方法的实例性实施例包括将电组件安装到电路小片安装区域且将来自所述电组件上的多个接合垫的多个接合线固定到多个线接合垫中的对应线接合垫。提供具有多个导电接触隧道的模腔。所述接触隧道经布置使得所述多个导电接触隧道设置于所述多个线接合垫上方。用制模化合物囊封所述电组件及所述接合线，从而大致上填充所述模腔。然后，用导电材料填充所述多个导电接触隧道。
附图说明
图1A-1C显示现有技术的凸块芯片载体。
图2A-2E显示根据本发明的可堆叠集成电路电路小片及离散组件载体的实例性截面。
具体实施方式
在图2A中，潜在可堆叠集成电路电路小片及离散组件载体的截面图包括牺牲金属基础条201、多个电路小片安装区域203及多个线接合垫205。如图所示，多个集成电路电路小片207安装到所述多个电路小片安装区域203中的对应电路小片安装区域。另一选择为，所述多个集成电路电路小片207还可以是离散组件(未显示)或安装到多个电路小片安装区域的集成电路电路小片与离散组件的组合。此外，所述牺牲金属基础层可由导电非金属材料构造，例如(举例来说)具有嵌入的碳微粒的聚丙烯或外表面镀敷有金属的聚合物条。
如所属技术领域中已知，通常使用导热粘合剂或胶带(两者均未显示)来将所述多个电路小片207安装到相关联的电路小片安装区域203。如所属技术领域中的技术人员将认识到，也可使用其它类型的粘合剂(例如，非导热、导电及非导电等)或其它安装技术。所述多个电路小片207各自包括多个接合垫209。一旦安装所述多个电路小片207，那么使用多个接合线211来将所述多个接合垫209电连接到所述多个线接合垫205中的所选定者。
通常将所述多个线接合垫205、电路小片207及接合线211囊封于制模化合物中。通过定位于牺牲金属基础条201的边缘处的制模浇口来将所述制模化合物引入模腔(未显示)内。所述制模化合物通常为由填充有二氧化硅及酐的环氧基材料组成的聚合前驱物，需要热能以进行固化以形成聚合囊封215。囊封215保护易碎的多个接合线211及其相关联的电连接以及所述多个电路小片207。在此实施例中，管道定位于所述多个线接合垫205中的每一者上方，从而在灌注并形成囊封215之后形成隧道213。可通过将引脚或其它结构置于模具中形成所述管道或后来添加所述管道(例如，机器加工或焊接到模腔中的适当位置)。路线217指示在后续切割操作中锯缝将要经过的地方。
参照图2B，隧道213已填充有导体以产生多个导电金属触点219。在具体实例性实施例中，牺牲金属基础条210提供电解镀敷工艺所需要的电连续性，因此可通过填充隧道213(图2A)来制作多个导电金属触点219(例如，铜)。然后，可视情况用(举例来说)镍-金合金帽或其它贵金属覆盖用于制作所述多个导电金属触点219的铜或几乎任何其它金属。另一选择为，可通过(举例来说)用材料(例如，钨或钽)镀敷到隧道213内来制作所述多个导电金属触点219。另外，可使用导电环氧树脂或聚合物来填充隧道213。然后，将所述导电环氧树脂固化到位。
然后，通过所属技术领域中已知的工艺蚀刻移除(图2C)牺牲金属基础条201。举例来说，可用金-镍-金或钯-金来镀敷电路小片安装区域及线接合垫，使得在蚀刻之后仅留下所述合金接合区域完整。然后，举例来说，通过电路小片锯或激光来将所述电路小片单个化(图2D)，从而产生第一251及第二253经封装产品。
参照图2E，以机械方式将单个化的第一251及第二253经封装产品堆叠。所述多个导电金属触点219允许一个层级(例如，在所述第一经封装产品251处)处的线接合垫205中的每一者通过使用焊料(例如，焊料膏)、导电环氧树脂、金属接合(例如，通过应用超声波或热力)等等互连到将要电连接的另一等级(例如，到所述第二经封装产品253)。因此，不存在对可堆叠的封装数量的限制。
在上述说明书中，已参照本发明的具体实施例说明了本发明。然而，将对所属技术领域中的技术人员显而易见的是，可在不背离所附权利要求书中所论述的本发明的较宽广精神及范围的情况下对本发明做出各种修改及改变。举例来说，所属技术领域中的技术人员将了解，本发明的实施例可容易地应用于
Figure A200780014844D00071
(薄阵列塑料封装)、
Figure A200780014844D00072
(超薄焊盘栅格阵列)、(凸块芯片载体)或其它类似封装类型。因此，须将本说明书及图式视为仅具有例示意义而非限制意义。

Claims (10)

1、一种三维可堆叠半导体封装，其包含：
至少一个电路小片安装区域，所述至少一个电路小片安装区域经配置以接纳集成电路电路小片或一个或一个以上离散电组件；
多个线接合垫，其与所述至少一个电路小片安装区域大致共面，所述多个线接合垫中的每一者经配置以接纳接合线，从而提供与所述集成电路电路小片或所述一个或一个以上离散电组件的电连通；及
制模帽，其具有最低部分及最高部分，所述最低部分处于与所述至少一个电路小片安装区域及所述多个线接合垫大致共面的水平，所述制模帽还具有多个导电接触隧道，所述多个导电接触隧道中的每一者相关联且经布置以在导电材料填充所述导电接触隧道时即刻与所述多个线接合垫中的对应一者电连通，所述多个导电接触隧道从所述多个线接合垫的最高部分延伸到所述制模帽的所述最高部分。
2、如权利要求1所述的三维可堆叠半导体封装，其进一步包含牺牲金属基础层，所述牺牲金属基础层充当所述至少一个电路小片安装区域及所述多个线接合垫的安装基础及电触点。
3、如权利要求2所述的三维可堆叠半导体封装，其中所述牺牲金属基础层经配置以在于所述制模帽内形成囊封制模化合物时即刻被蚀刻移除。
4、一种封装半导体装置的方法，所述方法包含：
将电组件安装到电路小片安装区域；
将来自所述电组件上的多个接合垫的多个接合线固定到多个线接合垫中的对应者；
提供具有多个导电接触隧道的模腔，使得所述多个导电接触隧道中的每一者的第一端设置在所述多个线接合垫中的相关联者上方并与其接触；
用制模化合物囊封所述电组件及所述多个接合线，所述制模化合物大致上填充所述模腔；及
用导电材料填充所述多个导电接触隧道。
5、如权利要求4所述的方法，其进一步包含将所述导电填充材料选择为大致上由铜组成。
6、如权利要求4所述的方法，其进一步包含提供导电覆盖材料以设置于所述经填充导电接触隧道的暴露端上方。
7、如权利要求6所述的方法，其中将所述覆盖材料选择为镍-金合金。
8、如权利要求4所述的方法，其进一步包含从所述经封装的半导体装置蚀刻移除牺牲基础材料。
9、如权利要求4所述的方法，其进一步包含以一者在另一者顶部上的形式堆叠多个半导体装置封装。
10、如权利要求9所述的方法，其进一步包含将第一经封装半导体装置上的所述多个经填充导电接触隧道中的每一者电耦合到第二经封装半导体装置上的所述多个经填充导电接触隧道中的每一者。
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CN103515249A (zh) * 2013-08-06 2014-01-15 江苏长电科技股份有限公司 先封后蚀三维系统级芯片正装凸点封装结构及工艺方法
CN103515249B (zh) * 2013-08-06 2016-02-24 江苏长电科技股份有限公司 先封后蚀三维系统级芯片正装凸点封装结构及工艺方法

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