CN102414825A - 功率用半导体装置 - Google Patents

功率用半导体装置 Download PDF

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Publication number
CN102414825A
CN102414825A CN2009801590094A CN200980159009A CN102414825A CN 102414825 A CN102414825 A CN 102414825A CN 2009801590094 A CN2009801590094 A CN 2009801590094A CN 200980159009 A CN200980159009 A CN 200980159009A CN 102414825 A CN102414825 A CN 102414825A
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Prior art keywords
insulating film
layer
pad portion
buffer insulating
power semiconductor
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CN2009801590094A
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CN102414825B (zh
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中田和成
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
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    • H01L2924/1304—Transistor
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    • H01L2924/30105—Capacitance

Abstract

本发明涉及功率用半导体装置。栅极电极（26）用于控制流过半导体层（SL）的电流。栅极绝缘膜（29）将半导体层（SL）与栅极电极（26）彼此电绝缘。导体部（24）设置在半导体层（SL）上且与半导体层（SL）电连接。层间绝缘膜(25)以导体部（24）与栅极电极（26）电绝缘的方式设置在栅极电极（26）上。缓冲绝缘膜（23）覆盖导体部（24）及层间绝缘膜（25）上的一部分区域并且由绝缘体构成。电极层（21）具有位于导体部（24）露出的区域上的布线部分（21w）及位于缓冲绝缘膜（23）上的焊盘部分（21p）。由此，能够抑制引线（22）连接到焊盘部分（21p）时对IGBT的损伤。此外，能够防止电流集中引起的破坏的产生，能够处理更大的功率。

Description

功率用半导体装置
技术领域
本发明涉及功率用半导体装置。
背景技术
在产业用马达或汽车用马达等的变换器电路（inverter circuit）、大容量服务器的电源装置、以及不间断电源装置等中，主要使用用于处理从数百千瓦到数兆瓦的比较大的功率的功率用半导体装置。作为该功率用半导体装置，存在例如MOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)以及IGBT（Insulated Gate Bipolar Transistor）等半导体开关。作为IGBT，以往广泛使用平面栅极型的IGBT，但是，近年来开始使用采用了能够高集成化的沟槽栅极的纵型的IGBT。
为了使采用了这样的沟槽栅极的IGBT能够处理的电流进一步增大，例如，根据日本特开2007-273931号公报（专利文献1），功率用半导体元件（功率用半导体装置）具有发射极插塞（emitter plug）和与该发射极插塞连接的发射极焊盘。
在上述的焊盘上例如利用引线键合进行电连接。此时，存在由于焊盘正下方的部分受到的冲击而使晶体管受到损伤的情况。这与高集成化相伴，很大原因在于各部位尺寸（间隔或大小、膜厚等）的细微化。为了抑制这样的损伤，例如，根据日本特开2006-324265号公报，半导体装置的特征在于：在焊盘正下方交替地层叠多个导电层布线金属和层间绝缘膜，夹着层间绝缘膜而相邻的导电层布线金属经由通孔被连接，所层叠的层被分割为层间绝缘膜的材料不同的多个精细层（fine layer），在材料不同的层间绝缘膜间的界面的上层所形成的层间绝缘膜上形成的通孔的直径比其他通孔的直径大。
现有技术文献
专利文献
专利文献1：日本特开2007-273931号公报；
专利文献2：日本特开2006-324265号公报。
发明内容
发明要解决的课题
根据上述日本特开2007-273931号公报的技术，如上述那样，存在如下问题：在进行向焊盘的电连接时，功率用半导体装置受到损伤。
此外，根据上述日本特开2006-324265号公报的技术，经由直径彼此不同的多个通孔进行电连接。因此在制造工序中所需的构图次数变多，所以，容易产生图形缺陷或图形偏差。其结果是，功率用半导体装置的通电能力容易产生偏差。特别是，具有小的直径的通孔的剖面积产生偏差，从而该通电能力产生很大偏差。因此，存在难以稳定地得到处理较大的功率的功率用半导体装置这样的问题。
本发明是为了解决上述问题而提出的，其目的在于提供一种功率用半导体装置，能够处理较大的功率并且能够抑制由于向焊盘的电连接而产生的损伤。
用于解决课题的手段
本发明的功率用半导体装置具有半导体层、栅极电极、栅极绝缘膜、导体部、层间绝缘膜、缓冲绝缘膜、电极层。栅极电极用于对流过半导体层的电流进行控制。栅极绝缘膜将半导体层与栅极电极彼此电绝缘。导体部设置在半导体层上，并且与半导体层电连接。层间绝缘膜以导体部与栅极电极电绝缘的方式设置在栅极电极上。缓冲绝缘膜覆盖导体部以及层间绝缘膜上的一部分区域，并且由绝缘体构成。电极层具有：布线部分，位于导体部露出的区域上；焊盘部分，位于缓冲绝缘膜上。
发明效果
根据本发明的功率用半导体装置，焊盘部分位于缓冲绝缘膜上。因此，在与焊盘部分进行电连接时施加到半导体层的冲击被缓冲绝缘膜缓和。因此，能够抑制对功率用半导体装置的损伤。此外，将焊盘部分的正下方的半导体层和焊盘部分之间直线地连结的较短的电流路径被缓冲绝缘膜切断。因此，能够防止焊盘部分的正下方的电流集中。因此，防止了电流集中所引起的功率用半导体装置的破坏，所以，能够处理更大的功率。
附图说明
图1是示意性地示出本发明的实施方式1的功率用半导体装置的结构的部分平面图。
图2是沿图1的线II-II的示意剖面图。
图3是示出由于向本发明的实施方式1的功率用半导体装置的焊盘部分的电连接而产生的不良率和缓冲绝缘膜的厚度的加速条件下的关系的一例的图表。
图4是示意性地示出本发明的实施方式2的功率用半导体装置的结构的部分平面图。
具体实施方式
以下，基于附图对本发明的实施方式进行说明。并且，在部分平面图（图1以及图4）中未示出发射极电极（电极层）以及引线，此外，为了使附图容易观察，对导体部以及层间绝缘膜附加了阴影线。
（实施方式1）
参照图1以及图2，作为本实施方式的功率用半导体装置的IGBT具有半导体层SL、栅极电极26、栅极绝缘膜29、导体部24、层间绝缘膜25、缓冲绝缘膜23、发射极电极21（电极层）、集电极电极33、引线22。
半导体层SL作为IGBT的半导体部分，具有成为发射极的nE层27、用于得到欧姆接触的p+层28、被称为基极等的nB层30、pB层31、以及成为集电极的pC层32。nE层27以及nB层30是n型的半导体层，p+层28、pB层31以及pC层32是p型的半导体层，半导体层是硅层。此外，半导体层SL具有沿着一个方向（图1中的纵向）延伸并且在与该方向正交的方向（图1以及图2中的横向）彼此空出间隔配置的多个沟槽。各沟槽面向nE层27、pB层31以及nB层30。即，沟槽在半导体层中形成为条纹状。
栅极电极26作为IGBT的栅极电极，用于控制在厚度方向（图2中的纵向）流过半导体层SL的电流。即，本实施方式的功率用半导体装置是纵型IGBT。此外，栅极电极26是通过在形成于半导体层SL的沟槽中埋入例如多晶硅而形成的，是所谓的沟槽栅极。栅极绝缘膜29由薄的硅氧化膜等构成，将半导体层SL和栅极电极26彼此电绝缘。
导体部24设置在半导体层SL上，与半导体层SL的nE层27以及p+层28电连接，另一方面，在栅极电极26上以与栅极电极26电绝缘的方式设置有层间绝缘膜25。并且，导体部24以比栅极电极26的导电率大的例如钨材料形成。此外，层间绝缘膜25以使用了例如作为有机类的材料的TEOS（tetraethylorthosilicate）的硅氧化膜（下面，称为TEOS膜）形成。导体部24是设置于层间绝缘膜25的所谓的触点（插塞），将半导体层SL和发射极电极21电连接。
如图1所示，缓冲绝缘膜23覆盖导体部24以及层间绝缘膜25上的一部分区域。因此，如图2所示，缓冲绝缘膜23包括隔着层间绝缘膜25而位于栅极电极26上的部分。并且，在该情况下，优选在平面图中与沟槽延伸的方向平行的缓冲绝缘膜23的端部（图1中的左右两端）不在导体部24上而位于层间绝缘膜25上。此外，缓冲绝缘膜23是由绝缘体构成的膜，例如是与层间绝缘膜25同样的TEOS膜、SOG（spin on glass）膜、或者有机类绝缘膜。作为有机类绝缘膜，能够使用例如聚酰亚胺膜。
发射极电极21以例如铝形成并且具有：位于缓冲绝缘膜23上的焊盘部分21p；以在平面图中包围该焊盘部分21p的方式位于导体部24以及层间绝缘膜25上的布线部分21w。
焊盘部分21p用作键合焊盘。即，焊盘部分21p是用于对引线22进行键合的部分。
布线部分21w位于不被缓冲绝缘膜23覆盖而使导体部24以及层间绝缘膜25露出的部分（导体部24以及层间绝缘膜25上的上述一部分区域以外）上。因此，布线部分21w在其正下方具有与导体部24的直接的电连接，与在其正下方和导体部24绝缘的焊盘部分21p电连接。
引线22在接合部分44与发射极电极21的焊盘部分21p接合。引线22例如是应用了利用超声波进行的引线键合法的铝引线。
作为与焊盘部分21p对应的优选的缓冲绝缘膜23的各部分尺寸，首先，其膜厚具有发射极电极21的焊盘部分21p的厚度的五分之一以上并且五分之四以下的厚度。
并且，关于缓冲绝缘膜23的幅度，具有引线22的宽度（直径）尺寸以上且3倍以下的宽度尺寸（图1中的纵向的尺寸）和与引线22接合的接合部分44的长度以上且3倍以下的长度（图1中的横向的长度）。此外，在与多个引线22对应地具有多个缓冲绝缘膜23的情况下，缓冲绝缘膜23的面积的合计（总面积）具有发射极电极21的面积的二分之一以下的面积。
根据本实施方式，如图2所示，作为键合焊盘的焊盘部分21p位于缓冲绝缘膜23上。因此，在键合时施加到半导体层SL的冲击AF被缓冲绝缘膜23缓和，所以，能够抑制引线22被连接到焊盘部分21p时的对IGBT的损伤。
此外，缓冲绝缘膜23包括隔着层间绝缘膜25而位于栅极电极26上的部分。因此，栅极电极26被缓冲绝缘膜23保护而免受冲击AF。
此外，如上述那样，引线22的连接所引起的损伤被抑制，所以，能够以更强的条件进行引线22的引线键合。具体地说，例如能够使用更强的超声波或者更强的载荷进行引线键合。由此，能够增大引线22与焊盘部分21p的接合部分44的接合强度以及接合面积。因此，能够延长接合部分44由于温度循环而最终剥离的极限寿命即功率循环寿命。由此，能够确保充分的寿命并且能够处理更大的功率。
特别是，如本实施方式那样，在栅极电极26是沟槽栅极的情况下，假设当较大的冲击AF施加到沟槽附近时，在栅极电极26和nE层27之间容易产生裂纹。当产生这样的裂纹时，在栅极电极26和nE层27之间，耐压降低或者产生短路。但是，根据本实施方式，冲击AF被缓冲绝缘膜23缓和，所以，能够抑制上述的那样的裂纹的产生。
此外，根据本实施方式，如图2所示，将焊盘部分21p的正下方的p+层28和焊盘部分21p之间直线地连接的较短的电流路径AI被缓冲绝缘膜23切断。因此，能够防止引线22的接合部分44所在的焊盘部分21p的正下方的电流集中，所以，防止由该电流集中所导致的破坏。因此，能够防止电流集中所导致的破坏的产生，并且，能够处理更大的功率。
此外，导体部24的导电率比栅极电极26的导电率大。利用该导电率较大的导体部24，分别在nE层27和p+层28，能够降低依赖于直到焊盘部分21p为止的电路径的长度的电压降。由此，能够使IGBT整体更加均匀地动作，所以，能够处理更大的功率。
此外，缓冲绝缘膜23具有发射极电极21的焊盘部分21p的厚度的五分之一以上并且五分之四以下的厚度。在缓冲绝缘膜23的厚度满足这样的条件的情况下，能够降低功率用半导体装置的不良率。进行该验证实验的结果是，如图3所示，确认了发射极电极21的焊盘部分21p的厚度和缓冲绝缘膜23的厚度的膜厚比RT（横轴）与向焊盘部分21p连接引线22时的不良率DR的关系。即，将发射极电极21的焊盘部分21p的厚度设为1的情况下的缓冲绝缘膜23的膜厚比RT为0.2以上且0.8以下（五分之一以上且五分之四以下），由此，不良率DR显著地减低。
并且，在缓冲绝缘膜23的膜厚比RT小于0.2的情况下，由于引线键合时的冲击AF（图2），缓冲绝缘膜23容易损伤，由此，进而产生在栅极电极26和nE层27之间发生短路这样的损伤，不良率DR上升。此外，在缓冲绝缘膜23的膜厚RT超过0.8的情况下，发射极电极21的焊盘部分21p与布线部分21w的边界处的台阶差变得过度地大，在该台阶差部分产生断线，由此，不良率DR上升。
此外，缓冲绝缘膜23具有发射极电极21的面积的二分之一以下的面积。由此，发射极电极21被缓冲绝缘膜23遮挡的部分被限定，所以，关于发射极电极21的有效面积，能够确保充分的大小。因此，能够抑制IGBT的导通电压的上升和饱和电流的下降。
此外，缓冲绝缘膜23由使用了有机类的材料的TEOS膜或SOG膜、有机类绝缘膜（聚酰亚胺膜）等构成。由此，与缓冲绝缘膜23由无机类的材料（硅烷等）构成的情况相比，能够以低温形成缓冲绝缘膜23。因此，能够在半导体层SL中的杂质不进行再扩散的情况下，以更高的精度对杂质分布图进行控制。此外，能够容易地形成厚度较大的缓冲绝缘膜23，所以，能够缓和冲击AF（图2）。
并且，对于有机类绝缘膜来说，根据其材料所具有的硬度特性等，是针对冲击AF的缓和性能特别优良的有机类绝缘膜。
此外，缓冲绝缘膜23具有引线22的宽度尺寸以上的宽度尺寸（图1中的纵向的尺寸）。由此，能够抑制接合部分44在宽度方向上从缓冲绝缘膜23上的焊盘部分21p露出。此外，缓冲绝缘膜23具有引线22的宽度尺寸的3倍以下的宽度尺寸。由此，能够防止焊盘部分21p（缓冲绝缘膜23）的宽度尺寸超过作为键合焊盘的必要性而过度地变大。
此外，缓冲绝缘膜23具有与引线22接合的接合部分44的长度的3倍以下的长度（图1中的横向的长度）。由此，能够防止焊盘部分21p（缓冲绝缘膜23）的长度超过作为键合焊盘的必要性而过度地变大。
（实施方式2）
参照图4，代替缓冲绝缘膜23（实施方式1：图1），本实施方式的功率用半导体装置具有缓冲绝缘膜23V。优选缓冲绝缘膜23V与缓冲绝缘膜23同样地具有发射极电极21（在图4中未图示）的面积的二分之一以下的面积。
在缓冲绝缘膜23V上，与实施方式1同样地设置有覆盖缓冲绝缘膜23V的发射极电极21。发射极电极21的缓冲绝缘膜23V之上的部分是焊盘部分，在多个连接部分44a、44b分别连接有引线22（在图4中未图示）。
并且，上述以外的结构与如上所述的实施方式1的结构大致相同，所以，对相同或者对应的要素标注相同的附图标记，不重复其说明。
根据本实施方式，一体地设置有用于多个引线22的焊盘部分。因此，与用于各引线22的焊盘部分分散地设置的情况相比，各焊盘部分的面积变大。因此，能够确保引线22的接合的位置精度并且能够将焊盘部分（缓冲绝缘膜）的面积降低到同等以下，即，能够较大地取得发射极电极的有效面积。
此外，在引线的数目需要很多的情况下，缓冲绝缘膜间的距离变短，所以，在形成了发射极电极21时，存在在缓冲绝缘膜间形成空隙的情况。对于这样的课题，使焊盘部分成为一体，由此，能够防止空隙的产生，使可靠性提高。
此外，缓冲绝缘膜23V的面积为发射极电极21的面积的二分之一以下，由此，发射极电极21被缓冲绝缘膜23V遮挡的部分被限定，所以，关于发射极电极21的有效面积，能够确保充分的大小。因此，能够抑制IGBT的导通电压的上升和饱和电流的下降。
并且，在上述各实施方式中，对IGBT进行了说明，但是，本发明的功率用半导体装置并不限定于此，例如也可以是MOSFET。
应当认为此次公开的各实施方式在所有方面都是例示而不是限制。本发明的范围不是由上述的说明示出而是包括与技术方案等同的意思以及范围内的所有的变更。
产业上的可利用性
本发明能够特别有利地应用于功率用半导体装置。
附图标记说明：
21  发射极电极（电极层）
21p 焊盘部分
21w 布线部分
22  引线
23、23V  缓冲绝缘膜
24  导体部
25  层间绝缘膜
26  栅极电极
27  nE层
28  p+层
30  nB层
31  pB层
32  pC层
33  集电极电极
44、44a、44b  接合部分
SL  半导体层。
权利要求书(按照条约第19条的修改)
1.（修改后）一种功率用半导体装置，其特征在于，具有：
半导体层（SL）；
栅极电极（26），用于对流过所述半导体层（SL）的电流进行控制；
栅极绝缘膜（29），将所述半导体层（SL）以及所述栅极电极（26）彼此电绝缘；
导体部（24），设置在所述半导体层（SL）上，并且与所述半导体层（SL）电连接；
层间绝缘膜（25），以所述导体部（24）与所述栅极电极（26）电绝缘的方式设置在所述栅极电极（26）上；
缓冲绝缘膜（23），覆盖所述导体部（24）以及层间绝缘膜（25）上的一部分区域，并且由绝缘体构成；以及
电极层（21），具有位于所述导体部（24）露出的区域上的布线部分（21w）和位于所述缓冲绝缘膜（23）上的焊盘部分（21p），
在平面图中与所述沟槽栅极延伸的方向平行的所述缓冲绝缘膜（23）的端部位于所述层间绝缘膜（25）上。
2.如权利要求1所述的功率用半导体装置，其特点在于，
所述栅极电极（26）是沟槽栅极。
3.（删除）。
4.如权利要求1所述的功率用半导体装置，其特征在于，
所述缓冲绝缘膜(23)具有所述电极层（21）的所述焊盘部分（21p）的厚度的五分之一以上并且五分之四以下的厚度。
5.如权利要求1所述的功率用半导体装置，其特征在于，
所述缓冲绝缘膜（23）具有所述电极层（21）的面积的二分之一以下的面积。
6.如权利要求1所述的功率用半导体装置，其特征在于，
所述缓冲绝缘膜（23）是TEOS膜、SOG膜、有机类绝缘膜的任意一种。
7.如权利要求1所述的功率用半导体装置，其特征在于，
还具有与所述电极层（21）的所述焊盘部分（21p）接合的引线（22），
所述焊盘部分（21p）具有所述引线（22）的宽度尺寸以上并且所述引线（22）的宽度尺寸的3倍以下的宽度尺寸。
8.如权利要求1所述的功率用半导体装置，其特征在于，
还具有与所述电极层（21）的所述焊盘部分（21p）接合的引线（22），
所述焊盘部分（21p）具有所述焊盘部分（21p）的与所述引线（22）接合的部分（44）的长度的3倍以下的长度。

Claims (8)

1.一种功率用半导体装置，其特征在于，具有：
半导体层（SL）；
栅极电极（26），用于对流过所述半导体层（SL）的电流进行控制；
栅极绝缘膜（29），将所述半导体层（SL）以及所述栅极电极（26）彼此电绝缘；
导体部（24），设置在所述半导体层（SL）上，并且与所述半导体层（SL）电连接；
层间绝缘膜（25），以所述导体部（24）与所述栅极电极（26）电绝缘的方式设置在所述栅极电极（26）上；
缓冲绝缘膜（23），覆盖所述导体部（24）以及层间绝缘膜（25）上的一部分区域，并且由绝缘体构成；以及
电极层（21），具有位于所述导体部（24）露出的区域上的布线部分（21w）和位于所述缓冲绝缘膜（23）上的焊盘部分（21p）。
2.如权利要求1所述的功率用半导体装置，其特点在于，
所述栅极电极（26）是沟槽栅极。
3.如权利要求2所述的功率用半导体装置，其特征在于，
在平面图中与所述沟槽栅极延伸的方向平行的所述缓冲绝缘膜（23）的端部位于所述层间绝缘膜（25）上。
4.如权利要求1所述的功率用半导体装置，其特征在于，
所述缓冲绝缘膜(23)具有所述电极层（21）的所述焊盘部分（21p）的厚度的五分之一以上并且五分之四以下的厚度。
5.如权利要求1所述的功率用半导体装置，其特征在于，
所述缓冲绝缘膜（23）具有所述电极层（21）的面积的二分之一以下的面积。
6.如权利要求1所述的功率用半导体装置，其特征在于，
所述缓冲绝缘膜（23）是TEOS膜、SOG膜、有机类绝缘膜的任意一种。
7.如权利要求1所述的功率用半导体装置，其特征在于，
还具有与所述电极层（21）的所述焊盘部分（21p）接合的引线（22），
所述焊盘部分（21p）具有所述引线（22）的宽度尺寸以上并且所述引线（22）的宽度尺寸的3倍以下的宽度尺寸。
8.如权利要求1所述的功率用半导体装置，其特征在于，
还具有与所述电极层（21）的所述焊盘部分（21p）接合的引线（22），
所述焊盘部分（21p）具有所述焊盘部分（21p）的与所述引线（22）接合的部分（44）的长度的3倍以下的长度。
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