WO2010125639A1 - 電力用半導体装置 - Google Patents

電力用半導体装置 Download PDF

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Publication number
WO2010125639A1
WO2010125639A1 PCT/JP2009/058320 JP2009058320W WO2010125639A1 WO 2010125639 A1 WO2010125639 A1 WO 2010125639A1 JP 2009058320 W JP2009058320 W JP 2009058320W WO 2010125639 A1 WO2010125639 A1 WO 2010125639A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
layer
pad portion
buffer insulating
gate electrode
Prior art date
Application number
PCT/JP2009/058320
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English (en)
French (fr)
Other versions
WO2010125639A9 (ja
Inventor
和成 中田
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to KR1020117025155A priority Critical patent/KR20120008511A/ko
Priority to DE112009004978.8T priority patent/DE112009004978B4/de
Priority to PCT/JP2009/058320 priority patent/WO2010125639A1/ja
Priority to JP2011511209A priority patent/JP5599388B2/ja
Priority to US13/148,326 priority patent/US8450796B2/en
Priority to CN200980159009.4A priority patent/CN102414825B/zh
Publication of WO2010125639A1 publication Critical patent/WO2010125639A1/ja
Publication of WO2010125639A9 publication Critical patent/WO2010125639A9/ja

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance

Definitions

  • the present invention relates to a power semiconductor device.
  • Power semiconductor devices are mainly used to handle relatively large electric power of several hundred kilowatts to several megawatts in inverter circuits such as industrial motors and motor for motor vehicles, power supplies of large capacity servers, uninterruptible power supplies, etc. May be Examples of the power semiconductor device include semiconductor switches such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Insulated Gate Bipolar Transistor). Conventionally, a planar gate type has been widely used as an IGBT, but in recent years, a vertical IGBT using a trench gate capable of high integration has come to be used.
  • MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • the power semiconductor device (power semiconductor device) is formed of an emitter plug and an emitter plug. And an emitter pad connected to the emitter plug.
  • the pads as described above are electrically connected, for example, by wire bonding.
  • the transistor may be damaged by an impact applied to a portion immediately below the pad. This is largely due to the miniaturization of each part size (interval, size, film thickness, etc.) as the degree of integration increases.
  • a plurality of conductive layer wiring metals and interlayer insulating films are alternately stacked directly under the pad, and adjacent to each other with the interlayer insulating film interposed therebetween.
  • the present invention has been made to solve the above-mentioned problems, and the object thereof is to handle a large amount of power and to suppress the damage caused by the electrical connection to the pad. It is providing a semiconductor device.
  • the power semiconductor device of the present invention includes a semiconductor layer, a gate electrode, a gate insulating film, a conductor portion, an interlayer insulating film, a buffer insulating film, and an electrode layer.
  • the gate electrode is for controlling the current flowing through the semiconductor layer.
  • the gate insulating film electrically insulates the semiconductor layer and the gate electrode from each other.
  • the conductor portion is provided on the semiconductor layer and is electrically connected to the semiconductor layer.
  • the interlayer insulating film is provided on the gate electrode so that the conductor portion is electrically insulated from the gate electrode.
  • the buffer insulating film covers a conductor region and a partial region on the interlayer insulating film, and is made of an insulator.
  • the electrode layer has a wiring portion located above the region where the conductor portion is exposed, and a pad portion located above the buffer insulating film.
  • the pad portion is located on the buffer insulating film. Therefore, the shock applied to the semiconductor layer when the electrical connection is made to the pad portion is mitigated by the buffer insulating film. Therefore, damage to the power semiconductor device can be suppressed. Also, a short current path that connects the semiconductor layer directly below the pad portion and the pad portion linearly is interrupted by the buffer insulating film. Thus, current concentration immediately below the pad portion can be prevented. As a result, destruction of the power semiconductor device due to current concentration can be prevented, and therefore, larger power can be handled.
  • FIG. 1 is a partial plan view schematically showing a configuration of a power semiconductor device in a first embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG. It is a graph which shows an example of the relationship on the acceleration conditions of the defect rate generate
  • FIG. 10 is a partial plan view schematically showing a configuration of a power semiconductor device in a second embodiment of the present invention.
  • the IGBT as the power semiconductor device of the present embodiment includes semiconductor layer SL, gate electrode 26, gate insulating film 29, conductor portion 24, and interlayer insulating film 25.
  • the semiconductor layer SL as a semiconductor portion of the IGBT, n E layer 27 as an emitter, p + layer 28 for obtaining ohmic contact, n B layer 30 called such a base, p B layer 31, and a collector p C It has a layer 32.
  • the n E layer 27 and the n B layer 30 are n-type semiconductor layers
  • the p + layer 28, the p B layer 31 and the p C layer 32 are p-type semiconductor layers
  • the semiconductor layer is a silicon layer.
  • the semiconductor layer SL extends along one direction (longitudinal direction in FIG. 1), and has a plurality of trenches spaced apart from one another in a direction (horizontal direction in FIGS. 1 and 2) orthogonal to this direction. Have. Each trench faces the n E layer 27, the p B layer 31 and the n B layer 30. That is, the trenches are formed in stripes in the semiconductor layer.
  • the gate electrode 26 serves as a gate electrode of the IGBT to control the current flowing through the semiconductor layer SL in the thickness direction (vertical direction in FIG. 2). That is, the power semiconductor device of the present embodiment is a vertical IGBT.
  • the gate electrode 26 is formed by burying, for example, polycrystalline silicon in a trench formed in the semiconductor layer SL, and is a so-called trench gate.
  • Gate insulating film 29 is made of a thin silicon oxide film or the like, and electrically insulates semiconductor layer SL and gate electrode 26 from each other.
  • the conductor portion 24 is provided on the semiconductor layer SL and electrically connected to the n E layer 27 and the p + layer 28 of the semiconductor layer SL, while the gate is electrically insulated from the gate electrode 26.
  • An interlayer insulating film 25 is provided on the electrode 26.
  • the conductor portion 24 is formed of, for example, a tungsten material, which is larger than the conductivity of the gate electrode 26.
  • the interlayer insulating film 25 is formed of, for example, a silicon oxide film (hereinafter referred to as a TEOS film) using TEOS (tetraethylorthosilicate) which is an organic material.
  • the conductor portion 24 is a so-called contact (plug) provided in the interlayer insulating film 25 and electrically connects the semiconductor layer SL and the emitter electrode 21.
  • Buffer insulating film 23 covers a partial region on conductor portion 24 and interlayer insulating film 25 as shown in FIG. Therefore, as shown in FIG. 2, buffer insulating film 23 includes a portion located on gate electrode 26 with interlayer insulating film 25 interposed therebetween. In this case, the end portions (both left and right ends in FIG. 1) of buffer insulating film 23 parallel to the direction in which the trench extends in plan view are located not on conductor portion 24 but on interlayer insulating film 25.
  • the buffer insulating film 23 is a film made of an insulator, and is, for example, a TEOS film, an SOG (spin on glass) film, or an organic insulating film similar to the interlayer insulating film 25. For example, a polyimide film can be used as the organic insulating film.
  • Emitter electrode 21 is formed of, for example, aluminum, and pad portion 21 p located on buffer insulating film 23, and a wire located on conductor portion 24 and interlayer insulating film 25 so as to surround pad portion 21 p in plan view. And a portion 21w.
  • the pad portion 21p is used as a bonding pad. That is, the pad portion 21p is a portion for bonding the wire 22.
  • the wiring portion 21 w is not covered by the buffer insulating film 23 and is located on the exposed portion of the conductor portion 24 and the interlayer insulating film 25 (other than the partial region on the conductor portion 24 and the interlayer insulating film 25). Therefore, the wiring portion 21 w has a direct electrical connection with the conductor portion 24 directly below it, and is electrically connected with the pad portion 21 p insulated from the conductor portion 24 directly below.
  • the wire 22 is bonded to the pad portion 21 p of the emitter electrode 21 at the bonding portion 44.
  • the wire 22 is, for example, an aluminum wire to which an ultrasonic wire bonding method is applied.
  • the film thickness thereof has a thickness of 1 ⁇ 5 to 4 ⁇ 5 of the thickness of the pad portion 21p of the emitter electrode 21.
  • the width of the buffer insulating film 23 With regard to the width of the buffer insulating film 23, the width (diameter) dimension of the wire 22 or more and 3 times or less the width dimension (dimension in the vertical direction in FIG. 1) and the length of the bonding portion 44 joined to the wire 22 As described above, the length is 3 times or less (the length in the horizontal direction in FIG. 1).
  • the total area (total area) of the buffer insulating films 23 is not more than half the area of the emitter electrode 21. Have an area of
  • pad portion 21 p as a bonding pad is located on buffer insulating film 23. Therefore, the shock AF applied to the semiconductor layer SL at the time of bonding is alleviated by the buffer insulating film 23, so that damage to the IGBT when the wire 22 is connected to the pad portion 21p can be suppressed.
  • Buffer insulating film 23 includes a portion located on gate electrode 26 with interlayer insulating film 25 interposed therebetween. Thus, the gate electrode 26 is protected by the buffer insulating film 23 from the impact AF.
  • the wire bonding of the wire 22 can be performed under stronger conditions. Specifically, for example, wire bonding can be performed using stronger ultrasonic waves or stronger loads. As a result, the bonding strength and bonding area at the bonding portion 44 between the wire 22 and the pad portion 21p can be increased. Thus, the critical life, ie, the power cycle life, in which the bonding portion 44 eventually peels off due to the temperature cycle can be lengthened. Thereby, larger power can be handled while securing a sufficient life.
  • the gate electrode 26 is a trench gate as in the present embodiment
  • a crack is easily generated between the gate electrode 26 and the nE layer 27.
  • the breakdown voltage may be reduced or a short circuit may occur between the gate electrode 26 and the nE layer 27.
  • the shock absorbing AF is mitigated by the buffer insulating film 23, it is possible to suppress the occurrence of the crack as described above.
  • a short current path AI for linearly connecting the p + layer 28 immediately below the pad portion 21p and the pad portion 21p is formed by the buffer insulating film 23. It is cut off.
  • current concentration immediately below the pad portion 21p where the bonding portion 44 of the wire 22 is located can be prevented, so that breakage due to this current concentration can be prevented. Therefore, a larger amount of power can be handled while preventing the occurrence of destruction due to current concentration.
  • the conductivity of the conductor portion 24 is larger than the conductivity of the gate electrode 26.
  • the conductor portion 24 with high conductivity can reduce the voltage drop depending on the length of the electrical path to the pad portion 21 p in each of the n E layer 27 and the p + layer 28. As a result, the entire IGBT can be operated more evenly, so that a larger amount of power can be handled.
  • the buffer insulating film 23 has a thickness not less than one fifth and not more than four fifths of the thickness of the pad portion 21 p of the emitter electrode 21.
  • the defect rate of the power semiconductor device can be reduced.
  • this verification experiment was conducted, as shown in FIG. 3, the wire 22 to the pad portion 21p with respect to the film thickness ratio RT (horizontal axis) between the thickness of the pad portion 21p of the emitter electrode 21 and the thickness of the buffer insulating film 23 The relationship of defect rate DR in connection was confirmed.
  • the film thickness ratio RT of the buffer insulating film 23 is 0.2 or more and 0.8 or less (5 or more and 4 or less). As a result, the defect rate DR was significantly reduced.
  • the buffer insulating film 23 When the film thickness ratio RT of the buffer insulating film 23 is less than 0.2, the buffer insulating film 23 is easily damaged by impact AF (FIG. 2) at the time of wire bonding, further the gate electrode 26 and the n E layer It is considered that damage occurs such that a short circuit occurs with 27 and the defect rate DR increases.
  • the film thickness RT of the buffer insulating film 23 is more than 0.8, the step at the boundary between the pad portion 21p and the wiring portion 21w in the emitter electrode 21 becomes excessively large, and disconnection occurs at this step. It is thought that the rate DR has risen.
  • Buffer insulating film 23 has an area equal to or less than half the area of emitter electrode 21. As a result, the portion in which the emitter electrode 21 is interrupted by the buffer insulating film 23 is limited, so that the effective area of the emitter electrode 21 is secured to a sufficient size. Therefore, it is possible to suppress an increase in the on voltage of the IGBT and a decrease in the saturation current.
  • the buffer insulating film 23 is formed of a TEOS film, an SOG film, an organic insulating film (polyimide film) or the like using an organic material. Thereby, the buffer insulating film 23 can be formed at a low temperature as compared with the case where the buffer insulating film 23 is made of an inorganic material (such as silane). Therefore, the impurity profile in the semiconductor layer SL can be controlled with higher accuracy without re-diffusion of the impurity in the semiconductor layer SL. Further, since the thick buffer insulating film 23 can be easily formed, the impact AF (FIG. 2) can be alleviated.
  • the organic insulating film has particularly excellent alleviation performance against impact AF due to the hardness characteristics of the material.
  • Buffer insulating film 23 has a width dimension (dimension in the vertical direction in FIG. 1) equal to or greater than the width dimension of wire 22.
  • the buffer insulating film 23 has a width that is not more than three times the width of the wire 22. As a result, it is possible to prevent the width dimension of the pad portion 21p (buffer insulating film 23) from becoming excessively large beyond the necessity as a bonding pad.
  • the buffer insulating film 23 has a length (three times or less in FIG. 1) longer than the length of the bonding portion 44 bonded to the wire 22. As a result, it is possible to prevent the length of the pad portion 21p (buffer insulating film 23) from becoming excessively large beyond the necessity as a bonding pad.
  • the power semiconductor device of the present embodiment has buffer insulating film 23V instead of buffer insulating film 23 (first embodiment: FIG. 1).
  • buffer insulating film 23V has an area equal to or less than a half of the area of emitter electrode 21 (not shown in FIG. 4), similarly to buffer insulating film 23.
  • an emitter electrode 21 covering the buffer insulating film 23V is provided on the buffer insulating film 23V.
  • a portion of the emitter electrode 21 above the buffer insulating film 23V is a pad portion, and a wire 22 (not shown in FIG. 4) is connected to each of the plurality of connection portions 44a and 44b.
  • the pad portions for the plurality of wires 22 are integrally provided. Therefore, the area of each pad portion is larger than when the pad portions for each wire 22 are provided in a distributed manner. Therefore, the area of the pad portion (buffer insulating film) can be reduced to the same level or less while securing the positional accuracy of the bonding of the wire 22, that is, the effective area of the emitter electrode can be increased.
  • the distance between the buffer insulating films becomes short, so that when the emitter electrode 21 is formed, a gap may be formed between the buffer insulating films.
  • a gap may be formed between the buffer insulating films.
  • the area of the buffer insulating film 23V is not more than half the area of the emitter electrode 21, the portion where the emitter electrode 21 is interrupted by the buffer insulating film 23V is limited. A sufficient size will be secured for the area. Therefore, it is possible to suppress an increase in the on voltage of the IGBT and a decrease in the saturation current.
  • the power semiconductor device of the present invention is not limited to this, and may be, for example, a MOSFET.
  • the present invention can be applied particularly advantageously to power semiconductor devices.

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Abstract

　ゲート電極（２６）は、半導体層（ＳＬ）を流れる電流を制御するためのものである。ゲート絶縁膜（２９）は、半導体層（ＳＬ）およびゲート電極（２６）を互いに電気的に絶縁している。導体部（２４）は、半導体層（ＳＬ）の上に設けられ、かつ半導体層（ＳＬ）と電気的に接続されている。層間絶縁膜（２５）は、導体部（２４）がゲート電極（２６）と電気的に絶縁されるように、ゲート電極（２６）の上に設けられている。緩衝絶縁膜（２３）は、導体部（２４）および層間絶縁膜（２５）上の一部領域を覆い、かつ絶縁体からなる。電極層（２１）は、導体部（２４）が露出する領域の上に位置する配線部分（２１ｗ）と、緩衝絶縁膜（２３）の上に位置するパッド部分（２１ｐ）とを有する。これにより、パッド部分（２１ｐ）にワイヤ（２２）が接続される際のＩＧＢＴへのダメージを抑制することができる。また、電流集中による破壊の発生を防止しつつ、より大きな電力を扱うことができる。

Description

電力用半導体装置
　本発明は、電力用半導体装置に関するものである。
　産業用モータや自動車用モータなどのインバータ回路、大容量サーバの電源装置、および無停電電源装置などにおいて、主として数百キロワットから数メガワットまでの比較的大きな電力を取り扱うための電力用半導体装置が用いられることがある。この電力用半導体装置としては、たとえばＭＯＳＦＥＴ(Metal-Oxide-Semiconductor　Field-Effect　Transistor)およびＩＧＢＴ(Insulated　Gate　Bipolar　Transistor)などの半導体スイッチがある。ＩＧＢＴとしては、従来は平面ゲート型のものが広く用いられていたが、近年は高集積化が可能なトレンチゲートを用いた縦型のＩＧＢＴが使われるようになってきている。
　このようなトレンチゲートを用いたＩＧＢＴが扱える電流をより大きくするため、たとえば特開２００７－２７３９３１号公報（特許文献１）によれば、電力用半導体素子（電力用半導体装置）は、エミッタプラグと、このエミッタプラグに接続されたエミッタパッドとを有する。
　上記のようなパッドには、たとえばワイヤボンディングによって電気的接続が行なわれる。この際にパッド直下の部分が受ける衝撃によってトランジスタにダメージが与えられることがある。これは高集積化に伴って、各部位サイズ（間隔や大きさ、膜厚など）の微細化に因るところが大きい。このようなダメージを抑制するため、たとえば特開２００６－３２４２６５号公報によれば、半導体装置は、パッド直下に導電層配線メタルと層間絶縁膜が交互に複数積層され、層間絶縁膜を挟んで隣り合う導電層配線メタルがビアを介して接続され、積層された層が層間絶縁膜の材料が異なる複数のファイン層に分割され、材料の異なる層間絶縁膜間の界面の上層に形成された層間絶縁膜に形成されたビアの径が他のビアの径より太いことを特徴とする。
特開２００７－２７３９３１号公報 特開２００６－３２４２６５号公報
　上記特開２００７－２７３９３１号公報の技術によれば、上述したように、パッドへの電気的接続の際に電力用半導体装置にダメージが与えられることがあるという問題がある。
　また上記特開２００６－３２４２６５号公報の技術によれば、互いに径の異なる複数のビアを介して電気的接続が行なわれる。このため製造工程において必要なパターニング回数が多くなるので、パターン欠陥やパターンばらつきが生じやすい。この結果、電力用半導体装置の通電能力にばらつきが生じやすい。特に、小さい径を有するビアの断面積がばらつくことで、この通電能力は大きくばらついてしまう。よって、大きな電力を扱う電力用半導体装置を安定的に得ることが困難であるという問題がある。
　本発明は上記のような問題を解決するためになされたものであって、その目的は、大きな電力を扱うことができ、かつパッドへの電気的接続により生じるダメージを抑制することができる電力用半導体装置を提供することである。
　本発明の電力用半導体装置は、半導体層と、ゲート電極と、ゲート絶縁膜と、導体部と、層間絶縁膜と、緩衝絶縁膜と、電極層とを有する。ゲート電極は、半導体層を流れる電流を制御するためのものである。ゲート絶縁膜は、半導体層およびゲート電極を互いに電気的に絶縁している。導体部は、半導体層の上に設けられ、かつ半導体層と電気的に接続されている。層間絶縁膜は、導体部がゲート電極と電気的に絶縁されるように、ゲート電極の上に設けられている。緩衝絶縁膜は、導体部および層間絶縁膜上の一部領域を覆い、かつ絶縁体からなる。電極層は、導体部が露出する領域の上に位置する配線部分と、緩衝絶縁膜の上に位置するパッド部分とを有する。
　本発明の電力用半導体装置によればパッド部分は緩衝絶縁膜の上に位置する。よってパッド部分に電気的接続が行なわれる際に半導体層に加わる衝撃が緩衝絶縁膜によって緩和される。このため電力用半導体装置へのダメージを抑制することができる。またパッド部分の直下の半導体層とパッド部分との間を直線的に結ぶような短い電流経路は、緩衝絶縁膜によって遮断される。よってパッド部分の直下における電流集中を防止することができる。このため電流集中による電力用半導体装置の破壊が防止されるので、より大きな電力を扱うことができる。
本発明の実施の形態１における電力用半導体装置の構成を概略的に示す部分平面図である。 図１の線ＩＩ－ＩＩに沿う概略断面図である。 本発明の実施の形態１における電力用半導体装置のパッド部分への電気的接続により発生する不良率と、緩衝絶縁膜の厚さとの加速条件下における関係の一例を示すグラフである。 本発明の実施の形態２における電力用半導体装置の構成を概略的に示す部分平面図である。
　以下、本発明の実施の形態について図に基づいて説明する。なお部分平面図（図１および図４）において、エミッタ電極（電極層）およびワイヤは図示されておらず、また図を見やすくするために導体部および層間絶縁膜にハッチングが付されている。
　（実施の形態１）
　図１および図２を参照して、本実施の形態の電力用半導体装置としてのＩＧＢＴは、半導体層ＳＬと、ゲート電極２６と、ゲート絶縁膜２９と、導体部２４と、層間絶縁膜２５と、緩衝絶縁膜２３と、エミッタ電極２１（電極層）と、コレクタ電極３３と、ワイヤ２２とを有する。
　半導体層ＳＬは、ＩＧＢＴの半導体部分として、エミッタとなるｎE層２７、オーミックコンタクトを得るためのｐ+層２８、ベースなどと呼ばれるｎB層３０、ｐB層３１、およびコレクタとなるｐC層３２を有する。ｎE層２７およびｎB層３０はｎ型の半導体層であり、ｐ+層２８、ｐB層３１およびｐC層３２はｐ型の半導体層であり、半導体層はシリコン層である。また半導体層ＳＬは、一の方向（図１における縦方向）に沿って延び、この方向に直交する方向（図１および図２における横方向）において互いに間隔を空けて配置された複数のトレンチを有する。各トレンチは、ｎE層２７、ｐB層３１およびｎB層３０に面している。つまり、トレンチは半導体層中にストライプ状に形成されている。
　ゲート電極２６は、ＩＧＢＴのゲート電極として、半導体層ＳＬを厚さ方向（図２における縦方向）に流れる電流を制御するためのものである。すなわち本実施の形態の電力用半導体装置は縦型ＩＧＢＴである。またゲート電極２６は、半導体層ＳＬに形成されたトレンチにたとえば多結晶シリコンが埋め込まれることで形成されており、いわゆるトレンチゲートである。ゲート絶縁膜２９は、薄いシリコン酸化膜などからなり半導体層ＳＬおよびゲート電極２６を互いに電気的に絶縁している。
　導体部２４は、半導体層ＳＬの上に設けられて半導体層ＳＬのｎE層２７およびｐ+層２８と電気的に接続され、一方、ゲート電極２６とは電気的に絶縁されるようにゲート電極２６上には層間絶縁膜２５が設けられている。そして導体部２４は、ゲート電極２６の導電率よりも大きい、たとえばタングステン材料で形成されている。また層間絶縁膜２５は、たとえば有機系の材料であるＴＥＯＳ(tetraethylorthosilicate)を用いたシリコン酸化膜（以降、ＴＥＯＳ膜と称す）で形成されている。導体部２４は、層間絶縁膜２５に設けられたいわゆるコンタクト(プラグ）であって、半導体層ＳＬとエミッタ電極２１とを電気的に接続している。
　緩衝絶縁膜２３は、図１に示すように、導体部２４および層間絶縁膜２５の上の一部領域を覆っている。よって緩衝絶縁膜２３は、図２に示すように、層間絶縁膜２５を介してゲート電極２６上に位置する部分を含む。なお、この場合、平面視においてトレンチが延びる方向に平行な緩衝絶縁膜２３の端部（図１における左右両端）は、導体部２４上ではなく、層間絶縁膜２５上に位置していることが好ましい。また緩衝絶縁膜２３は、絶縁体からなる膜であり、たとえば、層間絶縁膜２５と同様のＴＥＯＳ膜、ＳＯＧ（spin on glass）膜、または有機系絶縁膜である。有機系絶縁膜としては、たとえばポリイミド膜を用いることができる。
　エミッタ電極２１は、たとえばアルミニウムで形成され、緩衝絶縁膜２３の上に位置するパッド部分２１ｐと、このパッド部分２１ｐを平面視において取り囲むように導体部２４および層間絶縁膜２５の上に位置する配線部分２１ｗとを有する。
　パッド部分２１ｐは、ボンディングパッドとして使用する。すなわちパッド部分２１ｐはワイヤ２２がボンディングされるための部分である。
　配線部分２１ｗは、緩衝絶縁膜２３によって覆われず導体部２４および層間絶縁膜２５が露出されている部分（導体部２４および層間絶縁膜２５上の上記一部領域以外）の上に位置する。よって配線部分２１ｗは、その直下において導体部２４との直接的な電気的接続を備え、その直下においては導体部２４と絶縁されているパッド部分２１ｐと電気的に接続している。
　ワイヤ２２は接合部分４４においてエミッタ電極２１のパッド部分２１ｐに接合されている。ワイヤ２２は、たとえば、超音波によるワイヤボンディング法が適用されるアルミニウムワイヤである。
　パッド部分２１ｐに対応する好ましい緩衝絶縁膜２３の各部寸法として、まずその膜厚は、エミッタ電極２１のパッド部分２１ｐの厚さの５分の１以上かつ５分の４以下の厚さを有する。
　そして緩衝絶縁膜２３の広さについては、ワイヤ２２の幅（径）寸法以上、３倍以下の幅寸法（図１における縦方向の寸法）と、ワイヤ２２に接合される接合部分４４の長さ以上、３倍以下の長さ（図１における横方向の長さ）とを有する。また複数個のワイヤ２２に対応して複数個の緩衝絶縁膜２３を備える場合にあっては、緩衝絶縁膜２３の面積の合計（総面積）が、エミッタ電極２１の面積の２分の１以下の面積を有する。
　本実施の形態によれば、図２に示すように、ボンディングパッドとしてのパッド部分２１ｐは緩衝絶縁膜２３の上に位置する。よってボンディングの際に半導体層ＳＬに加わる衝撃ＡＦが緩衝絶縁膜２３によって緩和されるので、パッド部分２１ｐにワイヤ２２が接続される際のＩＧＢＴへのダメージを抑制することができる。
　また緩衝絶縁膜２３は層間絶縁膜２５を介してゲート電極２６上に位置する部分を含む。よってゲート電極２６は衝撃ＡＦから緩衝絶縁膜２３によって保護される。
　また上記のようにワイヤ２２の接続によるダメージが抑制されるので、ワイヤ２２のワイヤボンディングをより強い条件で行なうことができる。具体的には、たとえば、より強い超音波またはより強い荷重を用いてワイヤボンディングを行なうことができる。これによりワイヤ２２とパッド部分２１ｐとの接合部分４４における接合強度および接合面積を大きくすることができる。よって接合部分４４が温度サイクルによって最終的に剥離する限界寿命、すなわちパワーサイクル寿命を長くすることができる。これにより、十分な寿命を確保しつつ、より大きな電力を扱うことができる。
　特に、本実施の形態のようにゲート電極２６がトレンチゲートである場合、仮に大きな衝撃ＡＦがトレンチ近傍に加わると、ゲート電極２６とｎE層２７との間にクラックが生じやすい。このようなクラックが生じると、ゲート電極２６とｎE層２７との間で、耐圧が低下したり、あるいは短絡が生じたりし得る。しかし本実施の形態によれば緩衝絶縁膜２３によって衝撃ＡＦが緩和されるので、上記のようなクラックの発生を抑制することができる。
　また本実施の形態によれば、図２に示すように、パッド部分２１ｐの直下のｐ+層２８とパッド部分２１ｐとの間を直線的に結ぶような短い電流経路ＡＩが緩衝絶縁膜２３によって遮断される。よってワイヤ２２の接合部分４４が位置するパッド部分２１ｐの直下における電流集中を防止することができるので、この電流集中による破壊が防止される。よって電流集中よる破壊の発生を防止しつつ、より大きな電力を扱うことができる。
　また導体部２４の導電率は、ゲート電極２６の導電率よりも大きい。この導電率の大きい導体部２４によって、ｎE層２７およびｐ+層２８の各々において、パッド部分２１ｐまでの電気的経路の長さに依存する電圧降下を低減することができる。これによりＩＧＢＴ全体をよりむらなく動作させることができるので、より大きな電力を扱うことができる。
　また緩衝絶縁膜２３はエミッタ電極２１のパッド部分２１ｐの厚さの５分の１以上かつ５分の４以下の厚さを有する。緩衝絶縁膜２３の厚さがこのような条件を満たす場合、電力用半導体装置の不良率を低減することができる。この検証実験を行なったところ、図３に示すように、エミッタ電極２１のパッド部分２１ｐの厚さと緩衝絶縁膜２３の厚さとの膜厚比ＲＴ（横軸）に対するパッド部分２１ｐへのワイヤ２２の接続の際の不良率ＤＲの関係が確認された。すなわち、エミッタ電極２１のパッド部分２１ｐの厚さを１とした場合の緩衝絶縁膜２３の膜厚比ＲＴが０．２以上０．８以下（５分の１以上５分の４以下）であることにより、不良率ＤＲが顕著に低減された。
　なお緩衝絶縁膜２３の膜厚比ＲＴが０．２未満の場合、ワイヤボンディングの際の衝撃ＡＦ（図２）によって緩衝絶縁膜２３が容易に損傷することで、さらにゲート電極２６とｎE層２７との間に短絡が生じるようなダメージが発生し、不良率ＤＲが上昇したと考えられる。また緩衝絶縁膜２３の膜厚ＲＴが０．８超の場合、エミッタ電極２１におけるパッド部分２１ｐと配線部分２１ｗとの境界における段差が過度に大きくなり、この段差部分おいて断線が生じることで不良率ＤＲが上昇したと考えられる。
　また緩衝絶縁膜２３は、エミッタ電極２１の面積の２分の１以下の面積を有する。これによりエミッタ電極２１が緩衝絶縁膜２３に遮られる部分が限定されることになるので、エミッタ電極２１の有効面積については十分な大きさが確保されることになる。よってＩＧＢＴのオン電圧の上昇と飽和電流の低下とを抑制することができる。
　また緩衝絶縁膜２３は有機系の材料を使ったＴＥＯＳ膜やＳＯＧ膜、有機系絶縁膜（ポリイミド膜）などからなる。これにより緩衝絶縁膜２３が無機系の材料（シランなど）からなる場合に比して緩衝絶縁膜２３を低温で形成することができる。よって半導体層ＳＬ中の不純物が再拡散することもなく、不純物プロファイルをより高い精度で制御することができる。また厚さの大きい緩衝絶縁膜２３を容易に形成することができるので、衝撃ＡＦ（図２）を緩和することができる。
　なお有機系絶縁膜は、その材料がもつ硬度特性などから、衝撃ＡＦに対する緩和性能が特に優れたものとなる。
　また緩衝絶縁膜２３は、ワイヤ２２の幅寸法以上の幅寸法（図１における縦方向の寸法）を有する。これにより、緩衝絶縁膜２３上のパッド部分２１ｐから接合部分４４が幅方向においてはみ出すことを抑制することができる。また緩衝絶縁膜２３は、ワイヤ２２の幅寸法の３倍以下の幅寸法を有する。これによりパッド部分２１ｐ（緩衝絶縁膜２３）の幅寸法がボンディングパッドとしての必要性を超えて過度に大きくなることを防止することができる。
　また緩衝絶縁膜２３は、ワイヤ２２に接合される接合部分４４の長さの３倍以下の長さ（図１における横方向の長さ）を有する。これによりパッド部分２１ｐ（緩衝絶縁膜２３）の長さがボンディングパッドとしての必要性を超えて過度に大きくなることを防止することができる。
　（実施の形態２）
　図４を参照して、本実施の形態の電力用半導体装置は、緩衝絶縁膜２３（実施の形態１：図１）の代わりに緩衝絶縁膜２３Ｖを有する。好ましくは、緩衝絶縁膜２３Ｖは、緩衝絶縁膜２３と同様に、エミッタ電極２１（図４において図示せず）の面積の２分の１以下の面積を有する。
　緩衝絶縁膜２３Ｖの上には、実施の形態１と同様に緩衝絶縁膜２３Ｖを覆うエミッタ電極２１が設けられている。エミッタ電極２１のうち緩衝絶縁膜２３Ｖの上の部分がパッド部分であり、複数の接続部分４４ａ、４４ｂの各々においてワイヤ２２（図４において図示せず）が接続されている。
　なお、上記以外の構成については、上述した実施の形態１の構成とほぼ同じであるため、同一または対応する要素について同一の符号を付し、その説明を繰り返さない。
　本実施の形態によれば、複数のワイヤ２２のためのパッド部分が一体に設けられている。よって各ワイヤ２２のためのパッド部分が分散されて設けられる場合に比して、各パッド部分の面積が大きくなる。よってワイヤ２２の接合の位置精度を確保しつつ、パッド部分（緩衝絶縁膜）の面積を同等以下に下げることができ、すなわち、エミッタ電極の有効面積を大きくとることができる。
　また、ワイヤの数が多数必要な場合には、緩衝絶縁膜間の距離が短くなるため、エミッタ電極２１を形成した際、緩衝絶縁膜間に空隙ができることがある。このような課題に対しても、パッド部分を一体にすることで、空隙の発生を防止し信頼性を向上させることができる。
　また緩衝絶縁膜２３Ｖの面積がエミッタ電極２１の面積の２分の１以下であることにより、エミッタ電極２１が緩衝絶縁膜２３Ｖに遮られる部分が限定されることになるので、エミッタ電極２１の有効面積については十分な大きさが確保されることになる。よってＩＧＢＴのオン電圧の上昇と飽和電流の低下とを抑制することができる。
　なお上記の各実施の形態においてはＩＧＢＴについて説明したが、本発明の電力用半導体装置はこれに限定されるものではなく、たとえばＭＯＳＦＥＴであってもよい。
　今回開示された各実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなくて請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。
　本発明は、電力用半導体装置に特に有利に適用され得る。
　２１　エミッタ電極（電極層）、２１ｐ　パッド部分、２１ｗ　配線部分、２２　ワイヤ、２３，２３Ｖ　緩衝絶縁膜、２４　導体部、２５　層間絶縁膜、２６　ゲート電極、２７　ｎE層、２８　ｐ+層、３０　ｎB層、３１　ｐB層、３２　ｐC層、３３　コレクタ電極、４４，４４ａ，４４ｂ　接合部分、ＳＬ　半導体層。

Claims (8)

  1. 　半導体層（ＳＬ）と、
    　前記半導体層（ＳＬ）を流れる電流を制御するためのゲート電極（２６）と、
    　前記半導体層（ＳＬ）および前記ゲート電極（２６）を互いに電気的に絶縁するゲート絶縁膜（２９）と、
    　前記半導体層（ＳＬ）の上に設けられ、かつ前記半導体層（ＳＬ）と電気的に接続された導体部（２４）と、
    　前記導体部（２４）が前記ゲート電極（２６）と電気的に絶縁されるように、前記ゲート電極（２６）の上に設けられた層間絶縁膜（２５）と、
    　前記導体部（２４）および層間絶縁膜（２５）上の一部領域を覆い、かつ絶縁体からなる緩衝絶縁膜（２３）と、
    　前記導体部（２４）が露出する領域の上に位置する配線部分（２１ｗ）と、前記緩衝絶縁膜（２３）の上に位置するパッド部分（２１ｐ）とを有する電極層（２１）とを備えた、電力用半導体装置。
  2. 　前記ゲート電極（２６）はトレンチゲートである、請求の範囲第１項に記載の電力用半導体装置。
  3. 　平面視において前記トレンチゲートが延びる方向に平行な前記緩衝絶縁膜（２３）の端部は、前記層間絶縁膜（２５）の上に位置する、請求の範囲第２項に記載の電力用半導体装置。
  4. 　前記緩衝絶縁膜（２３）は、前記電極層（２１）の前記パッド部分（２１ｐ）の厚さの５分の１以上かつ５分の４以下の厚さを有する、請求の範囲第１項に記載の電力用半導体装置。
  5. 　前記緩衝絶縁膜（２３）は、前記電極層（２１）の面積の２分の１以下の面積を有する、請求の範囲第１項に記載の電力用半導体装置。
  6. 　前記緩衝絶縁膜（２３）は、ＴＥＯＳ膜、ＳＯＧ膜、有機系絶縁膜のいずれかである、請求の範囲第１項に記載の電力用半導体装置。
  7. 　前記電極層（２１）の前記パッド部分（２１ｐ）に接合されたワイヤ（２２）をさらに備え、
    　前記パッド部分（２１ｐ）は、前記ワイヤ（２２）の幅寸法以上、かつ前記ワイヤ（２２）の幅寸法の３倍以下の幅寸法を有する、請求の範囲第１項に記載の電力用半導体装置。
  8. 　前記電極層（２１）の前記パッド部分（２１ｐ）に接合されたワイヤ（２２）をさらに備え、
    　前記パッド部分（２１ｐ）は、前記パッド部分（２１ｐ）のうち前記ワイヤ（２２）に接合される部分（４４）の長さの３倍以下の長さを有する、請求の範囲第１項に記載の電力用半導体装置。
PCT/JP2009/058320 2009-04-28 2009-04-28 電力用半導体装置 WO2010125639A1 (ja)

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WO2017098547A1 (ja) * 2015-12-07 2017-06-15 三菱電機株式会社 炭化珪素半導体装置
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WO2017098547A1 (ja) * 2015-12-07 2017-06-15 三菱電機株式会社 炭化珪素半導体装置
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KR20120008511A (ko) 2012-01-30
CN102414825B (zh) 2014-12-24
DE112009004978T5 (de) 2012-09-06
CN102414825A (zh) 2012-04-11
JP5599388B2 (ja) 2014-10-01
WO2010125639A9 (ja) 2011-09-15
DE112009004978B4 (de) 2020-06-04
JPWO2010125639A1 (ja) 2012-10-25
US20110309436A1 (en) 2011-12-22

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