CN102362347A - 具有布置在插入层上的电容器的集成电路封装件 - Google Patents

具有布置在插入层上的电容器的集成电路封装件 Download PDF

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CN102362347A
CN102362347A CN2010800128876A CN201080012887A CN102362347A CN 102362347 A CN102362347 A CN 102362347A CN 2010800128876 A CN2010800128876 A CN 2010800128876A CN 201080012887 A CN201080012887 A CN 201080012887A CN 102362347 A CN102362347 A CN 102362347A
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substrate
lid
integrated circuit
substrate layer
package
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CN102362347B (zh
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T·T·童格
L·K·谭
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Altera Corp
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Altera Corp
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Abstract

本文公开了具有多个放置在管芯表面的芯片电容器的集成电路封装件。芯片电容器可以放置在具有插入衬底层的管芯的顶部。将芯片电容器放置在管芯顶部可减小要求的封装衬底的尺寸。一根或更多线可以用于将插入层上的芯片电容器连接到封装衬底。IC封装件可以包括放置在管芯顶部的盖子和热接口材料。盖子可以被成形为盖子的凸出部分通过热接口材料直接接触管芯以提高散热。

Description

具有布置在插入层上的电容器的集成电路封装件
技术领域
本发明一般涉及集成电路(IC)，并且更具体地涉及具有封装件上去耦(on-package decoupling(OPD))电容器的IC封装件。
背景技术
去耦电容器或芯片电容器通常用于去除不想要的信号或降低对芯片的电源噪声。在IC的正常操作中，芯片的电源使用可能变化。例如，芯片可能在电路状态存在变化时尝试从电源引出额外的电流。IC的电流消耗中的恒定变化引起电流波动并在芯片中产生不想要的噪声。同样，去耦电容器通常包含在典型的IC封装件中以稳定电流波动从而使装置更为平稳地运行。
这些电容器通常放置在IC封装件的衬底层上。然而，他们不能距离管芯太近地放置，并且在管芯和管芯周围的芯片电容器之间必须存在足够的空间。因此，当使用较大的管芯时，需要较大的衬底来容纳芯片电容器。换句话说，较大的管芯将要求甚至更大的封装衬底来安装管芯和IC封装件中的所有芯片电容器。封装尺寸的增大不仅增加了封装成本，还因为使用了较大的封装衬底而增大了制造风险。
因此，非常期望提供一种可容纳所有芯片电容器而不会进一步扩大封装衬底的尺寸的IC封装件，其中这些芯片电容器需要放置在IC封装件中。
发明内容
本发明的各实施例包括产生具有OPD电容器的IC封装件的装置和方法。
应当理解本发明可以通过多种方式实施，例如过程、装置、系统或器件。以下描述本发明的几个创造性实施例。
在一个实施例中，公开了一种IC封装件。该IC封装件包括布置在积层衬底上的IC。衬底层布置在IC的顶表面。布置在IC上的衬底层相对积层衬底较薄。多个电容器被布置在IC顶表面的衬底层上。一根或更多线用于将衬底层上的电容器连接到IC下的积层衬底。在一些实施例中，线是铜(Cu)线。在其他实施例中，线是金(Au)线。
在另一实施例中，公开了一种具有带型电路的IC封装件。该IC封装件包括布置在积层衬底表面的IC。带型电路被布置在IC的顶表面。在一个实施例中，带型电路在IC的边缘延伸并且被连接到积层衬底。多个电容器被布置在带型电路上。
在根据本发明的又一实施例中，公开了一种封装IC的方法。该方法包括将IC放置在封装衬底上。多个芯片电容器被放置在衬底层上。之后，衬底层被放置在IC的顶表面上。在一个实施例中，衬底层是放置在IC和多个芯片电容器之间的插入层。衬底层上的多个芯片电容器连接到具有一根或更多线的封装衬底。
根据以示例的方式图示本发明原理的以下详细说明并结合所附附图，本发明的其他方面将是显而易见的。
附图说明
可以通过参考以下说明结合附图来最好地理解本发明，附图中：
示例性而非限制性的图1显示具有芯片电容器的集成电路封装件100。
示例性而非限制性的图2显示根据本发明的一个实施例的IC封装件200。
示例性而非限制性的图2A显示根据本发明的一个实施例具有被成形以提高散热的盖子120的IC封装件250。
示例性而非限制性的图3是根据本发明的一个实施例的IC封装件300的截面图。
示例性而非限制性的图4显示根据本发明的一个实施例具有带型电路404的IC封装件400。
示例性而非限制性的图5显示根据本发明的又一实施例具有2层盖子的IC封装件500。
示例性而非限制性的图6显示根据本发明的一个实施例具有单片盖子120的IC封装件600。
图7显示根据本发明的一个实施例按序封装集成电路以将芯片电容器安装到IC封装件同时不增加IC封装件的尺寸的流程700。
具体实施方式
以下实施例描述产生具有OPD电容器的IC封装件的装置和方法。
然而，对于本领域技术人员来说，可以实践本发明而不具有一些或所有这些具体细节是显而易见的。在其他实例中，并未详细描述众所周知的操作以便不会不必要地模糊本发明。
这里描述的实施例提供产生具有OPD电容器的IC封装件的技术，其中并不扩展封装衬底的尺寸以容纳放置电容器。各实施例允许将芯片电容器放置在管芯顶部的插入层上而不是将电容器放置在管芯周围的积层(build-up)衬底(即封装衬底)上从而使用较小的封装衬底。插入层是放置在管芯和芯片电容器之间的中间衬底层。因此，插入层可以是夹在底部的管芯和放置在顶部的芯片电容器之间的衬底层，虽然与典型的封装衬底相比是较薄的层。这种方式要求芯片电容器仍旧可以放置在IC封装件中而不增加封装衬底(即积层衬底)和整个IC封装件的尺寸。于是，使用的封装件的尺寸基于使用的管芯的大小，而不是放置在封装件中的芯片电容器的数量。
示例性而非限制性的图1显示具有芯片电容器130的集成电路封装件100。具有撞击焊/焊接凸点(solder bump)106的IC 102布置在积层衬底108的一侧或外围。IC 102具有多个将IC 102连接到积层衬底108的接触焊盘106。IC 102和积层衬底108之间的空腔被底部填充物104填充。多个接触导线110布置在积层衬底108的相反侧。来自IC 102的信号通过附连到接触焊盘106的接触导线或焊接球110传递到IC封装件100外。通常用于减少IC 102产生的噪声的多个电容器130围绕着IC 102放置在积层衬底108上。热接口材料(TIM)122布置在IC 102上方并且盖子120放置在TIM 122的顶部。盖子120通常由高导电性材料制成以有效将来自IC 102的热量传递到IC封装件100之外。TIM 122用于填充IC 102和盖子120之间的间隙以提高热传递效率。盖子120的侧面由支撑构件123支撑。在示例性实施例中，支撑构件123是金属加硬器。粘合剂124用于将支撑构件124连接到盖子120和积层衬底108。
示例性而非限制性的图2显示IC封装件200作为依据本发明的一个实施例。衬底层225放置在位于IC 102顶表面的TIM 122的顶部。在一个实施例中，衬底层225包括两个金属层并且比积层衬底108薄。多个芯片电容器130放置在衬底层225顶部。在一个示例性实施例中，衬底层225是放置在IC 102和多个芯片电容器130之间的插入层。衬底层225通过一层TIM 122附连到IC 102。IC 102顶部的多个电容器130通过线210连接到积层108。应当理解，衬底225是多层衬底，其中这些层可以是由绝缘层分离的地平面或电源面，其通过线210将芯片电容器130电连接到积层衬底108。在一个实施例中，线210是铜(Cu)线。在另一实施例中，线210是金(Au)线。在又一实施例中，线210由铝(Al)或可以结合并电耦合到积层衬底108的其他导电金属制成。在一个实施例中，线210以尽可能接近衬底层225的边缘和管芯102的边缘的方式放置以缩短线210的长度从而减少自感应。TIM 122放置在衬底层225上方。TIM 122被成形为TIM 122的中心部分比TIM 122的侧面薄。TIM 122的较薄的中心部分接触衬底层225。IC 102周围的区域和IC封装件200中电容器周围的以模制化合物115填充。因此，在一些实施例中，TIM 122的侧面由模制化合物115支撑。在其他实施例中，TIM 122仅位于TIM 122的中心部分而不具有延伸的侧面。在这些实施例的一些实施例中，粘合剂用于将盖子120附连到模制化合物115。盖子120放置在IC封装件200上方TIM 122的顶部。在一个实施例中，盖子120是由诸如铜等高导电性金属制成的热沉。
示例性而非限制性的图2A根显示据本发明的一个实施例盖子120被成形以提高散热的IC封装件250。多个电容器130放置在通过一层TIM 122附连到IC 102的顶表面的衬底层225上。另一层TIM 122放置在衬底层225的顶部。放置在TIM 122顶部的盖子120以消除TIM 122具有较厚中心部分的必要性的方式被成形。相反，盖子120具有凸出的中心部分，该凸出的中心部分比盖子120的侧面厚。在一个实施例中，凸出的中心部分可以称为内部，并且盖子120的侧面可以称为外部。在另一实施例中，在使用IC 102顶部较薄的TIM 122层时，IC封装件250的散热更为有效。
示例性而非限制性的图3是根据本发明的一个实施例的IC封装件300的截面图。插入层即衬底层225通过TIM 122附连到IC 102的顶表面。然而，不像图2和2A分别所示的IC封装件200和250，IC封装件300中的衬底层225并不覆盖IC 102的顶表面的整个区域。如图3所图示的，IC封装件300中的衬底层225仅覆盖IC 102的顶表面的周边部分。多个电容器130布置在衬底层225的顶部，围绕IC 102的顶表面的周边。TIM 122放置在IC 102上方，并且TIM 122的凸出的中心部分与IC 102的顶表面的中心直接接触。盖子，即热沉，120放置在IC封装件300上方。盖子即热沉，120的凸出部分通过TIM 122连接到IC 102。在一个实施例中，热沉120和IC 102之间的直接接触改善了IC封装件300的散热性，因为来自IC 102的热量可以通过TIM 122直接传播到热沉120而不穿过插入层，即衬底层225。
示例性而非限制性的图4显示根据本发明的一个实施例具有带型电路404的IC封装件400。带型电路404作为多个芯片电容器130和IC 102之间的插入层布置在IC 102上。一层TIM 122将带型电路404附连到IC 102的顶表面。在一个实施例中，带型电路404是2金属层柔性衬底，其中一层连接到电源而另一层接地。芯片电容器130通过带型电路404连接到积层衬底108，带型电路404在IC 102上方延伸以连接到积层衬底108。在示例性实施例中，带型电路404通过焊接接头408连接到积层衬底108。应当理解，带型电路404包括将电信号从芯片电容器130传递到积层衬底108的布线图。还应当理解，带型电路404可以包括保护膜，其覆盖带型电路404上的布线图以保护布线图受到外部污染。在一个实施例中，带型电路404替换图2、2A和3中分别显示的IC封装件200、250和300中的衬底层225。在另一实施例中，使用带型电路404代替图2-3中提供的线210降低IC封装件400中的自感应。TIM 122放置在带型电路404的顶部，其中盖子120放置在IC封装件400上方。带型电路404可以称为在IC上方延伸的柔性电路的单一层。
示例性而非限制性的图5显示根据本发明的又一实施例具有两片盖子的IC封装件500。由支撑构件515支撑的盖子120被放置在IC封装件500上方。IC封装件500中使用的两片盖子由此由附连到支撑构件515的盖子120形成。盖子120具有中心凸出，其与带型电路404和IC 102顶部的TIM122接触。盖子120的中心凸出通过TIM 122和带型电路404与IC 102直接接触。即便带型电路404在IC封装件500中使用，但是本领域技术人员应当理解图2、2A和3中所示的衬底层225可以用作插入层代替带型电路404。多个芯片电容器130放置在IC封装件500中的带型电路404上。IC封装件100、200、250、300和400中的模制化合物115被去除，在IC封装件500中围绕IC 102留下空间510。在一个实施例中，空间510可以称为空腔。在另一实施例中，IC封装件500并不注入模制化合物115。同样，盖子120的侧面由支撑构件515而不是模制化合物115支撑。在示例性实施例中，支撑构件515是由Cu构成的加强器，并且通过粘合剂505与基层衬底108和盖子120接合。在一个实施例中，粘合剂505是热固化粘合剂。在一个实施例中，粘合剂505是环氧粘合剂。
示例性而非限制性的图6显示根据本发明的一个实施例具有单片盖子120的IC封装件600。图6中所示的盖子120具有多个凸出。第一凸出610自盖子120的中心延伸并且接触放置在IC 102顶部的TIM 122。第二凸出620自盖子120的周边延伸并且通过粘合剂505与积层衬底108接合。在一个实施例中，第二凸出620用作支撑放置在IC封装件600上方的盖子120的支撑构件。IC封装件600不使用模制化合物填充，因而围绕封装件600中的IC 102和IC电容器130形成空间510。即便IC封装件600中的电容器130放置在带型电路404上，这也只是示例性的而不是限制性的。本领域技术人员应当理解带型电路404可以用任何其他适当的插入层替代，例如，IC封装件200、250和300中使用的衬底层225。
图7显示根据本发明的一个实施例封装集成电路以将芯片电容器安装到IC封装件同时不增大IC封装件的尺寸的流程700。在操作710中，IC被放置在封装衬底上。在操作720中，多个芯片电容器被布置在衬底层的表面。之后，在操作730中，衬底层被放置在IC的顶表面上。在示例性实施例中，在IC之下的封装衬底包括6-8个金属层并且基本比IC顶部放置的衬底层厚。在一些实施例中，放置在IC顶部的衬底层类似于图2、2A和3所图示的衬底层225。在其他实施例中，衬底层类似于图4、5和6所示的带型电路404。在操作740中，衬底层顶部的多个芯片电容器连接到封装衬底。在一些实施例中，线用于将IC顶部的芯片电容器连接到封装衬底。在其他实施例中，向IC的边缘弯曲的柔性衬底用于将芯片电容器连接到封装衬底。本领域技术人员应当知道已经省去了IC封装过程中的其他已知步骤以便不会模糊本发明，已知步骤如衬底准备、线接合、成型和固化等。
本领域技术人员将理解在图1-6的示例性图示中提供了具有球栅阵列的覆晶(flip chip)封装件。然而，这并非意指限制性的，因为这里描述的技术可以应用到其他封装配置，例如，扩热板球栅阵列(HSBGA)、小外型球栅阵列(LBGA)、细间距球栅阵列(TFBGA)、覆晶晶粒封装(FCCSP)，等。
就此而言，各实施例就集成电路进行了描述。这里描述的方法和装置可以合并到任何适当电路中。例如，该方法和装置可以合并到多种类型的器件中，如微处理器或可编程逻辑器件。举例来说，示例性可编程逻辑器件包括可编程阵列逻辑(PAL)、可编程逻辑阵列(PLA)、现场可编程逻辑阵列(FPGA)、专用标准产品(ASSP)、专用集成电路(ASIC)。
尽管以具体的顺序描述了方法操作，但是应当理解可以在描述的操作之间执行其他操作，可以调整描述的操作，从而他们在稍微不同的时间发生或描述的操作可以分布在允许过程操作发生在与过程关联的各时间间隔的系统中，只要叠置操作的过程以预期的方式执行。
尽管为了清楚理解的目的，已经详细描述了之前的发明，但是可以在所附权利要求的范围内实践一些改变和变更是显而易见的。因此，当前的实施例将被视为示例性的而非限制性的，并且本发明并不限于这里给出的细节，但是可以在所附权利要求的范围内和其等价物内作出修改。

Claims (20)

1.一种集成电路封装件，包括：
积层衬底；
布置在所述积层衬底上的集成电路；
布置在所述集成电路的顶表面上方的衬底层；和
布置在所述衬底层上的多个电容器，其中所述电容器连接至所述积层衬底。
2.根据权利要求1所述的集成电路封装件，还包括：
所述集成电路、衬底层和所述多个电容器周围的模制化合物；
布置在所述衬底层的一部分顶表面上的热接口材料层，所述顶表面不暴露于所述模制化合物；和
具有较厚内部的盖子，其中所述内部放置在所述热接口材料层上方，并且所述盖子的外部由所述模制化合物支撑。
3.根据权利要求1所述的集成电路封装件，其中所述衬底层覆盖所述集成电路的所述顶表面的整个区域。
4.根据权利要求1所述的集成电路封装件，其中所述衬底层覆盖所述集成电路的所述顶表面的周边部分。
5.根据权利要求1所述的集成电路封装件，其中所述积层衬底比所述衬底层厚。
6.根据权利要求1所述的集成电路封装件，其中所述衬底层包括带型电路。
7.一种集成电路封装件，包括：
积层衬底；
布置在所述积层衬底表面上的集成电路；和
布置在所述集成电路的顶表面上的带型电路，所述带型电路具有多个布置在其上的电容器。
8.根据权利要求7所述的集成电路封装件，其中所述带型电路在所述集成电路的外围边缘上方延伸，并且其中所述带型电路与所述积层衬底电通信。
9.根据权利要求7所述的集成电路封装件，进一步包括：
热接口材料，其相对所述带型电路的中心区域布置，所述热接口材料被布置在所述带型电路上的所述多个电容器包围；和
具有凸出内部的盖子，其中所述盖子被布置在所述热接口材料上方。
10.根据权利要求9所述的集成电路封装件，其中所述带型电路和所述盖子之间限定一空腔。
11.根据权利要求9所述的集成电路封装件，进一步包括：
所述中心区域周围的模制化合物，其中所述模制化合物支撑所述盖子。
12.根据权利要求9所述的集成电路封装件，进一步包括：
固定到所述积层衬底的所述表面的支撑构件，所述支撑构件包围所述积层衬底的周边表面，其中所述支撑构件支撑所述盖子。
13.根据权利要求7所述的集成电路封装件，进一步包括：
相对所述带型电路的中心区域布置的热接口材料；和
具有多个凸出的盖子，其中第一凸出自所述盖子的中心部分延伸，第二部分自所述盖子的周边部分延伸，其中所述第一凸出邻近所述热接口材料，并且其中所述第二凸出邻近所述积层衬底。
14.一种封装集成电路的方法，包括：
将集成电路放置在封装衬底上；
将多个芯片电容器布置在衬底层上；
将具有所述多个芯片电容器的所述衬底层放置在所述集成电路的顶表面上；和
将所述衬底层上的所述多个芯片电容器连接到所述封装衬底。
15.根据权利要求14所述的方法，其中所述连接由所述衬底层和所述封装衬底之间的接合线执行。
16.根据权利要求14所述的方法，其中所述连接通过将所述多个芯片电容器放置在柔性电路的单一层上完成，其中所述柔性电路的单一层在所述集成电路的上方延伸至所述封装衬底。
17.根据权利要求14所述的方法，进一步包括：
将第一热接口材料放置在所述集成电路的所述顶表面上，其中所述第一热接口材料放置在所述集成电路和所述衬底层之间；
将第二热接口材料相对所述衬底层的中心区域放置；和
将盖子放置在所述第二热接口材料上方。
18.根据权利要求17所述的方法，其中所述第二热接口材料被所述衬底层上的所述多个芯片电容器包围。
19.根据权利要求14所述的方法，其中所述衬底层仅覆盖所述集成电路的所述顶表面的周边部分。
20.根据权利要求14所述的方法，其中所述衬底层覆盖所述集成电路的所述顶表面的整个区域。
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