JP5389971B2 - 挿入層上に配置されたコンデンサーを有するicパッケージ - Google Patents
挿入層上に配置されたコンデンサーを有するicパッケージ Download PDFInfo
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- JP5389971B2 JP5389971B2 JP2012076506A JP2012076506A JP5389971B2 JP 5389971 B2 JP5389971 B2 JP 5389971B2 JP 2012076506 A JP2012076506 A JP 2012076506A JP 2012076506 A JP2012076506 A JP 2012076506A JP 5389971 B2 JP5389971 B2 JP 5389971B2
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- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Description
本発明は、概して集積回路(IC)に関し、より具体的には、オンパッケージデカップリング(OPD)コンデンサーを有するICパッケージに関する。
例えば、本発明は以下の項目を提供する。
(項目1)
集積回路(IC)パッケージであって、
ビルドアップ基板と、
該ビルドアップ基板上に配置された集積回路と、
該集積回路の最上面を覆って配置された基板層と、
該基板層上に配置された複数のコンデンサーと
を備え、
該コンデンサーは、該ビルドアップ基板に接続されている、ICパッケージ。
(項目2)
前記IC、基板層、および複数のコンデンサーを囲む成形コンパウンドと、
該基板層の最上面の一部の上に配置される熱インタフェイス材料(TIM)層であって、該最上面は該成形コンパウンドに露出されていない、TIM層と、
より厚い内側部分を有する蓋であって、該内側部分は、該TIM層を覆って配置され、該蓋の外側部分は該成形コンパウンドによって支持される、蓋と
をさらに備えている、項目1に記載のICパッケージ。
(項目3)
前記基板層は、前記ICの前記最上面の全領域を覆っている、項目1に記載のICパッケージ。
(項目4)
前記基板層は、前記ICの前記最上面の周辺部分を覆っている、項目1に記載のICパッケージ。
(項目5)
前記ビルドアップ基板は、前記基板層よりも厚い、項目1に記載のICパッケージ。
(項目6)
前記基板層は、テープ回路を含む、項目1に記載のICパッケージ。
(項目7)
集積回路(IC)パッケージであって、
ビルドアップ基板と、
該ビルドアップ基板の表面上に配置された集積回路と、
該ICの最上面上に配置されたテープ回路と、
を備え、
該テープ回路は、該テープ回路上に複数のコンデンサーが配置されている、ICパッケージ。
(項目8)
前記テープ回路が前記ICの周辺端を覆って延びており、該テープ回路は前記ビルドアップ基板と電気的に連絡している、項目7に記載のICパッケージ。
(項目9)
前記テープ回路の中央領域に対して配置された熱インタフェイス材料(TIM)であって、該TIMは該テープ回路の上に配置された前記複数のコンデンサーによって囲まれている、TIMと、
突出している内側部分を有する蓋であって、該蓋は、該TIMを覆って配置されている、蓋と
をさらに備えている、項目7に記載のICパッケージ。
(項目10)
キャビティが前記テープ回路と前記蓋の間に規定されている、項目9に記載のICパッケージ。
(項目11)
前記中央領域を囲んでいる成形コンパウンドをさらに備え、該成形コンパウンドは、前記蓋を支持する、項目9に記載のICパッケージ。
(項目12)
前記ビルドアップ基板の前記表面に固着される支持部材をさらに備え、該支持部材は、該ビルドアップ基板の周辺表面を囲み、該支持部材は、前記蓋を支持する、項目9に記載のICパッケージ。
(項目13)
前記テープ回路の中央領域に対して配置されるTIMと、
複数の突出部を有する蓋と
をさらに備え、
第一の突出部は該蓋の中央部から延びており、第二の突出部は該蓋の周辺部から延びており、該第一の突出部は該TIMに隣接し、該第二の突出部は前記ビルドアップ基板に隣接している、項目7に記載のICパッケージ。
(項目14)
集積回路(IC)をパッケージングする方法であって、
集積回路をパッケージング基板上に設置することと、
基板層上に複数のチップコンデンサーを配置することと、
該複数のチップコンデンサーを有する該基板層を該ICの最上面上に設置することと、
該基板層上の該複数のチップコンデンサーを該パッケージング基板に接続することと
を含む、方法。
(項目15)
前記接続することは、前記基板層と前記パッケージング基板との間にワイヤーを連結することによって行われる、項目14に記載の方法。
(項目16)
前記接続することは、前記ICを覆って前記パッケージング基板まで延びている可撓性回路の一体層上に前記複数のチップコンデンサーを設置することによって行われる、項目14に記載の方法。
(項目17)
第一の熱インタフェイス材料(TIM)を前記ICの前記最上面上に設置することであって、該第一のTIMは、該ICと前記基板層との間に設置される、ことと、
第二のTIMを該基板層の中央領域に対して設置することと、
該第二のTIMを覆って蓋を設置することと
をさらに含む、項目14に記載の方法。
(項目18)
前記第二のTIMは、前記基板層上の前記複数のチップコンデンサーによって囲まれている、項目17に記載の方法。
(項目19)
前記基板層は、前記ICの前記最上面の周辺部のみを被覆している、項目14に記載の方法。
(項目20)
前記基板層は、前記ICの前記最上面の全領域を被覆している、項目14に記載の方法。
Claims (6)
- 集積回路(IC)パッケージであって、
ビルドアップ基板と、
前記ビルドアップ基板の表面に配置されたICと、
前記ICの最上面に配置されたテープ回路であって、前記テープ回路は、前記テープ回路上に配置された複数のコンデンサーを有し、前記テープ回路は、前記ICの周辺端の上を延びている、テープ回路と、
前記テープ回路の中央領域に対して配置された熱インタフェイス材料(TIM)であって、前記TIMは、前記テープ回路上に配置された前記複数のコンデンサーによって囲まれている、TIMと、
突出している内側部分を有する蓋であって、前記蓋は、前記TIMの上に配置されている、蓋と
を備えている、ICパッケージ。 - 前記テープ回路は、前記ビルドアップ基板と電気的に連絡している、請求項1に記載のICパッケージ。
- キャビティが前記テープ回路と前記蓋の間に規定されている、請求項1に記載のICパッケージ。
- 前記中央領域を囲んでいる成形コンパウンドをさらに備え、前記成形コンパウンドは、前記蓋を支持する、請求項1に記載のICパッケージ。
- 前記ビルドアップ基板の前記表面に固着される支持部材をさらに備え、前記支持部材は、前記ビルドアップ基板の周辺表面を囲み、前記支持部材は、前記蓋を支持する、請求項1に記載のICパッケージ。
- 前記蓋は、複数の突出部を有し、
第一の突出部は、前記蓋の中央部から延びており、第二の突出部は、前記蓋の周辺部から延びており、前記第一の突出部は、前記TIMに隣接しており、前記第二の突出部は、前記ビルドアップ基板に隣接している、請求項1に記載のICパッケージ。
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US12/356,491 US7989942B2 (en) | 2009-01-20 | 2009-01-20 | IC package with capacitors disposed on an interposal layer |
US12/356,491 | 2009-01-20 |
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US9640477B1 (en) | 2016-03-04 | 2017-05-02 | Fuji Xerox Co., Ltd. | Semiconductor package and method of producing the semiconductor package |
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US9640477B1 (en) | 2016-03-04 | 2017-05-02 | Fuji Xerox Co., Ltd. | Semiconductor package and method of producing the semiconductor package |
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US7989942B2 (en) | 2011-08-02 |
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EP2389686A2 (en) | 2011-11-30 |
US8525326B2 (en) | 2013-09-03 |
WO2010090820A2 (en) | 2010-08-12 |
JP5095012B2 (ja) | 2012-12-12 |
CN102362347A (zh) | 2012-02-22 |
JP2012518893A (ja) | 2012-08-16 |
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