CN102362343B - 包括非常锥形的转变贯孔的半导体装置的金属化系统 - Google Patents

包括非常锥形的转变贯孔的半导体装置的金属化系统 Download PDF

Info

Publication number
CN102362343B
CN102362343B CN200980157543.1A CN200980157543A CN102362343B CN 102362343 B CN102362343 B CN 102362343B CN 200980157543 A CN200980157543 A CN 200980157543A CN 102362343 B CN102362343 B CN 102362343B
Authority
CN
China
Prior art keywords
mask
dielectric material
depth
degree
lateral dimension
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN200980157543.1A
Other languages
English (en)
Chinese (zh)
Other versions
CN102362343A (zh
Inventor
F·福斯特尔
T·沃纳
K·弗罗贝格
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN102362343A publication Critical patent/CN102362343A/zh
Application granted granted Critical
Publication of CN102362343B publication Critical patent/CN102362343B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN200980157543.1A 2008-12-31 2009-12-29 包括非常锥形的转变贯孔的半导体装置的金属化系统 Active CN102362343B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
DE102008063430.1 2008-12-31
DE102008063430.1A DE102008063430B4 (de) 2008-12-31 2008-12-31 Verfahren zur Herstellung eines Metallisierungssystem eines Halbleiterbauelements mit zusätzlich verjüngten Übergangskontakten
US12/634,216 2009-12-09
US12/634,216 US8835303B2 (en) 2008-12-31 2009-12-09 Metallization system of a semiconductor device comprising extra-tapered transition vias
PCT/EP2009/009308 WO2010076019A1 (en) 2008-12-31 2009-12-29 A metallization system of a semiconductor device comprising extra-tapered transition vias

Publications (2)

Publication Number Publication Date
CN102362343A CN102362343A (zh) 2012-02-22
CN102362343B true CN102362343B (zh) 2015-03-25

Family

ID=42234624

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200980157543.1A Active CN102362343B (zh) 2008-12-31 2009-12-29 包括非常锥形的转变贯孔的半导体装置的金属化系统

Country Status (6)

Country Link
US (1) US8835303B2 (enExample)
JP (1) JP2012514319A (enExample)
KR (1) KR20130127013A (enExample)
CN (1) CN102362343B (enExample)
DE (1) DE102008063430B4 (enExample)
WO (1) WO2010076019A1 (enExample)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2975826A1 (fr) * 2011-05-27 2012-11-30 St Microelectronics Crolles 2 Procede de formation d'un trou ou d'une tranchee ayant un profil evase
JP2013021001A (ja) * 2011-07-07 2013-01-31 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8987916B2 (en) * 2011-11-28 2015-03-24 Freescale Semiconductor, Inc. Methods and apparatus to improve reliability of isolated vias
JP5891846B2 (ja) * 2012-02-24 2016-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
US8815752B2 (en) * 2012-11-28 2014-08-26 Micron Technology, Inc. Methods of forming features in semiconductor device structures
US9305886B2 (en) * 2013-12-18 2016-04-05 Globalfoundries Singapore Pte. Ltd. Integrated circuits having crack-stop structures and methods for fabricating the same
US10163778B2 (en) 2014-08-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of damascene structure
CN104505471B (zh) * 2014-12-22 2017-12-29 昆山工研院新型平板显示技术中心有限公司 一种高开口率掩膜板的制备方法及掩膜板
KR20160120891A (ko) 2015-04-09 2016-10-19 삼성전자주식회사 반도체 장치
US9536826B1 (en) * 2015-06-15 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (finFET) device structure with interconnect structure
US9679850B2 (en) * 2015-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company Ltd. Method of fabricating semiconductor structure
US9917027B2 (en) * 2015-12-30 2018-03-13 Globalfoundries Singapore Pte. Ltd. Integrated circuits with aluminum via structures and methods for fabricating the same
CN107622992B (zh) 2016-07-14 2021-04-27 联华电子股份有限公司 半导体元件及其制作方法
US10276485B2 (en) 2017-08-02 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory
US10998259B2 (en) 2017-08-31 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10522394B2 (en) * 2017-09-25 2019-12-31 Marvell World Trade Ltd. Method of creating aligned vias in ultra-high density integrated circuits
US10566411B2 (en) * 2017-12-07 2020-02-18 Globalfoundries Inc. On-chip resistors with direct wiring connections
KR102751263B1 (ko) 2018-08-07 2025-01-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US11158571B2 (en) * 2018-12-20 2021-10-26 Micron Technology, Inc. Devices including conductive interconnect structures, related electronic systems, and related methods
WO2020140202A1 (en) * 2019-01-02 2020-07-09 Yangtze Memory Technologies Co., Ltd. Method for forming dual damascene interconnect structure
CN112151497B (zh) 2019-06-28 2023-08-22 台湾积体电路制造股份有限公司 半导体结构以及形成半导体结构的方法
DE102019131408B4 (de) 2019-06-28 2025-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Verbesserte Kontaktierung von Metallleitungen bei Fehlausrichtung von BEOL-Durchkontaktierungen
US20210020455A1 (en) * 2019-07-17 2021-01-21 Nanya Technology Corporation Conductive via structure
US11652049B2 (en) 2021-03-10 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming thereof
KR20230009126A (ko) * 2021-07-08 2023-01-17 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
KR20230013438A (ko) * 2021-07-19 2023-01-26 삼성전자주식회사 반도체 장치
KR20230135384A (ko) * 2022-03-16 2023-09-25 주식회사 디비하이텍 저항 변화 메모리 장치 및 그 제조 방법
US20240332074A1 (en) * 2023-03-27 2024-10-03 International Business Machines Corporation Metal wires with expanded sidewalls

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039114A1 (en) * 1999-01-08 2001-11-08 Ryoichi Nakamura Method Of Forming Contact Or Wiring In Semiconductor Device
US6440847B1 (en) * 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
CN1873944A (zh) * 2005-05-30 2006-12-06 富士通株式会社 半导体器件及其制造方法
US20070126121A1 (en) * 2005-12-05 2007-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure with improved reliability

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4472240A (en) * 1981-08-21 1984-09-18 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
JPH03257822A (ja) * 1990-03-07 1991-11-18 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2787646B2 (ja) * 1992-11-27 1998-08-20 三菱電機株式会社 半導体装置の製造方法
JP3427534B2 (ja) * 1995-01-11 2003-07-22 ソニー株式会社 接続孔の形成方法
JPH10163316A (ja) * 1996-12-04 1998-06-19 Sony Corp 半導体装置における埋め込み配線の形成方法
US6025259A (en) * 1998-07-02 2000-02-15 Advanced Micro Devices, Inc. Dual damascene process using high selectivity boundary layers
US6239017B1 (en) * 1998-09-18 2001-05-29 Industrial Technology Research Institute Dual damascene CMP process with BPSG reflowed contact hole
JP2000260873A (ja) * 1999-01-08 2000-09-22 Nec Corp 半導体装置のコンタクト又は配線の形成方法
TW424301B (en) * 1999-10-02 2001-03-01 Taiwan Semiconductor Mfg Manufacturing method for dual damascene
JP2001358213A (ja) * 2000-06-13 2001-12-26 Nec Corp テーパ状スルーホールを有する半導体装置の製造方法
US6861347B2 (en) * 2001-05-17 2005-03-01 Samsung Electronics Co., Ltd. Method for forming metal wiring layer of semiconductor device
KR100386622B1 (ko) * 2001-06-27 2003-06-09 주식회사 하이닉스반도체 듀얼 다마신 배선 형성방법
US6605540B2 (en) * 2001-07-09 2003-08-12 Texas Instruments Incorporated Process for forming a dual damascene structure
KR100454128B1 (ko) * 2002-04-02 2004-10-26 삼성전자주식회사 금속간 절연막 패턴 및 그 형성 방법
KR100529676B1 (ko) * 2003-12-31 2005-11-17 동부아남반도체 주식회사 듀얼 다마신 패턴을 형성하는 방법
JP2007149773A (ja) * 2005-11-24 2007-06-14 Mitsumi Electric Co Ltd 半導体装置の製造方法
DE102006025405B4 (de) * 2006-05-31 2018-03-29 Globalfoundries Inc. Verfahren zur Herstellung einer Metallisierungsschicht eines Halbleiterbauelements mit unterschiedlich dicken Metallleitungen

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010039114A1 (en) * 1999-01-08 2001-11-08 Ryoichi Nakamura Method Of Forming Contact Or Wiring In Semiconductor Device
US6440847B1 (en) * 2001-04-30 2002-08-27 Taiwan Semiconductor Manufacturing Company Method for forming a via and interconnect in dual damascene
CN1873944A (zh) * 2005-05-30 2006-12-06 富士通株式会社 半导体器件及其制造方法
US20070126121A1 (en) * 2005-12-05 2007-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure with improved reliability

Also Published As

Publication number Publication date
DE102008063430A1 (de) 2010-07-08
DE102008063430B4 (de) 2016-11-24
KR20130127013A (ko) 2013-11-22
US20100164121A1 (en) 2010-07-01
CN102362343A (zh) 2012-02-22
WO2010076019A1 (en) 2010-07-08
US8835303B2 (en) 2014-09-16
JP2012514319A (ja) 2012-06-21

Similar Documents

Publication Publication Date Title
CN102362343B (zh) 包括非常锥形的转变贯孔的半导体装置的金属化系统
US8048796B2 (en) Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material
US8377820B2 (en) Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size
CN106057772B (zh) 互连结构及其形成方法
US20040232552A1 (en) Air gap dual damascene process and structure
US20170110369A1 (en) Electronic device and method for producing same
CN101278386A (zh) 用于形成包含导电封盖层的铜基金属化层的技术
CN101038905A (zh) 具有阻挡层冗余特征的互连结构
TWI588901B (zh) 自對準通孔流程
US9627256B2 (en) Integrated circuit interconnects and methods of making same
US20170256449A1 (en) Methods of forming conductive structures with different material compositions in a metallization layer
US8383510B2 (en) Semiconductor device comprising metallization layers of reduced interlayer capacitance by reducing the amount of etch stop materials
WO2010060639A1 (en) A microstructure device including a metallization structure with air gaps formed commonly with vias
US20090108462A1 (en) Dual integration scheme for low resistance metal layers
JPWO2006046487A1 (ja) 半導体装置および半導体装置の製造方法
US20100052175A1 (en) Reducing leakage and dielectric breakdown in dielectric materials of metallization systems of semiconductor devices by forming recesses
KR100939773B1 (ko) 반도체 소자의 금속배선 및 그의 형성방법
US7498677B2 (en) Semiconductor device
JP2001176965A (ja) 半導体装置及びその製造方法
US7618887B2 (en) Semiconductor device with a metal line and method of forming the same
JP2010141024A (ja) 半導体装置の製造方法および半導体装置
CN113594133B (zh) 半导体结构及其形成方法
JP2009016619A (ja) 半導体装置及びその製造方法
KR100752174B1 (ko) 2개의 시드층을 이용한 반도체 소자의 구리 배선 형성 방법
JP5424551B2 (ja) 半導体装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Free format text: FORMER OWNER: AMD FAB 36 LIMITED LIABILITY COMPANY + CO. KG

Effective date: 20120106

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20120106

Address after: American California

Applicant after: Advanced Micro Devices Inc.

Address before: American California

Applicant before: Advanced Micro Devices Inc.

Co-applicant before: AMD FAB 36 limited liability company

C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant