CN102254899B - 具有对准标记的半导体结构及其形成方法 - Google Patents

具有对准标记的半导体结构及其形成方法 Download PDF

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CN102254899B
CN102254899B CN201010527199.5A CN201010527199A CN102254899B CN 102254899 B CN102254899 B CN 102254899B CN 201010527199 A CN201010527199 A CN 201010527199A CN 102254899 B CN102254899 B CN 102254899B
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semiconductor substrate
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CN102254899A (zh
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温明璋
王宪程
陈俊光
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种具有对准标记的半导体结构及其形成方法。在一实施例的半导体结构中，多个栅极堆叠形成于半导体基板上并构成对准标记。多个掺杂结构形成于半导体基板中并位于每一栅极堆叠的两侧。多个通道区位于栅极堆叠下方，且通道区不具有任何通道掺质。

Description

具有对准标记的半导体结构及其形成方法
技术领域
本发明是有关于一种微影工艺(lithographic processes)所用的对准标记(alignment masks)，且特别是有关于一种改善高介电常数的介电层-金属栅极工艺的对准标记结构与形成方法。
背景技术
对准标记对半导体组件或集成电路的制作很重要，这是因为制作中需根据对准标记对准导电材料层、半导体层与绝缘材料层。产品功能性与可信度的关键在于准确对准每一层与前一层。一般来说，晶片步进机可完成上述对准工作。步进机的晶片吸盘可用以放置晶片。步进机可将固定其中的光罩的电路图案投影至晶片上的光阻层。在光罩图案转移前，晶片需先准确对准光罩。当对准步骤完成后，才可继续将光罩图案投影至半导体晶片上。
在对准过程中，一般以激光束侦测晶片上的对准标记，经对准标记反弹后形成反射光信号。上述反射光信号将由步进机的侦测器接收并分析，以确认对准标记的确切位置。值得注意的是，由对准标记反射的信号质量将直接反应在结构的可信度及集成度上。现有技术所形成的对准标记并无法形成够强的反射信号，这会使准确的对准更为困难。
综上所述，部分现有技术已调整对准标记的形成方法以符合特定需求，但这些方法并不完全适于所有应用。
发明内容
本发明的目的在于提供一种具有对准标记的半导体结构及其形成方法。
本发明提供一种对准标记的结构，其包括位于半导体基板上的多个栅极堆叠、位于栅极堆叠两侧的半导体基板中的多个掺杂结构，以及位于栅极堆叠下方的多个通道区，其中通道区不具有任何掺质。
本发明亦提供一种具有对准标记的半导体结构，包括半导体基板，其具有组件区与对准区。位于组件区中的场效晶体管组件，其包括位于半导体基板上的第一栅极堆叠。第一源极/漏极区形成于半导体基板中，并分别位于第一栅极堆叠两侧。第一通道区具有通道掺杂结构，位于第一栅极堆叠下的半导体基板中。位于对准区中的对准标记，其包括位于半导体基板上的第二栅极堆叠、位于第二栅极堆叠两侧的半导体基板中的第二源极/漏极区及位于第一栅极堆叠下的半导体基板中的第二通道区，且第二通道区不具有通道掺杂结构。
本发明更提供一种半导体结构的形成方法，包括提供半导体基板，其具有组件区与对准区。以布值掩模遮住对准区，进行第一离子布植至半导体基板的组件区中，同时以布植掩模层覆盖对准区。接着形成第一多晶硅栅极堆叠于组件区中，与第二多晶硅栅极堆叠于对准区中。接着进行第二离子布植至半导体基板的组件区与对准区中。
本发明并不限于半导体结构如FET(金属氧化物半导体晶体管)或SRAM，并可进一步应用于其它具有金属栅极堆叠与对准标记的集成电路。举例来说，半导体结构可包含动态随机存取内存(DRAM)单元、影像侦测器、电容及/或其它通称为微电子组件的组件。在另一实施例中，半导体结构包含鳍状场效晶体管(FinFET)。可以确定的是，本发明亦可应用于其它种类的晶体管如单栅极晶体管、双栅极晶体管或其它多栅极晶体管，亦可应用于其它组件如侦测单元、存储单元、逻辑单元或其它单元。
附图说明
图1是本发明的多种实施例中，具有对准标记的半导体结构的形成方法的流程图；
图2-10是本发明的多种实施例中，具有对准标记的半导体结构的工艺剖视图；
图11是图8的半导体结构中对准标记的上视图。
【主要组件符号说明】
100：方法                                 102：步骤
104：步骤                                 106：步骤
108：步骤                                 110：步骤
112：步骤                                 200：半导体结构
210：半导体基板                          212：对准区
214：组件区                              216：浅沟槽绝缘结构
217：布植掩模层                          218：第一离子布植
219：掺杂结构                            220：介电材料层
222：硅层                                224：硬掩模层
226：栅极堆叠                            228：栅极堆叠
229：栅极堆叠                            230：LDD布植
232：LDD结构                             234：间隙壁
236：离子布植                            242：层间介电层
244：高介电常数的介电材料层              246：功函数金属层
248：导电材料层                          250：接触蚀刻停止层
252：层间介电层                          260：对准标记
具体实施方式
本发明是有关于一种微影工艺所用的对准标记，且特别是有关于一种改善高介电常数的介电层-金属栅极工艺的对准标记结构与形成方法。可以理解的是，下述内容将提供多种不同的实施例或实例，以说明不同实施例中的不同结构。下述的特定组成与形态是用以简化说明，当然只用以举例而非限定本发明。此外为了简化说明，本发明在不同实例中可能重复一些标号及/或符号，但这些重复不代表不同实施例及/或结构中具有相同标号的组件具有对应关系。另一方面，形成第一结构于第二结构上可能包含下列两者情况。在第一种情况中，第一结构直接形成于第二结构上，两者直接接触。在另一种情况中，第一结构与第二结构之间隔有额外结构，两者并不直接接触。
图1是一实施例中，制造半导体组件的方法100的流程图。根据本发明的多种实施例，半导体组件包含金属栅极与对准标记。图2-10是依据本发明多种实施例中，半导体结构200的工艺剖视图。通过图1-10及相关描述，将揭露半导体结构200与其形成方法100。
如图1及2所示，方法100的步骤102提供半导体基板210。半导体基板210的材料可为硅。另一方面，半导体基板210的材料也可为锗、硅锗合金或其它合适的半导体材料。半导体基板210亦包含多种绝缘结构如浅沟槽绝缘(STI)形成于其中，浅沟槽绝缘的作用在分隔不同组件。在一实施例中，半导体基板210包含对准区212与组件区214，前者具有对准标记而后者具有一或多个场效晶体管(FET)及(或)其它组件。多种浅沟槽绝缘结构216是形成于半导体基板210中。形成浅沟槽绝缘结构216的方法可为蚀刻基板形成沟槽，接着在沟槽中填入一或多种绝缘材料如氧化硅、氮化硅或氮氧化硅。填入沟槽的结构可为多层结构，比如在衬垫氧化层上以氧化硅填满沟槽。在一实施例中，浅沟槽绝缘结构216的工艺如下述：成长垫氧化层(pad oxide layer)后，以低压化学气相沉积法(LPCVD)形成氮化物层。接着利用光阻与光罩，于光阻中图案化出浅沟槽绝缘开口，再利用浅沟槽开口来蚀刻基板，形成沟槽。接着，选择性地以热氧化法来成长衬氧化层(liner oxide layer)，以改善沟槽界面，再以化学气相沉积法将氧化物填入沟槽中。然后以化学机械研磨法(CMP)回蚀上述结构后，剥除氮化物层即完成浅沟槽绝缘结构。半导体基板210亦具有多种n型井区与p型井区，其位于各种主动区中。
如图1及2所示，方法100的步骤104进行第一离子布植218，将掺质布植入半导体基板210的组件区214之中。在此同时，以布植掩模层(implant masklayer)217保护对准区212不受第一离子布植218影响。在形成栅极堆叠之前，采用一或多种离子的第一离子布植218将形成多种掺杂结构219。在一实施例中，第一离子布植218包含形成井区如n型井区或p型井区的井区离子布植、调整临界电压的离子布植、反贯穿(anti-punch through)离子布植或上述的组合。布植掩模层217可为图案化光阻层或其它合适材料，如氮化硅。在一实施例中，布植掩模层217选用图案化光阻层。图案化光阻层形成于基板210上以覆盖对准区212，且图案化光阻层的开口会露出部分或全部的组件区214。当第一离子布植218施加于组件区214时，掺质将形成多个掺杂结构219。在一实例中，当采用p型掺质形成一或多个p型井区于部份组件区214时，布植掩模层217将覆盖对准区与其它作为n型井区的部份组件区214。当布植掩模层217为图案化光阻层时，其形成方法为如下的微影工艺：涂布光阻、软烤(soft baking)、曝光、曝光后烘烤(post-exposure baking)、显影及硬烤(hard baking)。之后，可采用适当工艺来移除图案化光阻，比如湿式剥除法或等离子灰化法。在其它实施例中，可额外使用硬掩模层。此时图案化光阻将用以图案化硬掩模层，并以图案化硬掩模层作为布植掩模层。
如图1、3及4所示，接着进行方法100的步骤106，以于组件区214与对准区212中形成栅极堆叠。在一实施例中，于半导体基板210上形成多种栅极材料层，如图3所示。栅极材料层包含介电材料层220与硅层222，如多晶硅。在此实施例中，硅层222可为非掺杂硅，且介电材料层220可为高介电常数的介电材料。在其它实施例中，硅层222可为非晶硅或额外包含非晶硅。当硅层222采用非掺杂的非晶硅或多晶硅时，其形成方法为化学气相沉积法，并采用硅烷或其它硅为主化合物作为前趋物。非掺杂的非晶硅的沉积条件可为较高温度。
当介电材料层220具有高介电常数时，其介电常数高于热氧化硅的介电常数(约3.9)。在一实施例中，高介电常数的介电材料层220可为氧化铪。在各种实例中，高介电常数的介电材料层220包含金属氧化物、金属氮化物或上述的组合。在一实例中，高介电常数的介电材料层220的厚度介于约10埃至约100埃之间。在多种实施例中，介电材料层220包含多层结构的介电层，比如界面层(如氧化硅)与位于界面层上的高介电常数材料层。在多种实施例中，界面层的形成方法包含化学氧化法、热氧化法、原子层沉积法或化学气相沉积法。高介电常数之介电材料层的形成方法包含原子层沉积法、化学气相沉积法、等离子增强式化学气相沉积法或等离子增强式原子层沉积法。
在另一实施例中，用以图案化栅极的硬掩模层224(如氮化硅或氧化硅)是进一步形成于栅极材料层上。硬掩模层如氮化硅与氧化硅的形成方法可为化学气相沉积法或其它合适技术。
接着如图4所示，图案化栅极材料层以形成一或多个栅极堆叠，如对准区212中的栅极堆叠226及228，并于组件区214中形成一或多个栅极堆叠229(如虚置栅极)。图案化栅极材料层的方法可为微影工艺及/或蚀刻工艺。举例来说，先形成图案化光阻层于硬掩模层224上以定义多种电阻区与栅极区。图案化光阻层的形成方法包括涂布光阻、软烤、曝光、曝光后烘烤(PEB)、显影及硬烤。接着沿图案化光阻层的开口蚀刻硬掩模层224，形成图案化的硬掩模层224。接着以图案化的硬掩模层224蚀刻栅极材料层，形成多种电阻与栅极堆叠。之后以适当工艺移除图案化光阻层，比如湿式剥除法或等离子灰化法。在其它实施例中，若省略硬掩模层224的话，可直接以图案化光阻层作为蚀刻栅极材料层的蚀刻掩模。
上述的栅极堆叠226与228将构成对准标记。在一实施例中，对准区212的栅极堆叠226与228将构成周期性结构，其可作为光栅对准标记。举例来说，光栅对准标记可具有周期性平行排列的两个、三个、四个或更多个栅极堆叠。在另一实施例中，对准标记之栅极堆叠可为框式的盒中盒或框中框设计，以构成框式对准标记。在另一实施例中，形成于组件区214的栅极堆叠229可作为场效晶体管(field-effect transistor；FET)，比如金属氧化物半导体(MOS)晶体管。场效晶体管可为n型场效晶体管(nFET)或p型场效晶体管(pFET)。在其它实施例中，形成于组件区214的栅极堆叠229可作为影像侦测器。
如图1、5及6所示，方法100的步骤108接着进行第二离子布植230至半导体基板210中，使掺质布植入组件区214与对准区212。第二离子布植230的顺序在步骤106形成栅极堆叠226、228及229之后。第二离子布植230可包含多种布植步骤以分别形成掺杂结构。在一实施例中，第二离子布植230包含淡掺杂漏极(lightly-doped drain；LDD)离子布植与重掺杂源极/漏极(S/D)布植。由于第二离子布植230的顺序在形成栅极堆叠226、228及229的步骤106之后，因此其形成的掺杂结构实质上位于栅极堆叠226、228及229侧壁旁的半导体基板210中，而非位于栅极堆叠226、228及229下方的通道区。
在进一步的实施例中，第二离子布植230包含LDD布植以于对准区212及组件区214中形成LDD结构232，如图5所示。在一实例中，n型掺质如磷或砷被布植入半导体基板210的组件区214与对准区212，以形成n型LDD结构。上述布植的掺杂剂量大于约1×1014离子数/cm2，以有效改变半导体基板210的折射率。在一实施例中，n型LDD布植可让硅基板的折射率由3.89下降至3.0。在对准区212中，位于栅极堆叠下的硅基板(未布植)与LDD布植过的硅基板之间的折射率差异，可增加对准标记在对准步骤中的对比。在一实施例中，LDD布植的剂量约为1015离子数/cm2。在另一实例中，LDD布植的能量介于约50keV至约100keV之间。在一实施例中，具有LDD布植图案的光罩具有额外开口来对应对准区。举例来说，若对准区212的尺寸为50微米×882微米，则对应的光罩具有额外开口，其尺寸为50微米*882微米，以于对准区212中形成LDD结构。在另一实施例中，可采用p型掺质(如硼)，于对准区212中形成p型LDD结构。
第二离子布植230可进一步在LDD布植后进行另一布植步骤，以形成重掺杂源极/漏极(S/D)结构。如此一来，组件区214与对准区212中的每一栅极堆叠均具有LDD结构与S/D结构，统称为源极/漏极区。当组件区214同时包含n型FET(nFET)与p型FET(pFET)时，将采用适当的掺质分别形成nFET与pFET的源极区与漏极区。
在一实施例中，以nFET为例，是以淡掺杂剂量进行离子布植以形成LDD结构232。在沉积介电层后进行非等向蚀刻如等离子蚀刻，即形成间隙壁234。接着以重掺杂剂量进行离子布植236以形成重掺杂S/D结构。其它p型FET的源极/漏极结构亦可由类似工艺完成，差异在采用相反的掺杂型态。
在一实施例中，形成多种n型源极与漏极结构的掺杂工艺，亦于对准区212中形成对应结构如LDD与S/D结构，如图6所示。同样地，间隙壁234亦可形成于对准区212中的栅极堆叠的侧壁上。在一实施例中，之后可进行高温回火工艺以活化组件区214中的源极与漏极结构中的不同掺质。在另一实施例中，第二离子布植230可额外进行或直接置换为环形离子布植工艺(pocketion implantation)，其掺质型态与源极/漏极相反，形成的掺杂区位于半导体基板210中并与通道区相邻。
如图1、7及8所示，接着进行方法100的步骤110以形成金属栅极于组件区214及对准区212中。在一实施例中，先形成层间介电层242于半导体基板210上。层间介电层242可为氧化硅、低介电常数的介电材料、其它合适的介电材料或上述的组合。在另一实施例中，层间介电层242由下往上依序可为缓冲氧化硅层、接触蚀刻停止层(contact etch stop layer；CESL)以及其它介电材料层。层间介电层242的形成方法将叙述如下。
层间介电层242可由合适技术(如化学气相沉积法)形成。举例来说，可采用高密度等离子化学气相沉积法形成层间介电层242。在一实施例中，形成于半导体基板210上的层间介电层242，将填入对准区212与组件区214的栅极堆叠226、228及229之间的空隙。在进一步的实施例中，形成于半导体基板210上的层间介电层242其表面高度将高于栅极堆叠如226、228及229的上表面。接着以化学机械研磨工艺减少层间介电层242的厚度，直到露出栅极堆叠226、228及229的上表面为止。为了部分移除并平坦化层间介电层242，可调整CMP工艺的条件与参数，如研磨浆组成与研磨压力。CMP工艺可部分或完全地移除硬掩模层224。
在形成层间介电层242后，将进行蚀刻工艺以移除组件区214及对准区212中栅极堆叠226、228及229的硅层222，其可为多晶硅层或非晶硅层。若前述CMP步骤未移除硬掩模层224，则此蚀刻工艺亦将移除硬掩模层224。在一实施例中，蚀刻工艺包含两个步骤，前段蚀刻是用以移除硬掩模层224，而后段蚀刻是用以移除组件区214与对准区212中栅极堆叠的硅层222。当堆叠结构中的硅层222被移除后，将形成沟槽(称作栅极沟槽)于层间介电层242中。
在一实施例中，若硬掩模层224含有氮化硅，用以移除硬掩模层224的前段蚀刻可采用磷酸、氢氟酸或缓冲氢氟酸。在另一实施例中，用以移除栅极堆叠226、228及229的硅层222的后段蚀刻可为适当的干蚀刻、湿蚀刻或上述的组合。在一实例中，用以移除多晶硅或非晶硅的蚀刻溶液可为硝酸、氢氟酸水溶液或氨水溶液。在另一实施例中，氯为主的等离子可用以选择性移除多晶硅。
在形成栅极沟槽后，于栅极沟槽中形成一或多个金属栅极材料层。在一实施例中，将具有适当功函数的金属层246(称作功函数金属)与导电材料层248填入栅极沟槽中。在一实施例中，功函数金属层246与导电材料层248将依序填入组件区214与对准区212的栅极沟槽中，以形成nFET的栅极。用于nFET之功函数金属246被称为n型金属。n型金属可为金属为主的导电材料，其功函数与nFET兼容。举例来说，n型金属的功函数小于或等于约4.2eV。在一实施例中，n型金属可为钽。在另一实施例中，n型金属可为氮化钛铝。在其它实施例中，n型金属可为钽、钛铝合金、氮化钛铝或上述的组合。n型金属亦可为多种金属为主的堆叠结构，以改良组件效能及工艺兼容度。n型金属层可由合适工艺如物理气相沉积法形成。导电材料层248可为铝、钨或其它合适金属。接着进行CMP工艺以移除多余的功函数金属246与导电材料248。在一实施例中，组件区214同时包含nFET与pFET。在此实施例中，将以适当工艺分别形成nFET与pFET的金属栅极。举例来说，在移除栅极堆叠226、228及229的硅层222后，可先以图案化光阻层保护pFET，接着沉积n型金属246、沉积导电材料层248以及进行CMP工艺移除多余的n型金属层246与导电材料层248，即形成nFET与对准标记的金属栅极。之后沉积p型金属层246、沉积导电材料层248、以及进行CMP工艺移除多余的p型金属层246及导电材料层248，即形成pFET的金属栅极。在其它实施例中，先以图案化光阻层保护nFET，再沉积pFET的p型金属层。当pFET被图案化光阻层保护时，再沉积nFET与对准标记的n型金属层。之后沉积导电材料层以填满nFET、pFET与对准标记的栅极沟槽。接着进行CMP工艺移除多余的n型金属层、p型金属层、以及导电材料层，即完成nFET、pFET、以及对准标记的金属栅极。
p型金属可为金属为主的导电材料，其功函数与pFET兼容。举例来说，p型金属的功函数大于或等于约5.2eV。在一实施例中，p型金属可为氮化钛或氮化钽。在其它实施例中，p型金属可为氮化钛、氮化钨、氮化钽或上述的组合。p型金属亦可为多种金属为主的堆叠结构，以改良组件效能及工艺兼容度。p型金属层可由适当工艺形成，比如物理气相沉积法(PVD)、化学气相沉积法、ALD、PE化学气相沉积法或PEALD。之后将导电材料实质上填入栅极沟槽中。导电材料可依据不同实施例采用铝或钨。导电材料的形成方法可为PVD、化学气相沉积法、ALD、PE化学气相沉积法、PEALD或旋转涂布法。接着可进行CMP工艺移除多余的功函数金属与导电材料，以形成金属栅极。虽然图标中的半导体结构200的组件区214只具有单一场效晶体管，但可于组件区214中形成多个场效晶体管与其它组件。用以形成金属栅极的工艺可置换为其它工艺。举例来说，nFET与pFET的金属栅极可由其它工艺或顺序完成。
在一实施例中，形成金属栅极的方法包含于栅极沟槽中的氧化层220上沉积高介电常数材料层244，接着形成功函数金属层246与导电材料层248于高介电常数材料层上224。上述方法被称作后制高介电常数材料工艺(high-k last)。在其它后制高介电常数材料的工艺中，在形成功函数金属层246与导电材料层248之前，先移除氧化硅层220。在这种情况下，会先形成新的界面层如氧化硅层，接着再形成高介电常数的介电材料层、功函数金属层与导电材料层于对应的栅极沟槽中。
如前所述，对准区212中的对准标记其栅极堆叠226与228会被置换成金属栅极。更明确的说，与组件区214中的nFET的金属栅极类似，栅极堆叠226与228中的硅层222会被置换为金属栅极。如此一来，对准区212的栅极堆叠将具有n型金属层与导电材料层。在另一实例中，与组件区214中的pFET的金属栅极类似，栅极堆叠226与228中的硅层222会被置换为金属栅极。在此例中，对准区212的栅极堆叠将具有p型金属层与导电材料层。
在另一实施例中，作为对准区212中对准标记的栅极堆叠仍为多晶硅栅极堆叠而不进行上述置换成金属栅极的工艺。在此例中，当组件区214中的组件，其栅极因置换栅极工艺改变为金属时，图案化掩模如图案化光阻层或图案化硬掩模层将覆盖对准区212使其不受栅极置换工艺影响，如图9所示。
如图1及10所示，方法100的步骤112接着形成接点孔(contact hole，未示于图上)作为电性内连线。在一实施例中，接触蚀刻停止层(CESL)250形成于层间介电层242上，而另一层间介电层252形成于接触蚀刻停止层250之上。接着涂布光阻层(未图标)于半导体结构上以进行微影工艺，并软烤涂布的光阻层。接着将具有接点孔图案的光罩置于微影曝光装置上，并将半导体结构固定于微影曝光装置的晶片平台上。在曝光涂布后的光阻层之前，先将光罩对准半导体结构200。对准步骤是依据对准区212中的对准标记，比如栅极堆叠226与228。对准标记将搭配图11作更详细的说明。图11是图8的半导体结构的对准标记(亦即对准区212)上视图。在图11中，对准标记的标号为260。对准标记260是形成于图8的对准区212中。对准标记260除了栅极堆叠226与228以外，还可包含额外栅极堆叠以组成光栅对准标记。在一实施例中，栅极堆叠的厚度为约1.6微米，而两个相邻的栅极堆叠间距为约1.6微米。
在另一实施例中，对准标记260可包含第二组的栅极堆叠构成类似的光栅结构，且第二组栅极堆叠是用于垂直方向的对准步骤。在一实施例中，第二组栅极堆叠的方向垂直于栅极堆叠226与228的方向。在另一实施例中，第二组栅极堆叠的方向与栅极堆叠226及228相同，差异在于相邻的栅极堆叠的间距。
由于半导体基板210经过一或多道掺杂工艺如LDD掺杂、重掺杂S/D及/或环形掺杂，其折射率已不同于掺杂前的半导体基板210，这将实质上增加对准信号的强度。所谓的晶片质量(wafer quality；WQ)可由对准信号的质量定量。WQ是实际上的信号强度与基准标记产生的信号比值。在一实施例中，WQ的定义如下式：
WQ＝(SSalign/Gainalign)/(SSref/Gainref)
在上式中，SSalign为来自对准标记的对准信号强度。Gainalign为对准信号的增益信号强度。SSref为来自基准标记的标准信号强度。Gainref为标准信号的增益强度。
一般来说，为了得到可信赖的对准结果，WQ的值需大于1％。在一实例中，现有的对准结构其WQ小于1％，比如0.3％。在上述揭露的对准标记结构中，WQ被提升到大于1％。在另一实例中，当对准光源的波长为约633nm时，WQ是大于3％。在又一实施例中，当对准源的波长为约532nm时，WQ是大于8％。
在对准步骤中，半导体结构200(或晶片)是置于晶片平台上，并采用上述的对准结构对准光罩与晶片。在对准后即曝光涂布的光阻。在对准光罩的接点图案与其它结构如栅极堆叠、源极与漏极结构后，接着可进行其它微影工艺如曝光后烘烤(PEB)、显影与硬烤以形成图案化光阻层。之后进行蚀刻工艺至层间介电层242与252，以形成接点孔于层间介电层中。接着可进行其它工艺步骤。在另一实施例中，可将导电材料如钨填入接点孔中以形成接点。在一实施例中，可先形成金属硅化物于半导体基板上以降低接点电阻后，再将导电材料填入接点孔中以形成接点。之后可进行化学机械研磨工艺以移除额外的导电材料层。
虽然未图示，但本发明的其它实施例仍可采用其它特征或工艺步骤。在一实施例中，组件区214包含其它组件如静态随机存取内存(SRAM)单元。在一实例中，SRAM单元具有交叉耦合的nFET与pFET，并可进一步具有其它晶体管作为通道栅极。在另一实施例中，FET可设计并作为其它应用，比如影像侦测器。在另一实施例中，半导体基板200具有多个对准区。举例来说，每一个晶粒(die)区域均具有一个对准标记。在曝光工艺中，每一个晶粒区域中的对准标记将用以对准光阻与晶粒区域。接着以微影光源曝光晶粒区域。上述工艺将重复进行于晶片的其它晶粒区域。在另一实施例中，可形成两个或多个对准标记于晶片的不同位置，而对准工艺将通过不同对准标记传回的对准信号平均值来进行。接着，整片晶片将以步进方式进行扫描或曝光。在另一实施例中，组件区214中的nFET包含p型井区，而pFET则包含n型井区。在另一实施例中，组件区214包含p型单元与n型单元的离子布植结构，以应用于SRAM组件。P型单元和n型单元的离子布植结构与p型井区和n型井区类似，差异在于掺杂剂量和浓度不同。在另一实施例中，对准标记是形成于半导体基板210上。举例来说，对准标记包含多个STI结构形成于对准区中，且STI结构可作为光栅，其组态类似于图11所示的对准标记260。
在另一实施例中，p型金属层与n型金属层的形成顺序不同，比如先形成n型金属层再形成p型金属层。在另一实施例中，pFET具有应力结构以增加其载子移动率并改善组件效能。在进一步的实施例中，可形成硅锗合金(SiGe)于pFET的源极/漏极区，使其具有适当的应力效应。在形成上述具有应力的pFET的实施例中，以一或多道蚀刻步骤蚀刻pFET的源极/漏极区的硅基板，使其凹陷。接着磊晶成长SiGe于凹陷区中，并形成重掺杂源极/漏极区于磊晶成长的SiGe结构中。在另一实例中，在形成LDD结构后接着形成虚置间隙壁，并在形成SiGe结构后移除虚置间隙壁。接着在对应的栅极堆叠侧壁上形成主要间隙壁。主要间隙壁与虚置间隙壁之间的厚度差异可让SiGe结构补偿重掺杂源极/漏极。举例来说，主要间隙壁比虚置间隙壁厚，因此重掺杂源极/漏极会形成于SiGe结构中。
在另一实施例中，nFET具有应力结构以增加载子移动律并改善组件效能。在进一步的实施例中，可形成碳化硅(SiC)于nFET的源极/漏极区，使其具有适当的应力效应。使nFET具有应力的方法与使pFET具有应力的方法类似。在另一实施例中，n型金属层与p型金属层各自具有适当的金属或合金。在另一实施例中，n型金属层与p型金属层各自具有多层结构，以最佳化其功函数并降低其临界电压。
在形成栅极堆叠(如226及228)之前、之中及(或)之后可进行其它工艺步骤。举例来说，在步骤112之后可进一步形成多层内连线。多层内连线包含垂直内连线如已知导孔，以及水平内连线如金属线路。上述内连线结构可采用多种导电材料如铜、钨或金属硅化物。在一实施例中，可采用镶嵌工艺以形成含铜的多层内连线结构。
在一实例中，高介电常数的介电材料层可由其它合适方法形成，比如有机金属化学气相沉积法(metal organic chemical vapor deposition；MOCVD)或分子束磊晶(molecular beam epitaxy；MBE)。在一实施例中，高介电常数的介电材料包含氧化铪。在另一实施例中，高介电常数的介电材料包括氧化铝。在其它实施例中，高介电常数的介电材料层包含金属氮化物、金属硅酸盐或其它金属氧化物。在另一实例中，界面层如氧化硅可形成于半导体基板上，其形成方法可为热氧化法、ALD、紫外线-臭氧氧化法或其它合适方法。在另一实例中，盖层可形成于高介电常数的介电材料层与n型金属层(或p型金属层)之间。
在前述的又一实施例中，在移除多晶硅层后可形成高介电常数的介电材料层于栅极堆叠中。举例来说，图1的步骤106所形成的介电材料层220如氧化硅层可视作虚置氧化层，接着形成高介电常数的介电层-金属栅极的堆叠，将高介电常数的介电材料层及金属层填入栅极沟槽。如此一来，高介电常数的介电层-金属栅极的堆叠亦称作完全置换栅极。
多种图案化工艺可包含以微影工艺形成图案化光阻层。举例来说，微影工艺可包含旋转涂布光阻、软烤、对准光罩、曝光、曝光后烘烤、显影与硬烤。微影工艺亦可加入或置换为其它合适方法如无光罩微影工艺、电子束直写、离子束直写、热微影或分子转印。
本发明并不限于半导体结构如FET(金属氧化物半导体晶体管)或SRAM，并可进一步应用于其它具有金属栅极堆叠与对准标记的集成电路。举例来说，半导体结构可包含动态随机存取内存(DRAM)单元、影像侦测器、电容及/或其它通称为微电子组件的组件。在另一实施例中，半导体结构包含鳍状场效晶体管(FinFET)。可以确定的是，本发明亦可应用于其它种类的晶体管如单栅极晶体管、双栅极晶体管或其它多栅极晶体管，亦可应用于其它组件如侦测单元、存储单元、逻辑单元或其它单元。
虽然本发明已以实施方式揭露如上，然其并非用以限定本发明，任何熟习此技艺者，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视所附的权利要求书所界定的范围为准。

Claims (3)

1.一种半导体结构的形成方法，其特征在于，包括：
提供一半导体基板，其具有一组件区与一对准区；
进行一第一离子布植至该半导体基板的该组件区中，同时以一布植掩模层覆盖该对准区，该第一离子布植是择自井区布植、临界电压布植与上述的组合；
接着形成一第一多晶硅栅极堆叠于该组件区中，与一第二多晶硅栅极堆叠于该对准区中；以及
接着进行一第二离子布植至该半导体基板的该组件区与该对准区，该第二离子布植的步骤会调整该半导体基板的折射率，且会将来自该对准区的对准信号的晶片质量提升至大于1％，其中所述的晶片质量(WQ)的定义如下式：
WQ=(SSalign／Gainalign)／(SSref/Gainref)
在上式中，SSalign为来自对准标记的对准信号强度，Gainalign为对准信号的增益信号强度，SSref为来自基准标记的标准信号强度，Gainref为标准信号的增益强度。
2.根据权利要求1所述的半导体结构的形成方法，其特征在于，还包括：
形成一层间介电材料层于该半导体基板上；
将该第一与第二多晶硅栅极堆叠置换为金属栅极堆叠；
形成一接触蚀刻停止层于该第一层间介电材料层上；
形成一另一层间介电材料层于该接触蚀刻停止层上；
涂布一光阻层于该另一层间介电材料层上；
根据来自对准区的对准信号，将光罩对准该半导体基板；以及
以该光罩的接点图案曝光该光阻层。
3.根据权利要求1所述的半导体结构的形成方法，其特征在于，该第二离子布植的掺杂剂量大于1014离子数／cm2。
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