CN105990145B - 一种半导体器件及其制作方法和电子装置 - Google Patents

一种半导体器件及其制作方法和电子装置 Download PDF

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CN105990145B
CN105990145B CN201510058467.6A CN201510058467A CN105990145B CN 105990145 B CN105990145 B CN 105990145B CN 201510058467 A CN201510058467 A CN 201510058467A CN 105990145 B CN105990145 B CN 105990145B
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gate trench
coating
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dielectric layer
thickness
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CN105990145A (zh
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李勇
王小娜
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明提供一种半导体器件及其制作方法和电子装置，所述制作方法包括：提供半导体衬底，所述半导体衬底上形成有伪栅极结构及位于所述伪栅极结构两侧壁上的偏移侧墙；去除所述伪栅极结构，以形成栅极沟槽；步骤三：在所述栅极沟槽的底部和侧壁沉积形成高k介电层；在所述高k介电层上形成覆盖层，所述覆盖层位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层位于所述栅极沟槽底部中间区域的厚度。根据本发明的制作方法，适当的增大栅极沟槽底部拐角处的覆盖层的厚度，有效抑制拐角处金属栅极的铝扩散，进而提高了器件的可靠性和性能。

Description

一种半导体器件及其制作方法和电子装置
技术领域
本发明涉及半导体技术领域，具体而言涉及一种半导体器件及其制作方法和电子装置。
背景技术
在下一代集成电路的制造工艺中，对于金属氧化物半导体(MOS)的栅极的制作，通常采用高k-金属栅极工艺。
无论是先金属栅极还是后金属栅极，铝扩散一直是影响器件可靠性和性能的主要问题之一，例如对与时间相关电介质击穿(Time Dependent Dielectric Breakdown，简称TDDB)、负偏压温度不稳定性(Negative Bias Temperature Instability，简称NBTI)，正偏压温度不稳定性(Positive Bias Temperature Instability，简称PBTI)等可靠性造成负面影响，同时铝扩散还会影响载流子的迁移率，降低器件的性能。
铝扩散往往有两个路径，一个是在栅极沟槽的中间区域，另一个是栅极沟槽的侧壁。通常，N型功函数金属层是采用PVD法沉积形成的TiAl，它具有很强的张应力，沉积和热处理后，在栅极沟槽底部的中间位置其呈“弓”形，如图1所示，使得位于沟槽中间位置的膜层厚，而接近侧壁位置的膜层比较薄，导致金属栅极的铝金属很容易从沟槽的侧壁向下扩散，造成器件的可靠性和性能不断下降。
因此，有必要提出一种新的制作方法，以解决现有技术的不足。
发明内容
在发明内容部分中引入了一系列简化形式的概念，这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征，更不意味着试图确定所要求保护的技术方案的保护范围。
为了克服目前存在的问题，本发明提供一种半导体器件的制作方法，包括：
步骤一：提供半导体衬底，所述半导体衬底上形成有伪栅极结构及位于所述伪栅极结构两侧壁上的偏移侧墙；
步骤二：去除所述伪栅极结构，以形成栅极沟槽；
步骤三：在所述栅极沟槽的底部和侧壁沉积形成高k介电层；
步骤四：在所述高k介电层上形成覆盖层，所述覆盖层位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层位于所述栅极沟槽底部中间区域的厚度。
进一步，位于所述栅极沟槽底部拐角处的覆盖层的厚度比位于所述栅极沟槽底部中间区域的覆盖层的厚度厚3～30埃。
进一步，形成所述覆盖层的方法包括：
在所述高k介电层上沉积形成覆盖层；
对所述覆盖层进行磁控溅射，以使得所述覆盖层位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层位于所述栅极沟槽底部中间区域的厚度。
进一步，所述磁控溅射采用软氩气作为溅射气体。
进一步，沉积形成所述覆盖层的方法为原子层沉积法，所述覆盖层的材料为TiN。
进一步，在所述步骤四之后还包括步骤五：回蚀刻去除位于所述栅极沟槽侧壁上的覆盖层。
进一步，在所述步骤四之后和所述步骤五之前，还包括在所述栅极沟槽底部的覆盖层上方形成牺牲材料层的步骤。
进一步，所述牺牲材料层为深紫外线吸收氧化层。
进一步，形成所述深紫外线吸收氧化层的步骤包括：在所述栅极沟槽内形成深紫外线吸收氧化物材料；回蚀刻所述深紫外线吸收氧化物材料。
进一步，所述深紫外线吸收氧化层的厚度为3～10nm。
进一步，在所述步骤一之后和所述步骤二之前，还包括以下步骤：
实施轻掺杂离子注入，以在所述半导体衬底中形成低掺杂源/漏区；
在所述半导体衬底上所述伪栅极结构的两侧分别执行口袋注入工艺，形成口袋区；
在所述伪栅极结构两侧源/漏区生长应力层；
在所述半导体衬底上形成覆盖所述伪栅极结构和所述偏移侧墙的层间介电层；
执行化学机械研磨平坦化所述层间介电层，直至露出所述伪栅极结构的顶部。
进一步，在所述步骤四之后，还包括以下步骤：
在所述覆盖层上依次形成阻挡层和功函数金属层；
在所述功函数金属层上形成填充所述栅极沟槽的金属栅极。
进一步，在形成所述高k介电层之前，还包括在所述栅极沟槽的底部形成界面层的步骤。
本发明实施例二提供一种半导体器件，包括：
半导体衬底，位于所述半导体衬底上的层间介电层；
位于所述层间介电层内的栅极沟槽，位于所述栅极沟槽两侧的紧靠所述层间介电层的偏移侧墙，以及位于所述栅极沟槽两侧所述半导体衬底中的源/漏区的应力层；
位于所述栅极沟槽侧壁和底部上的高k介电层；
位于所述栅极沟槽底部的高k介电层上的覆盖层，其中位于所述栅极沟槽底部拐角处的部分覆盖层的厚度大于位于所述栅极沟槽底部中间区域的覆盖层的厚度。
进一步，所述半导体器件还包括：
依次位于所述高k介电层和所述覆盖层上的阻挡层和功函数金属层；
位于所述功函数金属层上填充所述栅极沟槽的金属栅极。
进一步，位于所述栅极沟槽底部拐角处的部分覆盖层的厚度比位于所述栅极沟槽底部中间区域的覆盖层的厚度厚3～30埃。
进一步，所述覆盖层为TiN。
进一步，所述金属栅极的材料为Al。
本发明实施例三提供一种电子装置，包括半导体器件以及与所述半导体器件相连接的电子组件，其中所述半导体器件包括：
半导体衬底，位于所述半导体衬底上的层间介电层；
位于所述层间介电层内的栅极沟槽，位于所述栅极沟槽两侧的紧靠所述层间介电层的偏移侧墙，以及位于所述栅极沟槽两侧所述半导体衬底中的源/漏区的应力层；
位于所述栅极沟槽侧壁和底部上的高k介电层；
位于所述栅极沟槽底部的高k介电层上的覆盖层，其中位于所述栅极沟槽底部拐角处的部分覆盖层的厚度大于位于所述栅极沟槽底部中间区域的覆盖层的厚度。
综上所述，根据本发明的制作方法，适当的增大栅极沟槽底部拐角处的覆盖层的厚度，有效抑制拐角处金属栅极的铝扩散，同时通过去除栅极沟槽侧壁上的覆盖层来增强金属栅极材料的填充能力，进而提高了器件的可靠性和性能。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述，用来解释本发明的原理。
附图中：
图1示出了现有的金属栅极功函数金属层的扫描电镜示意图；
图2A-2E示出了根据本发明的制作方法依次实施步骤形成的器件的剖面示意图；
图3示出了根据本发明的制作方法依次实施步骤的工艺流程图；
图4示出了本发明实施例二中半导体器件的剖面示意图。
具体实施方式
在下文的描述中，给出了大量具体的细节以便提供对本发明更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本发明可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本发明发生混淆，对于本领域公知的一些技术特征未进行描述。
应当理解的是，本发明能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本发明的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本发明，将在下列的描述中提出详细的结构及步骤，以便阐释本发明提出的技术方案。本发明的较佳实施例详细描述如下，然而除了这些详细描述外，本发明还可以具有其他实施方式。
实施例一
下面将参照图2A-2E及图3对本发明的半导体器件的制作方法做详细描述。
首先，如图2A所示，提供半导体衬底200，半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，半导体衬底200的构成材料选用单晶硅。
在半导体衬底200中形成有隔离结构201，隔离结构201可以为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，在本实施例中，隔离结构较佳地为浅沟槽隔离结构。隔离结构201将半导体衬底200分为NFET区和PFET区。半导体衬底200中还形成有各种阱(well)结构，为了简化，图示中予以省略。
在半导体衬底200上形成有伪栅极结构202，较佳地，所述伪栅极结构具有栅极足部。伪栅极结构202包括自下而上层叠的牺牲栅介电层和牺牲栅电极层。牺牲栅介电层的材料较佳地为氧化物，例如二氧化硅。牺牲栅电极层的材料包括多晶硅或无定形碳，较佳地是多晶硅。牺牲栅介电层和牺牲栅电极层的形成方法可以采用本领域技术人员所熟习的任何现有技术，优选化学气相沉积法(CVD)，如低温化学气相沉积(LTCVD)、低压化学气相沉积(LPCVD)、快热化学气相沉积(RTCVD)、等离子体增强化学气相沉积(PECVD)。
在一个示例中，形成所述伪栅极结构202的方法为：依次在半导体衬底上沉积形成牺牲栅介电层和牺牲栅电极层，在所述牺牲栅电极层上形成图案化的光刻胶层，所述光刻胶层定义了所述伪栅极的形状以及关键尺寸的大小，以所述光刻胶层为掩膜蚀刻牺牲栅电极层以及牺牲栅介电层，形成伪栅极结构202。然后去除所述光刻胶层。上述伪栅极结构202的形成方法仅是示例性地，其他任何形成伪栅极结构的方法均可适用于本发明。
在伪栅极结构202的两侧壁上形成有紧靠伪栅极结构202的偏移侧墙(offsetspacer)203。所述偏移侧墙203的材料例如是氮化硅，氧化硅或者氮氧化硅等绝缘材料。在本实施例中，偏移侧墙203为氧化物和氮化物的叠层。在伪栅极结构202两侧形成偏移侧墙203的工艺可以为本领域技术人员熟知的任何工艺，例如化学气相沉积。在偏移侧墙203沉积的过程中不可避免的在伪栅极结构202的上方也会形成偏移侧墙，但其会在之后的制程中被化学机械研磨或刻蚀去除。
参考图2B，在所述伪栅极结构202两侧源/漏区生长应力层204。
在形成应力层204之前，可先实施轻掺杂离子(LDD)注入，以在半导体衬底中形成低掺杂源/漏区(图中未示出)。执行LDD注入的步骤，所述形成LDD的方法可以是离子注入工艺或扩散工艺。所述LDD注入的离子类型根据将要形成的半导体器件的电性决定，即形成的器件为NMOS器件，则LDD注入工艺中掺入的杂质离子为磷、砷、锑、铋中的一种或组合；若形成的器件为PMOS器件，则注入的杂质离子为硼。根据所需的杂质离子的浓度，离子注入工艺可以一步或多步完成。
然后在半导体衬底200上所述伪栅极结构202的两侧分别执行口袋注入工艺(PKT，Pocket implantation)，形成口袋区，用于防止短沟道效应。口袋注入的元素类型可以为，P型元素氟化硼或硼，N型元素磷或砷。所述口袋注入的离子类型根据将要形成的半导体器件的电性决定。
在本发明中为了激活杂质又能抑制杂质的深度和横向扩散，执行完所述离子注入后进行尖峰退火(Spike Anneal)，可选地，所述尖峰退火温度为1000-1050℃。
然后在所述伪栅极结构202两侧源/漏区生长应力层204，在CMOS晶体管中，通常在NMOS晶体管上形成具有拉应力的应力层，在PMOS晶体管上形成具有压应力的应力层，CMOS器件的性能可以通过将所述拉应力作用于NMOS，压应力作用于PMOS来提高。现有技术中在NMOS晶体管中通常选用SiC作为拉应力层，在PMOS晶体管中通常选用SiGe作为压应力层。
作为优选，生长所述SiC作为拉应力层时，可以在所述衬底上外延生长，在离子注入后形成抬升源漏，在形成所述SiGe层时，通常在所述衬底中形成凹槽，然后在所述凹槽中沉积形成SiGe层。更优选，在所述衬底中形成“∑”形凹槽。
在本发明的一实施例中，可以选用干法蚀刻所述源/漏区以形成凹槽，在所述干法蚀刻中可以选用CF4、CHF3，另外加上N2、CO2、O2中的一种作为蚀刻气氛，其中气体流量为CF410-200sccm，CHF310-200sccm，N2或CO2或O210-400sccm，所述蚀刻压力为30-150mTorr，蚀刻时间为5-120s，优选为5-60s，更优选为5-30s。然后在所述凹槽中外延生长SiGe层；所述外延可以选用减压外延、低温外延、选择外延、液相外延、异质外延、分子束外延中的一种。
参考图2C，在半导体衬底200上形成覆盖伪栅极结构202、偏移侧墙203的层间介电层205，执行化学机械研磨研磨层间介电层205，直至露出伪栅极结构202的顶部。
形成层间介电层205可以采用本领域技术人员所熟习的各种适宜的工艺，例如化学气相沉积工艺。层间介电层205可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介电层也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。需要说明的是，在形成层间介电层205之前，还要先形成接触孔蚀刻停止层，采用共形沉积工艺形成接触孔蚀刻停止层，以使形成的接触孔蚀刻停止层具有良好的阶梯覆盖特性，接触孔蚀刻停止层的材料优选氮化硅。
接着，如图2D所示，去除伪栅极结构202，形成栅极沟槽206。在本实施例中，通过实施干法蚀刻，依次去除牺牲栅电极层和牺牲栅介电层。所述干法蚀刻的工艺参数包括：蚀刻气体HBr的流量为20-500sccm，压力为2-40mTorr，功率为100-2000W，其中mTorr代表毫毫米汞柱，sccm代表立方厘米/分钟。在实施所述干法蚀刻之后，采用湿法蚀刻工艺去除所述干法蚀刻产生的蚀刻残留物和杂质。
继续参考图2D，在栅极沟槽206的底部形成界面层(IL)，在栅极沟槽的底部的界面层上及栅极沟槽的侧壁上沉积形成高K(HK)介电层207。
界面层的构成材料包括硅氧化物(SiOx)，形成界面层的作用是改善高k介电层207与半导体衬底200之间的界面特性。IL层的可以为热氧化层、氮的氧化物层、化学氧化层或者其他适合的薄膜层。可以采用热氧化、CVD、ALD或者PVD等适合的工艺形成界面层。界面层的厚度范围为5埃至10埃。
高k介电层207的k值(介电常数)通常为3.9以上，其构成材料包括氧化铪、氧化铪硅、氮氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化铝等，较佳地是氧化铪、氧化锆或氧化铝。可以采用CVD、ALD或者PVD等适合的工艺形成高K介电层。高K介电层204的厚度范围为10埃至30埃。
参考图2D，在所述高k介电层207上形成覆盖层208，所述覆盖层208位于所述栅极沟槽206底部拐角处的厚度大于所述覆盖层208位于所述栅极沟槽206底部中间区域的厚度。
在一个示例中，形成所述覆盖层的方法包括：在所述高k介电层上沉积形成覆盖层；对所述覆盖层进行磁控溅射，以使得所述覆盖层位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层位于所述栅极沟槽底部中间区域的厚度。
覆盖层208的材料可以为La2O3、Al2O3、Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-x或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺沉积形成覆盖层208，较佳地，沉积形成所述覆盖层的方法为原子层沉积法。本实施例中，较佳地所述覆盖层208的材料为TiN。首先沉积的覆盖层208的厚度约5埃至50埃，上述厚度范围的数值仅是示例性地，还可根据实际工艺进行调整，本实施例中可以适当的增加覆盖层208的厚度，在经过之后的磁控溅射工艺后，还能使得位于栅极沟槽底部中间区域的覆盖层保留一定的厚度，示例性地，控制剩余栅极沟槽底部中间区域的覆盖层的厚度约为5到30埃。
对所述覆盖层208进行磁控溅射，以使得所述覆盖层208位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层208位于所述栅极沟槽底部中间区域的厚度。可选地，所述磁控溅射采用软氩气作为溅射气体。示例性地，以所述覆盖层208为TiN为例，将半导体衬底安装在溅射靶台上，抽真空，向溅射室内通入Ar气，其流量约为20～40cm3/min左右，例如25cm3/min、30cm3/min、35cm3/min，使溅射室内气压约为0.5～1.5pa，辉光放电后对覆盖层208进行溅射，位于栅极沟槽底部中间区域的部分覆盖层208被氩气轰击溅射去除，而相应的减薄了栅极沟槽底部中间区域的覆盖层208的厚度，被轰击的覆盖层原子还可能会在拐角处的覆盖层上堆积沉积，进而使得所述覆盖层208位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层208位于所述栅极沟槽底部中间区域的厚度。示例性地，位于所述栅极沟槽底部拐角处的覆盖层的厚度比位于所述栅极沟槽底部中间区域的覆盖层的厚度厚约3到30埃，例如3埃、5埃、10埃、15埃、20埃、25埃、30埃等，上述数值范围仅是示例性地，还可根据实际工艺进行适当调整。
参考图2E，在所述栅极沟槽206底部的覆盖层208上方形成牺牲材料层209。所述牺牲材料层209可以为深紫外线吸收氧化层(DUV Light Absorbing Oxide，简称DUO)或无定形碳等。较佳地，所述牺牲材料层209为较薄的深紫外线吸收氧化层。所述DUO层209一般可以采用硅氧烷聚合物(siloxane polymer)等高分子材料，用于实现以下功能：用于曝光过程中的抗反射，提供较高的蚀刻选择比，用以保证临界尺寸；提供平坦的表面，用以保证统一的抗反射性能，同时对栅极沟槽底部的覆盖层起到保护作用。在一个示例中，形成所述较薄的DUO层209的方法可以为：在所述栅极沟槽206内形成深紫外线吸收氧化物材料；回蚀刻所述深紫外线吸收氧化物材料，以在所述栅极沟槽206底部的覆盖层208上方形成较薄的深紫外线吸收氧化层209。
所述较薄的DUO层209的厚度范围取决于实际工艺中形成于栅极沟槽206底部的覆盖层208的厚度，所述较薄的DUO层209的厚度范围为3～10nm，例如为3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm等。较佳地，本实施例中所述较薄的DUO层209的厚度约为5nm。
继续参考图2E，回蚀刻去除位于所述栅极沟槽206侧壁上的覆盖层208，以增大栅极沟槽206的填充宽度。
所述回蚀刻具有所述覆盖层208对高k介电层207高的蚀刻选择比。所述回蚀刻工艺可以为干法蚀刻工艺，干法蚀刻工艺包括但不限于：反应离子蚀刻(RIE)、离子束蚀刻、等离子体蚀刻或者激光切割。所述干法蚀刻的源气体可以包括Cl2、BCl3、Ar、N2、CHF3、CH4和C2H4等。作为示例，在本实施例中，所述回蚀刻为干法蚀刻，所述干法蚀刻的工艺参数包括：蚀刻气体包含Cl2、BCl3和CH4，其流量分别为50sccm-500sccm、10sccm-100sccm和2sccm-20sccm，压力为2mTorr-50mTorr，其中，sccm代表立方厘米/分钟，mTorr代表毫毫米汞柱。所述回蚀刻工艺还可以为任何具有所述覆盖层208对高k介电层207高的蚀刻选择比的湿法刻蚀工艺。
回蚀刻去除位于所述栅极沟槽206侧壁上的覆盖层208的目的在于增大栅极沟槽206的宽度，减小栅极沟槽的深宽比，利于之后金属栅极材料的填充。
回蚀刻后可去除牺牲材料层209，以进行之后的制程，去除牺牲材料层209的方法可以采用本领域技术人员熟知的任何方法，在此不作赘述。
之后，还包括以下步骤：在所述栅极沟槽底部的覆盖层、栅极沟槽侧壁的高k介电层上依次形成阻挡层和功函数金属层；在所述功函数金属层上形成填充所述栅极沟槽的金属栅极。
阻挡层的材料可以选择为TaN，Ta，TaAl或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成阻挡层。阻挡层的厚度范围为5埃至40埃。
在PMOS区域内的阻挡层上形成P型功函数金属层，P型功函数金属层为PMOS功函数金属可调层，P型功函数金属层(PWF)的材料可以选择为但不限于TixN1-x、TaC、MoN、TaN或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成P型功函数金属层。P型功函数金属层的厚度范围为10埃至580埃。
在NMOS区域内的阻挡层上形成N型功函数金属层，N型功函数金属层(NWF)为NMOS功函数金属可调层，N型功函数金属层的材料可以选择为但不限于TaC、Ti、Al、TixAl1-x或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成N型功函数金属层。N型功函数金属层的厚度范围为10埃至80埃。
最后，在所述功函数金属层上形成填充所述栅极沟槽的金属栅极。金属栅极的材料可以选择为但不限于Al、W或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成金属栅极。至此完成了金属栅极制作的主要制程。
由于采用物理气相沉积形成的功函数金属层(例如N型功函数金属层TiAl)具有很强的张应力，在之后的沉积或热处理制程中，功函数金属层很容易产生变形，形成位于栅极沟槽底部的“弓”形，使得功函数金属层位于栅极沟槽底部中间的厚度比靠近侧壁的位置厚，因此栅极沟槽侧壁拐角处的金属栅极的铝很容易向下扩散进入衬底，而降低器件的可靠性和整体性能。而根据本发明的制作方法，适当的增大栅极沟槽底部拐角处的覆盖层的厚度，有效抑制拐角处金属栅极的铝扩散，同时通过去除栅极沟槽侧壁上的覆盖层来增强金属栅极材料的填充能力，进而提高了器件的可靠性和性能。
参照图3，示出了本发明一个具体实施方式依次实施的步骤的工艺流程图，用于简要示出整个制作工艺的流程。
在步骤301中，提供半导体衬底，所述半导体衬底上形成有伪栅极结构及位于所述伪栅极结构两侧壁上的偏移侧墙；
在步骤302中，去除所述伪栅极结构，以形成栅极沟槽；
在步骤303中，在所述栅极沟槽的底部和侧壁沉积形成高k介电层；
在步骤304中，在所述高k介电层上形成覆盖层，所述覆盖层位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层位于所述栅极沟槽底部中间区域的厚度。
实施例二
本发明还提供采用实施例一种方法制作的半导体器件。
参考图4，所述半导体器件包括半导体衬底。半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。作为示例，半导体衬底200的构成材料选用单晶硅。
在半导体衬底200中形成有隔离结构201，隔离结构201可以为浅沟槽隔离(STI)结构或者局部氧化硅(LOCOS)隔离结构，在本实施例中，隔离结构较佳地为浅沟槽隔离结构。隔离结构201将半导体衬底200分为NFET区和PFET区。半导体衬底200中还形成有各种阱(well)结构，为了简化，图示中予以省略。
还包括位于所述半导体衬底上的层间介电层205。层间介电层205可为氧化硅层，包括利用热化学气相沉积(thermal CVD)制造工艺或高密度等离子体(HDP)制造工艺形成的有掺杂或未掺杂的氧化硅的材料层，例如未经掺杂的硅玻璃(USG)、磷硅玻璃(PSG)或硼磷硅玻璃(BPSG)。此外，层间介电层205也可以是掺杂硼或掺杂磷的自旋涂布式玻璃(spin-on-glass，SOG)、掺杂磷的四乙氧基硅烷(PTEOS)或掺杂硼的四乙氧基硅烷(BTEOS)。
还包括位于所述层间介电层205内的栅极沟槽206，位于栅极沟槽206两侧的紧靠所述层间介电层205的偏移侧墙203，以及位于所述栅极沟槽206两侧半导体衬底200中的源/漏区的应力层204。所述偏移侧墙203的材料例如是氮化硅，氧化硅或者氮氧化硅等绝缘材料。在本实施例中，偏移侧墙203为氧化物和氮化物的叠层。在CMOS晶体管中，通常在NMOS晶体管上形成具有拉应力的应力层，在PMOS晶体管上形成具有压应力的应力层，CMOS器件的性能可以通过将所述拉应力作用于NMOS，压应力作用于PMOS来提高。现有技术中在NMOS晶体管中通常选用SiC作为拉应力层，在PMOS晶体管中通常选用SiGe作为压应力层。
还包括位于所述栅极沟槽206底部的界面层以及位于界面层上和栅极沟槽206的侧壁上的高k介电层207。界面层的构成材料包括硅氧化物(SiOx)，形成界面层的作用是改善高k介电层207与半导体衬底200之间的界面特性。IL层的可以为热氧化层、氮的氧化物层、化学氧化层或者其他适合的薄膜层。可以采用热氧化、CVD、ALD或者PVD等适合的工艺形成界面层。界面层的厚度范围为5埃至10埃。
高k介电层207的k值(介电常数)通常为3.9以上，其构成材料包括氧化铪、氧化铪硅、氮氧化铪硅、氧化镧、氧化锆、氧化锆硅、氧化钛、氧化钽、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化铝等，较佳地是氧化铪、氧化锆或氧化铝。可以采用CVD、ALD或者PVD等适合的工艺形成高K介电层207。高K介电层207的厚度范围为10埃至30埃。
还包括位于所述栅极沟槽206底部的高k介电层207上的覆盖层208，其中位于所述栅极沟槽206底部拐角处的部分覆盖层208的厚度大于位于所述栅极沟槽206底部中间区域的覆盖层208的厚度。在一个示例中，位于所述栅极沟槽206底部拐角处的部分覆盖层208的厚度比位于所述栅极沟槽206底部中间区域的覆盖层208的厚度约3到30埃，例如3埃、5埃、10埃、15埃、20埃、25埃、30埃等。所述栅极沟槽206底部中间区域的覆盖层208的厚度范围约为5埃至20埃。覆盖层208的材料可以为La2O3、AL2O3、Ga2O3、In2O3、MoO、Pt、Ru、TaCNO、Ir、TaC、MoN、WN、TixN1-x或者其他适合的薄膜层。较佳地，本实施例中所述覆盖层208的材料为TiN。
还包括依次位于所述高k介电层和所述覆盖层上的阻挡层和功函数金属层。阻挡层的材料可以选择为TaN，Ta，TaAl或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成阻挡层。阻挡层的厚度范围为5埃至40埃。
在PMOS区域内的阻挡层上形成P型功函数金属层，P型功函数金属层为PMOS功函数金属可调层，P型功函数金属层(PWF)的材料可以选择为但不限于TixN1-x、TaC、MoN、TaN或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成P型功函数金属层。P型功函数金属层的厚度范围为10埃至580埃。
在NMOS区域内的阻挡层上形成N型功函数金属层，N型功函数金属层(NWF)为NMOS功函数金属可调层，N型功函数金属层的材料可以选择为但不限于TaC、Ti、Al、TixAl1-x或者其他适合的薄膜层。可以采用CVD、ALD或者PVD等适合的工艺形成N型功函数金属层。N型功函数金属层的厚度范围为10埃至80埃。
还包括位于所述功函数金属层上填充所述栅极沟槽的金属栅极。金属栅极的材料可以选择为但不限于Al、W或者其他适合的薄膜层。
综上所述，根据本发明的半导体器件，其在栅极沟槽拐角处的覆盖层的厚度比较厚，可以有效抑制金属栅极的铝扩散，进而使得器件具有高的可靠性和性能。
实施例三
本发明实施例提供一种电子装置，包括半导体器件以及与所述半导体器件相连的电子组件。其中，该半导体器件为实施例二所述的半导体器件，或根据实施例一所述的半导体器件的制造方法所制得的半导体器件。该电子组件，可以为分立器件、集成电路等任何电子组件。
示例性地，所述电子装置包括半导体器件以及与所述半导体器件相连接的电子组件，其中所述半导体器件包括：半导体衬底，位于所述半导体衬底上的层间介电层；位于所述层间介电层内的栅极沟槽，位于所述栅极沟槽两侧的紧靠所述层间介电层的偏移侧墙，以及位于所述栅极沟槽两侧所述半导体衬底中的源/漏区的应力层；位于所述栅极沟槽侧壁和底部上的高k介电层；位于所述栅极沟槽底部的高k介电层上的覆盖层，其中位于所述栅极沟槽底部拐角处的部分覆盖层的厚度大于位于所述栅极沟槽底部中间区域的覆盖层的厚度。
由于包括的半导体器件具有更高的性能和可靠性，该电子装置同样具有上述优点。
该电子装置，可以是手机、平板电脑、笔记本电脑、上网本、游戏机、电视机、VCD、DVD、导航仪、照相机、摄像机、录音笔、MP3、MP4、PSP等任何电子产品或设备，也可以是具有上述半导体器件的中间产品，例如：具有该集成电路的手机主板等。
本发明已经通过上述实施例进行了说明，但应当理解的是，上述实施例只是用于举例和说明的目的，而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是，本发明并不局限于上述实施例，根据本发明的教导还可以做出更多种的变型和修改，这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (18)

1.一种半导体器件的制作方法，包括：
步骤一：提供半导体衬底，所述半导体衬底上形成有伪栅极结构及位于所述伪栅极结构两侧壁上的偏移侧墙；
步骤二：去除所述伪栅极结构，以形成栅极沟槽；
步骤三：在所述栅极沟槽的底部和侧壁沉积形成高k介电层；
步骤四：在所述高k介电层上沉积形成覆盖层，对所述覆盖层进行磁控溅射，位于所述栅极沟槽底部中间区域的部分所述覆盖层被轰击溅射去除以减薄所述栅极沟槽底部中间区域的覆盖层的厚度，被轰击的覆盖层原子在所述栅极沟槽底部拐角处的覆盖层上堆积沉积，以使得所述覆盖层位于所述栅极沟槽底部拐角处的厚度大于所述覆盖层位于所述栅极沟槽底部中间区域的厚度，从而抑制金属栅极的铝扩散；
在所述覆盖层上依次形成阻挡层和功函数金属层，其中，所述功函数金属层位于栅极沟槽底部中间区域的厚度比靠近侧壁的位置厚。
2.根据权利要求1所述的制作方法，其特征在于，位于所述栅极沟槽底部拐角处的覆盖层的厚度比位于所述栅极沟槽底部中间区域的覆盖层的厚度厚3～30埃。
3.根据权利要求1所述的制作方法，其特征在于，所述磁控溅射采用软氩气作为溅射气体。
4.根据权利要求1所述的制作方法，其特征在于，沉积形成所述覆盖层的方法为原子层沉积法，所述覆盖层的材料为TiN。
5.根据权利要求1所述的制作方法，其特征在于，在所述步骤四之后还包括步骤五：回蚀刻去除位于所述栅极沟槽侧壁上的覆盖层。
6.根据权利要求5所述的制作方法，其特征在于，在所述步骤四之后和所述步骤五之前，还包括在所述栅极沟槽底部的覆盖层上方形成牺牲材料层的步骤。
7.根据权利要求6所述的制作方法，其特征在于，所述牺牲材料层为深紫外线吸收氧化层。
8.根据权利要求7所述的制作方法，其特征在于，形成所述深紫外线吸收氧化层的步骤包括：在所述栅极沟槽内形成深紫外线吸收氧化物材料；回蚀刻所述深紫外线吸收氧化物材料。
9.根据权利要求7所述的制作方法，其特征在于，所述深紫外线吸收氧化层的厚度为3～10nm。
10.根据权利要求1所述的制作方法，其特征在于，在所述步骤一之后和所述步骤二之前，还包括以下步骤：
实施轻掺杂离子注入，以在所述半导体衬底中形成低掺杂源/漏区；
在所述半导体衬底上所述伪栅极结构的两侧分别执行口袋注入工艺，形成口袋区；
在所述伪栅极结构两侧源/漏区生长应力层；
在所述半导体衬底上形成覆盖所述伪栅极结构和所述偏移侧墙的层间介电层；
执行化学机械研磨平坦化所述层间介电层，直至露出所述伪栅极结构的顶部。
11.根据权利要求1所述的制作方法，其特征在于，在所述步骤四之后，还包括以下步骤：
在所述功函数金属层上形成填充所述栅极沟槽的金属栅极。
12.根据权利要求1所述的制作方法，其特征在于，在形成所述高k介电层之前，还包括在所述栅极沟槽的底部形成界面层的步骤。
13.一种如权利要求1至12中任一项所述的方法制备获得的半导体器件，包括：
半导体衬底，位于所述半导体衬底上的层间介电层；
位于所述层间介电层内的栅极沟槽，位于所述栅极沟槽两侧的紧靠所述层间介电层的偏移侧墙，以及位于所述栅极沟槽两侧所述半导体衬底中的源/漏区的应力层；
位于所述栅极沟槽侧壁和底部上的高k介电层；
位于所述栅极沟槽底部的高k介电层上的覆盖层，其中位于所述栅极沟槽底部拐角处的部分覆盖层的厚度大于位于所述栅极沟槽底部中间区域的覆盖层的厚度。
14.根据权利要求13所述的半导体器件，其特征在于，还包括：
依次位于所述高k介电层和所述覆盖层上的阻挡层和功函数金属层；
位于所述功函数金属层上填充所述栅极沟槽的金属栅极。
15.根据权利要求13所述的半导体器件，其特征在于，位于所述栅极沟槽底部拐角处的部分覆盖层的厚度比位于所述栅极沟槽底部中间区域的覆盖层的厚度厚3～30埃。
16.根据权利要求13所述的半导体器件，其特征在于，所述覆盖层为TiN。
17.根据权利要求14所述的半导体器件，其特征在于，所述金属栅极的材料为Al。
18.一种电子装置，其特征在于，包括如权利要求13至17中任一项所述的半导体器件以及与所述半导体器件相连接的电子组件，其中所述半导体器件包括：
半导体衬底，位于所述半导体衬底上的层间介电层；
位于所述层间介电层内的栅极沟槽，位于所述栅极沟槽两侧的紧靠所述层间介电层的偏移侧墙，以及位于所述栅极沟槽两侧所述半导体衬底中的源/漏区的应力层；
位于所述栅极沟槽侧壁和底部上的高k介电层；
位于所述栅极沟槽底部的高k介电层上的覆盖层，其中位于所述栅极沟槽底部拐角处的部分覆盖层的厚度大于位于所述栅极沟槽底部中间区域的覆盖层的厚度。
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