CN102208445B - 具有耗尽型mos晶体管的半导体装置 - Google Patents

具有耗尽型mos晶体管的半导体装置 Download PDF

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Publication number
CN102208445B
CN102208445B CN201110086411.3A CN201110086411A CN102208445B CN 102208445 B CN102208445 B CN 102208445B CN 201110086411 A CN201110086411 A CN 201110086411A CN 102208445 B CN102208445 B CN 102208445B
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CN
China
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low
region
concentration
type
impurity region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CN201110086411.3A
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English (en)
Chinese (zh)
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CN102208445A (zh
Inventor
原田博文
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Ablic Inc
Original Assignee
Seiko Instruments Inc
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Publication of CN102208445A publication Critical patent/CN102208445A/zh
Application granted granted Critical
Publication of CN102208445B publication Critical patent/CN102208445B/zh
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CN201110086411.3A 2010-03-29 2011-03-29 具有耗尽型mos晶体管的半导体装置 Expired - Fee Related CN102208445B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010076366A JP2011210901A (ja) 2010-03-29 2010-03-29 デプレッション型ｍｏｓトランジスタ
JP2010-076366 2010-03-29

Publications (2)

Publication Number Publication Date
CN102208445A CN102208445A (zh) 2011-10-05
CN102208445B true CN102208445B (zh) 2016-03-30

Family

ID=44655390

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110086411.3A Expired - Fee Related CN102208445B (zh) 2010-03-29 2011-03-29 具有耗尽型mos晶体管的半导体装置

Country Status (5)

Country Link
US (1) US9013007B2 (enExample)
JP (1) JP2011210901A (enExample)
KR (1) KR101781220B1 (enExample)
CN (1) CN102208445B (enExample)
TW (1) TWI521702B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6095927B2 (ja) * 2012-09-27 2017-03-15 エスアイアイ・セミコンダクタ株式会社 半導体集積回路装置
US9478571B1 (en) * 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
EP3528288B1 (en) * 2013-06-20 2020-08-26 Stratio, Inc. Gate-controlled charge modulated device for cmos image sensors
US9559203B2 (en) * 2013-07-15 2017-01-31 Analog Devices, Inc. Modular approach for reducing flicker noise of MOSFETs
CN114551595B (zh) * 2020-11-20 2023-10-31 苏州华太电子技术股份有限公司 应用于射频放大的沟道掺杂调制rfldmos器件及制法
JP2022108157A (ja) * 2021-01-12 2022-07-25 キオクシア株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891468A (en) * 1972-09-20 1975-06-24 Hitachi Ltd Method of manufacturing semiconductor device
US5712501A (en) * 1995-10-10 1998-01-27 Motorola, Inc. Graded-channel semiconductor device
US5929486A (en) * 1996-10-25 1999-07-27 Ricoh Company, Ltd. CMOS device having a reduced short channel effect
CN1689165A (zh) * 2002-10-09 2005-10-26 飞思卡尔半导体公司 非易失性存储器件及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4212683A (en) * 1978-03-27 1980-07-15 Ncr Corporation Method for making narrow channel FET
US4575746A (en) * 1983-11-28 1986-03-11 Rca Corporation Crossunders for high density SOS integrated circuits
JPH0369167A (ja) * 1989-08-08 1991-03-25 Nec Corp 埋め込み型ｐチャネルｍｏｓトランジスタ及びその製造方法
KR960008735B1 (en) * 1993-04-29 1996-06-29 Samsung Electronics Co Ltd Mos transistor and the manufacturing method thereof
KR100189964B1 (ko) * 1994-05-16 1999-06-01 윤종용 고전압 트랜지스터 및 그 제조방법
JP2001352057A (ja) * 2000-06-09 2001-12-21 Mitsubishi Electric Corp 半導体装置、およびその製造方法
KR100343472B1 (ko) * 2000-08-31 2002-07-18 박종섭 모스 트랜지스터의 제조방법
JP3865233B2 (ja) * 2002-08-19 2007-01-10 富士通株式会社 Ｃｍｏｓ集積回路装置
KR100540341B1 (ko) * 2003-12-31 2006-01-11 동부아남반도체 주식회사 반도체 소자 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891468A (en) * 1972-09-20 1975-06-24 Hitachi Ltd Method of manufacturing semiconductor device
US5712501A (en) * 1995-10-10 1998-01-27 Motorola, Inc. Graded-channel semiconductor device
US5929486A (en) * 1996-10-25 1999-07-27 Ricoh Company, Ltd. CMOS device having a reduced short channel effect
CN1689165A (zh) * 2002-10-09 2005-10-26 飞思卡尔半导体公司 非易失性存储器件及其制造方法

Also Published As

Publication number Publication date
JP2011210901A (ja) 2011-10-20
CN102208445A (zh) 2011-10-05
TWI521702B (zh) 2016-02-11
TW201203548A (en) 2012-01-16
US20110233669A1 (en) 2011-09-29
KR20110109948A (ko) 2011-10-06
US9013007B2 (en) 2015-04-21
KR101781220B1 (ko) 2017-09-22

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Effective date of registration: 20160304

Address after: Chiba County, Japan

Applicant after: DynaFine Semiconductor Co.,Ltd.

Address before: Chiba, Chiba, Japan

Applicant before: Seiko Instruments Inc.

C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Chiba County, Japan

Patentee after: ABLIC Inc.

Address before: Chiba County, Japan

Patentee before: DynaFine Semiconductor Co.,Ltd.

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160330

CF01 Termination of patent right due to non-payment of annual fee