CN102208445A - 具有耗尽型mos晶体管的半导体装置 - Google Patents

具有耗尽型mos晶体管的半导体装置 Download PDF

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CN102208445A
CN102208445A CN2011100864113A CN201110086411A CN102208445A CN 102208445 A CN102208445 A CN 102208445A CN 2011100864113 A CN2011100864113 A CN 2011100864113A CN 201110086411 A CN201110086411 A CN 201110086411A CN 102208445 A CN102208445 A CN 102208445A
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原田博文
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Abstract

得到改善的耗尽型MOS晶体管，其中包括：半导体衬底上的第一导电型的阱区；在阱区上形成的栅极绝缘膜；在栅极绝缘膜上形成的栅电极；在栅电极的两端形成的第二导电型的源极/漏极区；在源极/漏极区之间的栅极氧化膜下形成的第二导电型的低浓度杂质区；以及在源极/漏极区之间的第二导电型的低浓度杂质区之下形成的第一导电型的低浓度杂质区。

Description

具有耗尽型MOS晶体管的半导体装置
技术领域
本发明涉及包含具有埋入沟道的耗尽型MOS晶体管的半导体装置。
背景技术
作为晶体管的分类之一，有这样的分法：常截止型、即栅极电压为0V时不会在漏极/源极间有电流流动；以及常导通型、即栅极电压为0V时在漏极/源极间有电流流动。在MOS晶体管的情况下，特别是，将前者称为增强型，且将后者称为耗尽型。例如在N沟道MOS晶体管的情况下，耗尽型MOS晶体管被设定为阈值电压取负值。
图2是一般的耗尽型N沟道MOS晶体管的示意剖视图。不管是耗尽型还是增强型，N沟道晶体管大体上形成在1×1015/cm3到1×1017/cm3的P型阱区5上。耗尽型、增强型的差异在于耗尽型的情况下在栅极氧化膜10下的沟道区9形成有1×1017/cm3到5×1018/cm3的低浓度N型杂质区3，与1×1019/cm3以上的浓度的N型的栅电极8的两端的N型的源极/漏极区2一起形成N型的电流路径。通过这样的构成，施加在栅电极的电压为0V的情况下，若对漏极/源极间施加电压，则能使电流在由该N型的杂质区组构成的电流路径中流动。
接着，对一般的耗尽型N沟道MOS晶体管的电气动作进行说明。如之前讲述的那样，在栅极电压为0V的情况下，响应漏极/源极间电压而有电流经由低浓度N型杂质区而在N型的源极/漏极区之间流动。这时，电流路径的上游为与栅极氧化膜的界面，下游为P阱区和低浓度N型杂质区的PN结形成的界面。更严格地说，电流路径的下游达到在P阱区和低浓度N型杂质区的PN结附近形成的耗尽层的上游。在使栅极电压为正值的情况下，在低浓度N型杂质区中进一步感应电子，会有更多的电流流动。
另一方面，在使栅极电压为负值的情况下，从低浓度N型杂质区的栅极氧化膜界面起向下开始耗尽，随着负侧的电压增加收窄P阱区与PN结之间的电流路径。与之相伴地，电流值降低。
然后进一步将栅极电压向负侧增加，并且从栅极氧化膜界面产生的耗尽层，与由N型低浓度杂质区和P阱区的PN结形成的耗尽层接触时，电流路径就会消失并且电流值成为0。大体上此时的栅极电压值成为耗尽型N沟道MOS晶体管的阈值电压，会取负值。
从以上说明能够理解到，电流流过的路径主要为比栅极氧化膜在半导体衬底侧更深的部分，因此耗尽型MOS晶体管也被称为埋入沟道型MOS晶体管。另一方面，增强型MOS晶体管一般为表面沟道型。
在通过半导体制造工序作成具有上述那样的电气动作/结构的耗尽型N沟道MOS晶体管时，在形成栅极氧化膜前或者在形成栅电极前且形成栅极氧化膜后，追加在栅极氧化膜下注入N型杂质的沟道形成工序。其N型杂质为磷或砷，通过离子注入来引入，作为注入量(ド一ズ量)，有从1×1011/cm2到1×1013/cm2之间的值。
这种耗尽型MOS晶体管往往在半导体集成电路中活用称为常导通型的特征而作为恒流源加以利用。此外有利用其恒流构成恒压电路的例子。这种用途在模拟电路中特别多，精度越高，其恒流性越能对作为模拟电路的高性能化或整个电路的低成本化做贡献。
具体要求精度的是阈值电压和电流驱动能力，而与增强型N沟道MOS晶体管的阈值电压相比，一般耗尽型N沟道MOS晶体管的阈值电压的偏差较大。
其理由是因为与增强型N沟道MOS晶体管的阈值电压相关的参数大体上由以下的3个方面决定，与之相对，耗尽型N沟道MOS晶体管还要加沟道杂质深度的参数的缘故。
1)沟道杂质浓度
2)栅极氧化膜厚
3)由固定电荷等确定的平带电压
作为耗尽型MOS晶体管的作成方法或减少其特性劣化/偏差的方法，例如公开于专利文献1等。
专利文献：日本特开平7-161978号公报
发明内容
但是，现有的耗尽型MOS晶体管中存在如下的课题。耗尽型MOS晶体管的阈值电压与沟道的耗尽层的延伸相关，这与上述说明一样，但是用于产生该耗尽层的延伸的电压相应量，与耗尽层的延伸的平方成比例，因此耗尽层距离的变动会使阈值电压显著变化。该耗尽层距离在N沟道MOS晶体管的情况下，相当于N型杂质区的深度，但是这与N型杂质注入后的热处理及P型阱层的较深的部分中的浓度偏差相关，难以减小它们。因而耗尽型MOS晶体管的阈值电压会比增强型MOS晶体管还要大幅偏离，采用由模拟电路吸收该偏差有宽余的设计或规格的结果，存在的课题是难以低成本提供高精度的模拟IC。
本发明为了解决上述课题而采用以下方案。
首先，一种耗尽型MOS晶体管，其中包括：半导体衬底上的、第一导电型的阱区；在第一导电型阱区上形成的栅极绝缘膜；在栅极绝缘膜上形成的栅电极；在第一导电型的阱区内并且在栅电极的两端形成的第二导电型的源极/漏极区；在第一导电型的阱区内并且在源极/漏极区之间的栅极氧化膜下形成的第二导电型的低浓度杂质区；以及在第一导电型的阱区内并且在源极/漏极区之间的第二导电型的低浓度杂质区之下形成的第一导电型的低浓度杂质区。
此外，在耗尽型MOS晶体管中，从源极/漏极区相分离地形成第一导电型的低浓度杂质区。
然后，在耗尽型MOS晶体管中，以使上述第一导电型的低浓度杂质区和所述源极/漏极区的距离成为0.5μm到1.5μm之间的方式相分离。
而且，在耗尽型MOS晶体管中，第一导电型的低浓度杂质区的峰值浓度为5.0×1016/cm3到1.0×1018/cm3。
进而，在耗尽型MOS晶体管中，第二导电型的低浓度杂质区的峰值浓度为1.0×1017/cm3到5.0×1018/cm3。
(发明效果)
依据本发明，能够作成阈值偏差的变动少的耗尽型MOS晶体管，由此能够提供具有低成本/高性能的模拟电路的半导体集成电路。
附图说明
图1是本发明的第一实施例的耗尽型N沟道MOS晶体管的示意剖视图。
图2是现有的耗尽型N沟道MOS晶体管的示意剖视图。
图3是本发明的第二实施例的耗尽型N沟道MOS晶体管的示意剖视图。
图4是表示本发明的耗尽型N沟道MOS晶体管的深度方向杂质浓度分布的图表。
图5是表示本发明的耗尽型N沟道MOS晶体管的深度方向杂质浓度分布的其它图表。
图6A至6E是用于作成本发明的耗尽型N沟道MOS晶体管的工序流程剖视图。
具体实施方式
下面根据附图，对本发明的实施的方式进行说明。
图1是本发明的第一实施例的耗尽型N沟道MOS晶体管的示意剖视图。与现有方法的差异在于，在成为沟道的N型低浓度杂质区的下层重新用离子注入法形成具有比P阱区高的浓度的P型低浓度杂质区。在作成这样的结构的情况下，即便N型低浓度杂质区的深度因热处理的偏差而变大，N型低浓度杂质区的下摆的部分也会向P型低浓度杂质区的表面侧的扩散，从而能抵消，其结果是能抑制N型低浓度杂质区和其下的P型低浓度杂质区的接合位置的偏差，从而也能抑制更进一步的阈值电压的变动。
在此N型低浓度杂质区及P型低浓度杂质区的浓度峰值取决于离子注入能量，但由于偏差非常小，所以注入时的深度变动造成的阈值电压的偏差小到能忽略不计的程度。
关于该N型低浓度杂质区及P型低浓度杂质区的深度及浓度，通过适当地选择离子注入条件，能够选定各式各样的式样(pattern)。
例如图4示出下列情况下的杂质浓度分布：作为N型低浓度杂质的条件采用砷，在进行50keV、1.7×1012/cm2的离子注入之后，作为P型低浓度杂质的条件采用硼，在进行40keV、1.0×1012/cm2的离子注入。如此用注入能量控制P型杂质区的深度，从而无需改变N型低浓度杂质的接合位置而能在N型低浓度杂质区的正下方的位置设定P型低浓度杂质区。
该P杂质区采用硼元素，因此在形成沟道的杂质区之后若热处理较大，则硼的朝着表面方向的扩散会比砷的下方向的扩散更显著，有时N型低浓度杂质区的接合位置变浅。在这种情况下，增大用于形成P型低浓度杂质区的离子注入能量即可。例如，通过将硼的能量从40keV变更为60keV，能够设定为深达0.05um左右。
此外，图5是下列情况下的杂质浓度分布：作为N型低浓度杂质的条件使用砷，在进行50keV、1.7×1012/cm2的离子注入后，作为P型低浓度杂质的条件使用硼，在进行40keV，5.0×1012/cm2的离子注入。如果P型低浓度杂质区的注入量太大，则之前讲述的向表面侧的扩散占主导地位，且N型低浓度杂质区和下方的P型杂质区的接合面会受该P型低浓度杂质区的热处理造成的深度偏差的约束。因此，P型低浓度杂质区的最大峰值浓度最好为N型低浓度杂质区的最大峰值浓度以下。
在之前的例中，作为N型低浓度杂质的条件采用砷，在50keV、1.7×1012/cm2的情况下，作为P型低浓度杂质的条件，如果是硼，则离子注入条件最好为40至70keV；1.0×1012/cm2至5.0×1012/cm2的范围。尚且这也与上述的一样，根据后续的热处理的大小而改变最佳设定值。其后，经过各式各样的热处理，最终N型低浓度杂质区的峰值浓度成为1.0×1017/cm3到5.0×1018/cm3，但是为了减少阈值电压的偏差，P型低浓度杂质区的峰值浓度最好为5.0×1016/cm3到1.0×1018/cm3。
接着，借助图6A至6E，就本发明的N沟道耗尽型MOS晶体管的作成方法进行说明。
首先，与通常的MOS晶体管的制造方法同样地，在半导体衬底1上形成阱区，通过借助LOCOS法形成的较厚的氧化膜等，分离形成不形成元件的部分。(图6A)
接着，在元件形成区的耗尽型MOS晶体管形成区，以抗蚀剂为掩模，进行用于形成N型低浓度杂质区的离子注入。条件如前所述，根据以阈值电压为目标的值任意选择。(图6B)
接着，将同一抗蚀剂作为掩模，进行用于形成P型低浓度杂质区的离子注入。该条件也如前所述，为了抑制阈值偏差而选择任意的值。(图6C)
接着，进行用于形成耗尽型MOS晶体管的栅电极的、多晶硅的沉积/热扩散或离子注入等的1×1019/cm2的浓度的杂质注入/栅电极的构图。(图6D)
接着，进行源极/漏极的形成，完成为半导体元件。(图6E)
如以上讲述的那样，本方法不需要多余的掩模工序，仅通过增加一个步骤的离子注入工序就能够作成，因此不会伴随着工艺成本的增大而能够实现阈值电压的高精度化。
图3是表示本发明的第二实施例的示意剖视图。在第一实施例中没有提到源极/漏极的条件，但是为了抑制穿通(punch through)等短沟道效应而有时在栅电极肋形成低浓度漏极，根据条件，该低浓度漏极和P型低浓度杂质区的PN结中有时会引起耐压降低。在第二实施例中为了避免此情况，追加掩模工序，使P型低浓度杂质区向沟道的内侧偏置地形成。偏置宽度也与所需耐压相关，从0.5μm到1.5μm之间较为稳妥。
以上的说明列举了N沟道耗尽型MOS晶体管，但是在P沟道耗尽型MOS晶体管的情况下，仅仅变更注入杂质的导电型，也能容易得到本发明的结构/效果。即，将图1中成为沟道的N型低浓度杂质区3更换为P型低浓度杂质区，将其下的P型低浓度杂质区4更换为N型低浓度杂质区，就能达成。
附图标记说明
1半导体衬底；2源极/漏极区；3低浓度N型杂质区；4低浓度P型杂质区；5P型阱区；6N型阱区；7元件分离区；8栅电极；9沟道区；10栅极氧化膜；11第二低浓度P型杂质区。

Claims (5)

1.一种半导体装置，其中包括：
半导体衬底上的、第一导电型的阱区；
在所述第一导电型阱区上形成的栅极绝缘膜；
在所述栅极绝缘膜上形成的栅电极；
在所述第一导电型的阱区内并且在所述栅电极的两侧形成的第二导电型的源极/漏极区；
在所述第一导电型的阱区内并且在所述源极/漏极区之间的所述栅极氧化膜下形成的第二导电型的低浓度杂质区；以及
在所述第一导电型的阱区内并且在所述源极/漏极区之间的所述第二导电型的低浓度杂质区之下形成的第一导电型的低浓度杂质区。
2.如权利要求1所述的半导体装置，其中所述第一导电型的低浓度杂质区配置成与所述源极/漏极区相分离。
3.如权利要求2所述的半导体装置，其中所述第一导电型的低浓度杂质区和所述源极/漏极区在0.5μm到1.5μm之间相分离。
4.如权利要求1所述的半导体装置，其中所述第一导电型的低浓度杂质区的峰值浓度为5.0×1016/cm3到1.0×1018/cm3。
5.如权利要求4所述的半导体装置，其中所述第二导电型的低浓度杂质区的峰值浓度为1.0×1017/cm3到5.0×1018/cm3。
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