CN101819964A - 集成电路安装板、印刷布线板和制造集成电路安装板方法 - Google Patents

集成电路安装板、印刷布线板和制造集成电路安装板方法 Download PDF

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CN101819964A
CN101819964A CN201010124478A CN201010124478A CN101819964A CN 101819964 A CN101819964 A CN 101819964A CN 201010124478 A CN201010124478 A CN 201010124478A CN 201010124478 A CN201010124478 A CN 201010124478A CN 101819964 A CN101819964 A CN 101819964A
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insulating
integrated circuit
insulating barrier
board
circuit mounted
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CN101819964B (zh
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孝谷卓哉
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Denso Corp
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Denso Corp
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    • HELECTRICITY
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    • H05K1/0203Cooling of mounted components
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Abstract

一种集成电路安装板(1),包括印刷布线板(2)和安装在印刷布线板(2)上的集成电路裸芯片(3)。印刷布线板(2)包括金属基台(30)、绝缘材料制成并设置在金属基台(30)上的绝缘构件、以及设置在绝缘构件上的布线图案(10)。布线图案(10)包括电极部分(10a-10f),集成电路裸芯片(3)电连接到所述电极部分。绝缘构件包括与电极部分(10a-10f)相对的下部区域。金属基台(30)包括金属基底(30a)和从金属基底(30a)伸出的金属部分(6)。金属部分(6)埋设在绝缘构件的下部区域中。

Description

集成电路安装板、印刷布线板和制造集成电路安装板方法
 
技术领域
本发明涉及一种集成电路安装板、印刷布线板和集成电路安装板的制造方法。
背景技术
普通的集成电路安装板中,半导体例如硅制成的集成电路的裸芯片安装在印刷布线板上。印刷电路板中,绝缘材料制成的绝缘层以及包括例如铜制成的导电线的布线图案设置在金属基台上。
集成电路安装板的普通制造方法中,可以进行引线接合连接或者倒装芯片(flip-chip)连接。引线接合连接中,裸芯片(bare chip)的焊盘和布线图案的电极通过导电线相结合。在倒装芯片连接中,集成电路通过形成在裸芯片的焊盘上的隆突(bump)而结合在印刷布线板上。
当金用作引线接合连接或者倒装芯片连接中的导电线或者隆突(下面称为连接介质)时,可使用超声波热压方法。超声波热压方法中,印刷布线板安装在加热台(陶瓷或者金属)上,该加热台以150℃到200℃的温度加热,并且超声波振动施加到印刷布线板上的连接介质。
集成电路安装板中,玻璃环氧树脂(glass epoxy resin)或者酚醛纸(phenol paper)通常用作绝缘材料。当集成电路安装板用于处理高频信号例如毫米波时,可以使用氟树脂例如聚四氟乙烯(PTFE),比上述绝缘材料具有较低的介质损耗角正切,例如在JP-A-7-323501中描述的。通过使用具有低介质损耗角正切的绝缘材料,与信号频率以及介质损耗角正切成比例的能量损耗(介质损耗)可以被限制。
适于处理高频的绝缘材料例如氟树脂和液晶聚合物(LCP)的弹性模量会在150℃到200℃的高温下显著降低。
因此当引线接合连接和倒装芯片接合在集成电路安装板制造过程中进行时,加热台上印刷布线板中包括的绝缘材料会分散施加给连接介质的超声波和负荷。结果,引线接合连接或者倒装芯片连接会不适当进行,集成电路安装板的可靠性会降低。
发明内容
考虑上述问题,本发明第一目的是提供一种集成电路安装板,其中,集成电路裸芯片可以与印刷布线板可靠地电连接。本发明第二目的是提供一种印刷布线板,集成电路裸芯片可以可靠地电连接到其上。本发明第三目的是提供一种制造集成电路安装板的方法,其中,集成电路裸芯片可以与印刷布线板可靠地电连接。
根据本发明第一方面,集成电路安装板包括:印刷布线板和安装在印刷布线板上的集成电路裸芯片。印刷布线板包括:金属基台;绝缘构件,由绝缘材料制成,设置在金属基台上;和布线图案,设置在绝缘构件上。布线图案包括电极部件,集成电路裸芯片连接到其上。绝缘构件包括下部区域,与所述电极部件相对。金属基台包括金属基底和从金属基底突出的金属部分。金属部分埋设到绝缘构件的下部区域中。
上述集成电路安装板中,集成电路裸芯片可与印刷布线板可靠地电连接。
根据本发明第二方面,印刷布线板包括:金属基台;绝缘构件和布线图案。金属基台包括金属基底和从金属基底突出的金属部分。绝缘构件由绝缘材料制成,设置在金属基台上。布线图案设置在绝缘构件上,包括电极部件,该部件构造成与集成电路裸芯片电连接。绝缘构件包括与电极部件相对的下部区域。金属部分埋设在下部区域中。
上述印刷布线板可以与集成电路裸芯片可靠地电连接。
在根据本发明第三方面的方法中,制造集成电路安装板,包括印刷布线板和安装在印刷布线板上的集成电路裸芯片。印刷布线板包括金属基台;多个绝缘层;和布线图案。金属基台包括金属基底和从金属基底突出的金属部分。多个绝缘层由绝缘材料制成,设置在金属基台上。布线图案设置在多个绝缘层上,包括电极部分,集成电路裸芯片电连接到该电极部分。多个绝缘层包括:第一绝缘层,电极部分设置在其上;和第二绝缘层,设置在第一绝缘层的与电极部分相反的一侧上。多个绝缘层还包括与电极部分相反的下部区域。根据第三方面的方法中,腔形成在下部区域中,从而腔穿透多个绝缘层,从多个绝缘层的在与电极部分相反一侧上的表面到第二绝缘层的靠近第一绝缘层的表面,多个绝缘层以下列方式设置在金属基台上,即金属部分配合到腔中。
上述制造方法中,金属部分可以埋在多个绝缘层中。因此,集成电路裸芯片可以与印刷布线板可靠的电连接。
附图说明
结合附图,通过下面典型实施例的详细描述,本发明的另外目的和优点将显而易见。附图中:
图1的图形示出了根据本发明第一实施例的集成电路安装板的剖视图;
图2A的图形示出了根据第一实施例的集成电路安装板的俯视图;
图2B的图形示出了沿着图2A中的线IIB-IIB截取的集成电路安装板的剖视图;
图2C的图形示出了沿着图2A中的线IIC-IIC截取的集成电路安装板的剖视图;
图3A-3E的图形示出了根据第一实施例的制造集成电路安装板1的典型方法;
图4的图形示出了根据本发明第二实施例的集成电路安装板的剖视图;
图5A-5E的图形示出了根据第二实施例的集成电路安装板1制造的典型方法;
图6A的图形示出了根据本发明另一实施例的集成电路安装板的俯视图;
图6B的图形示出了沿着图6A中的线VIB-VIB截取的集成电路安装板的剖视图;
图6C的图形示出了沿着图6A中的线VIC-VIC截取的集成电路安装板的剖视图;
图7A的图形示出了根据本发明另一实施例的集成电路安装板的俯视图;
图7B的图形示出了沿着图7A中的线VIIB-VIIB截取的集成电路安装板的剖视图;
图7C图形示出了沿着图7A中的线VIIC-VIIC截取的集成电路安装板的剖视图;
图8A的图形示出了根据本发明另一实施例的集成电路安装板的俯视图;
图8B的图形示出了沿着图8A中的线VIIIB-VIIIB截取的集成电路安装板的剖视图;
图8C图形示出了沿着图8A中的线VIIIC-VIIIC截取的集成电路安装板的剖视图;
图9A的图形示出了根据本发明另一实施例的集成电路安装板的俯视图;
图9B的图形示出了沿着图9A中的线IXB-IXB截取的集成电路安装板的剖视图;
图9C图形示出了沿着图9A中的线IXC-IXC截取的集成电路安装板的剖视图;
图10A的图形示出了根据本发明另一实施例的集成电路安装板的俯视图;
图10B的图形示出了沿着图10A中的线XB-XB截取的集成电路安装板的剖视图;
图10C图形示出了沿着图10A中的线XC-XC截取的集成电路安装板的剖视图。
具体实施方式
首先,在描述本发明典型实施例之前,描述本发明的各个方面。
根据本发明第一方面,集成电路安装板包括印刷布线板以及安装在印刷电路板上的集成电路(IC)裸芯片。印刷布线板通过下面方式形成:在绝缘材料制成的绝缘构件上形成布线图案,并且将绝缘构件设置在金属基台上。金属基台包括金属基底和从金属基底伸出的金属部分。印刷布线板和IC裸芯片彼此电连接。布线图案包括电极部分,IC裸芯片电连接到该电极部分。
在与布线图案的电极部分相对的绝缘构件中的区域处(下面称为下部区域),从金属基底突出的金属部分被埋设。当绝缘构件的厚度方向被表示为Z轴方向时,下部区域是沿着Z轴方向位于电极部分下面的绝缘构件中的预定区域。
在集成电路安装板中,绝缘构件中的下部区域的刚度通过金属部分被增强。因此,当IC裸芯片和布线图案通过连接介质例如导电线和隆突(bump)连接时,施加到印刷布线板的超声波和负荷被有助于沿着Z轴方向传递。
与绝缘构件的绝缘材料无关,由于金属部分的刚度高于绝缘材料,连接介质可以可靠地热熔接合到电极部分。因此,IC裸芯片可以与印刷布线板可靠地电连接。
绝缘构件的绝缘材料可以是热塑性树脂。例如,绝缘材料可以是氟树脂,例如PTFE,塑料树脂,例如聚醚醚酮酮(PEEK),以及液晶聚合物(LCP),它们通常的介质损失角正切小于玻璃环氧树脂以及酚醛纸。
集成电路安装板可以限制能量损失(电介质损失),其正比于信号频率以及介质损失角正切。因此,集成电路可以适用于处理高频信号的装置,例如毫米波。
在电极部分包括多个电极的情况中,下部区域可包括一个与所有电极相反的区域,或者下部区域可包括多个区域,每个与其中一个电极相对。
当下部区域包括多个区域时,埋设在绝缘构件中的金属部分的区域可以减少。因此,当布线图案包括多个图案时,或者当布线图案具有微带线结构时,在绝缘构件上形成的布线图案的布线密度可以增大。
印刷布线板可以是多层印刷电路板,其中,绝缘构件包括多个绝缘层,布线图案包括多个布线层,每个布线层设置在其中一个绝缘层上。这种情况中,印刷布线板的面积可以减少。
当绝缘层的厚度减小时,热熔接合(thermal fusion bonding)过程中超声波和负荷的分散可以被限制。因此在多个绝缘层中,当电极部分形成在其上的绝缘层被称为第一绝缘层、并且形成在第一绝缘层的与电极部分相反一侧上的绝缘层被称为第二绝缘层时,金属部分可以埋在所有多个绝缘层中,包括第二绝缘层,除了第一绝缘层。也就是,金属部分可以穿入多个绝缘层,从多个绝缘层的靠近金属基台的表面到第二绝缘层的靠近第一绝缘层的表面。
第一绝缘层的厚度可以小于多个绝缘层中除了第一绝缘层的绝缘层的厚度。例如,当第一绝缘层具有第一厚度且第二绝缘层具有第二厚度时,第一厚度可小于第二厚度。
通过减小第一绝缘层的厚度,在热熔接合过程中超声波和负荷的分散可以受限。因此,IC裸芯片可以与印刷布线板可靠的电连接。
在布线图案具有微带线结构的情况中,当绝缘层厚度减小时,信号线的宽度需要减小从而将印刷布线板的特征阻抗设定到预定值(例如50Ω)。如果信号线的宽度太小,带线的传导损失可增大,并且整个电路的损失会增加。
在多层印刷布线板中,布线图案可以具有微带线结构,且多个布线层可包括带线图案层和两个接地图案层。在多个绝缘层中,信号线层可形成在第一绝缘层的表面上,其上形成电极部分(第一表面)。在第一绝缘层的靠近第二绝缘层的表面上(第二表面),其中一个接地图案层可以仅形成在与下部区域相对应的部分处。在与第一绝缘层相反的一侧上的第二绝缘层的表面上(第三表面),可以形成接地图案层中的另一个。设置在第二表面上的接地图案层以及设置在第三表面上的接地图案层,可以通过通路孔插塞(via plug)连接,该插塞穿过第二绝缘层。
上述集成电路安装板基本类似于下面的情况:第一绝缘层的厚度仅在与下部区域相对应的部分处减小。因此,IC裸芯片可以与印刷布线板可靠的电连接。另外,通过确保其它绝缘层的充分的厚度,带线的传导损失可以受限,同时不会不必要地降低信号线的宽度。
在补充材料提前包括在绝缘构件的绝缘材料中的情况中,从而绝缘构件的线性膨胀系数基本接近(近似)于布线图案的线性膨胀系数,金属基底和金属部分可以由这样的材料制成:其具有的线性膨胀系数接近于布线图案。例如,金属基底和金属部分可以由与布线图案相同的材料制成。补充材料可以是具有低线性膨胀系数的绝缘材料,例如玻璃布。包括补充材料的绝缘构件、布线图案、金属基底和金属部分,不需要具有严格相同的线性膨胀系数。
上述集成电路安装板中,印刷布线板和金属基台的剥离可以被限制。另外,布线图案和绝缘构件的剥离可以被限制。
根据本发明第二方面的印刷布线板包括:绝缘构件;设置在绝缘构件上的布线图案;和金属基台,其上布置绝缘构件。布线图案包括电极部分,该电极部分构造成与集成电路裸芯片电连接。金属基台包括金属基底和从金属基底突出的金属部分。绝缘构件包括与电极部分相对的下部区域。金属部分埋设在绝缘构件的下部区域中。上述印刷电路板可适用于根据本发明第一方面的集成电路安装板。
根据本发明第三方面的制造方法是制造集成电路安装板的方法,其中,集成电路裸芯片安装在多层印刷布线板上,IC裸芯片和多层印刷布线板彼此电连接。多层印刷布线板包括:多个绝缘层,由绝缘材料制成;形成在所述多个绝缘层上的布线图案;和金属基台,其上布置所述多个绝缘层。布线图案包括电极部分,集成电路裸芯片与所述电极部分电连接。所述多个绝缘层包括:第一绝缘层,其上布置电极部分;和第二绝缘层,布置在第一绝缘层的与电极部分相反的一侧上。
所述多个绝缘层还包括与电极部分相对的下部区域。制造方法中,腔形成在下部区域中从而腔从多个绝缘层的在与电极部分相反一侧上的表面穿透到第二绝缘层的靠近第一绝缘层的表面,多个绝缘层以下列方式设置在金属基台上,即金属部分配合到腔中。
上述集成电路安装板制造方法中,金属基台可以埋设在多个绝缘层中。因此集成电路裸芯片可以与多层印刷布线电路可靠地电连接。
(第一实施例)
下面参考图1和2描述本发明第一实施例的集成电路安装板1。
如图1,集成电路安装板1包括:金属基台30;多层印刷布线板2;集成电路(IC)裸芯片(bare chip)3;和芯片部件4。多层印刷布线板2中,形成有铜制的布线图案10。布线图案10包括多个堆叠的布线层。IC裸芯片3由半导体制成,例如硅。芯片部件4例如包括电容器和电阻。IC裸芯片3和芯片部件4安装在多层印刷布线板2的表面上。
IC裸芯片3和多层印刷布线板2的表面彼此通过导电线5电连接,该导电线例如由金或者铜制成。金属基台30包括铜基底30a和从铜基底30a伸出的铜部分6。金属基台30可例如用作散热器。
IC裸芯片3是没有被封装的半导体元件。多层印刷布线板2具有凹陷部分2a。IC裸芯片3通过粘结剂设置在凹陷部分2a上,粘结剂例如银环氧树脂和硅树脂。IC裸芯片3包括焊盘(pad)3a和3b,导电线5接合到所述焊盘上。
多层印刷布线板2包括绝缘材料制成的绝缘构件。绝缘构件包括多个绝缘层20。每个绝缘层20可以是预浸料坯(prepreg),通过利用聚四氟乙烯(PTFE)浸渍玻璃布(glass cloth)制成。玻璃布可用作补充材料(supplementing material)。每个布线层形成在其中一个绝缘层20上。绝缘层20设置在金属基台30上。玻璃布以与PTFE的浸渍量相对应的比率包括在绝缘层20中,从而绝缘层20的线性膨胀系数基本类似于布线图案10的线性膨胀系数。
根据本实施例的多层印刷电路板2中,布线图案10具有微带线(microstrip line)结构。信号线的宽度以及信号线和地线(groundline)之间的距离以下面的方式确定:多层印刷布线板2的特征阻抗变为预定值。该预定值例如50Ω。布线图案10包括位于信号线上的电极10a和10b以及接地焊盘10c-10f。导电线5接合到电极10a和10b以及接地焊盘10c-10f。电极10a和10b以及接地焊盘10c-10f可用作电极部分。
绝缘层20包括第一到第三绝缘层20。第一绝缘层20、第二绝缘层20和第三绝缘层20沿着厚度方向以这样的顺序从电极10a、10b和接地焊盘10c-10f设置在其上的一侧设置。金属基台30的铜部分6分别设置在位于电极10a、10b和接地焊盘10c-10f下面的第二绝缘层20和第三绝缘层20的区域处(下面称为下部区域(直下区域,underregions)),如图2B。
绝缘层20的每个下部区域与电极10a、10b和接地焊盘10c-10f中的一个相对。在位于接地焊盘10c-10f下面的第一绝缘层20的区域处,分别设置通路孔插塞(via plug)7。在绝缘层20的层间(interlayer)处,通路孔插塞7同样被设置,从而将形成在不同绝缘层20上的信号线或者地线电连接。
下面参考图3A-3E描述集成电路安装板1的典型制造方法。图3A-3E的制造方法中使用了组合(built-up)方法。
图3A所示的过程中,通孔设置在预浸料坯中,例如通过使用激光装置。每个通孔填充有导电糊膏(conductive paste),从而形成具有通路孔插塞7的预浸料坯。然后,铜薄膜连接到其中一个具有通路孔插塞7的预浸料坯的两侧上,例如通过利用滚子层压机来层压或者热压。铜薄膜被蚀刻,从而在绝缘层20上形成布线层。其上形成布线层的绝缘层20设置在具有通路孔插塞7的两个预浸料坯之间,并且两个预浸料坯和绝缘层20设置在两个铜薄膜之间。两个铜薄膜,两个预浸料坯,以及绝缘层20,通过热压彼此接合。然后,位于两侧上的两个铜薄膜被蚀刻,从而形成布线层。结果,包括三个绝缘层20和四个布线层的基台基底8形成。
基台基底8的制造方法不限于上述实例。例如,一个铜薄膜可以连接到每个预浸料坯的一侧,铜薄膜可以被蚀刻从而形成布线层,通孔可以填充有传导构件,从而形成通路孔插塞7,预浸料坯可以堆叠和挤压。其它组合方法也可使用。绝缘层20的数目和布线层的数目可以改变。例如,可以形成三个以上的绝缘层20和四个以上的布线层。
图3B和3C的过程中,与凹部2a相对应的通孔设置穿过基台基底8的第一到第三绝缘层20,例如通过激光装置。然后,具有预定宽度的多个腔设置在第二绝缘层20和第三绝缘层20中,从而靠近通孔。然后,基台基底8和金属基台30以下列方式彼此接合,即每个铜部分6配合到其中一个腔中,并且从而形成多层印刷布线板2。金属基台30中,铜基底30a和铜部分6整体形成,例如通过模铸或者挤压。模铸中,熔化的铜以一定压力被浇灌到模具中并固化。基台基底8和金属基台30通过导电粘结剂彼此接合。
在图3D的过程中,芯片部件4,例如电容器和电阻,焊接在多层印刷布线板2表面上的信号线和地线的预定部分上。在图3E的过程中,IC裸芯片3利用粘结剂接合到多层印刷布线板2的凹部2a,例如银环氧树脂或者硅树脂。包括IC裸芯片3的多层印刷布线板2设置在加热台上,该加热台以150℃到200℃的温度加热。然后,IC裸芯片3的焊盘3a以及多层印刷布线板2的表面上的电极10a、10b通过导电线5利用接合工具接合,线5例如由金或者铜制成。另外,IC裸芯片3的焊盘3b和多层印刷布线板2的表面上的接地焊盘10c-10f通过导电线5接合。
根据本实施例的集成电路安装板1中,铜部分6设置在电极10a、10b和接地焊盘10c-10f的下部区域处。因此,即使如果当IC裸芯片3的焊盘3a和3b以及电极10a和10b以及接地焊盘10c-10f被接合时施加给多层印刷布线板2的超声波和负荷,铜部分6可以限制超声波和负荷的分散。因此,导电线5可以可靠地热熔接合到电极10a、10b和接地焊盘10c-10f。
通过上述方法制造的集成电路安装板1,IC裸芯片3与多层印刷布线板2正确地连接。因此,集成电路安装板1的可靠性可以改善。在集成电路安装板1中,多层印刷布线板2的绝缘层20包括PTFE,其介质损失角正切小于玻璃环氧树脂(glass epoxy resin)。因此,集成电路安装板1可以限制介质损失,可适用于处理高频信号的装置,例如毫米波。
集成电路安装板1中,金属基台30的铜部分6分别设置在绝缘层20的下部区域处。因此,绝缘层20中铜部分6的区域可以减小,并且绝缘层20中布线图案10的密度可以增大。
另外,集成电路安装板1中,玻璃布被预先包括在PTFE中从而绝缘层20的线性膨胀系数基本类似于布线图案10的线性膨胀系数,金属基台30中的铜部分6和布线图案10由相同材料制成。因此,可限制布线图案10从金属基台30剥离。另外,布线图案10从绝缘层20的玻璃可以被限制。
(第二实施例)
参考图4描述本发明第二实施例的集成电路安装板1。
集成电路安装板1包括多层印刷布线板2、IC裸芯片3、芯片部件4,例如电容器和电阻。电极10a和10b形成在多层印刷布线板2的表面上。IC裸芯片3具有焊盘3a和3b。多层印刷布线板2的电极10a和10b通过形成在焊盘3a和3b上的隆突分别与IC裸芯片3的焊盘3a和3b电连接。隆突可以由例如金或者铜制成。IC裸芯片3设置在多层印刷布线板2的表面上,也就是第一绝缘层20上。
根据本实施例的多层印刷布线板2中,布线图案10具有接地共面带线结构。信号线的宽度以及信号线和地线之间的距离以下面的方式确定:多层印刷布线板2的特征阻抗变为预定值。预定值例如50Ω。
参考图5A到5E描述本实施例的制造集成电路安装板1的典型方法。图5A的过程中,基台基底8以类似于图3A过程的方式形成。
图5B和5C的过程中,腔设置在基台基底8中的第二绝缘层20和第三绝缘层的预定区域处,例如利用激光装置。腔穿入基台基底8,从基台基底8的在与电极10a和10b相反一侧上的表面,到第二绝缘层20的靠近第一绝缘层20的表面。然后,基台基底8和金属基台30以下列方式彼此接合,即铜部分6配合到腔中。本实施例中,铜部分6与所有电极10a和10b相对。也就是,与所有电极10a和10b相对的一个下部区域设置在绝缘层20中。
图5D所示过程中,芯片部分4,例如电容器和电阻,被焊接在多层印刷布线板2的表面上的信号线的预定部分上。多层印刷布线板2设置在加热台上,其以从150℃到200℃的温度加热。IC裸芯片3面向下设置,形成在焊盘3a和3b上的隆突直接熔接到多层印刷布线板2的表面上的电极10a和10b,也就是在第一绝缘层20上。
上述制造方法中,IC裸芯片3可以与多层印刷布线板2电连接,不用导电线5。因此,IC裸芯片3的安装区域可以减小,IC裸芯片3和多层印刷布线板2之间的连接部分的长度可以减小。因此,集成电路安装板1的电特性可以改善。
(其它实施例)
虽然已经参考附图结合典型实施例充分描述了本发明,需要注意的是各种变化和修改对于本领域技术人员是显而易见的。
例如,如图6A-6C以及7A-7C,第一绝缘层20的厚度可以小于第一绝缘层20以外的绝缘层20的厚度。
通过减小第一绝缘层20的厚度,当集成电路安装板1制造时,在热熔接合过程中的超声波和负荷的分散可以被限制。因此,IC裸芯片3可以与多层印刷布线板2可靠地电连接。
在根据上述实施例的每个集成电路安装板1中,布线图案10例如具有微带线结构或者接地共面带线结构。布线图案10还可具有共面带线结构。
在布线图案10具有微带线结构的情况中,如图8A到8C以及9A到9C,在其上形成有电极10a和10b以及接地焊盘10c-10f的第一绝缘层20的表面上,其对应于第一表面,带线图案层可以形成,在靠近第二绝缘层20的第一绝缘层20的表面上,其对应于第二表面,接地图案层可以仅形成在与下部区域相对应的部分处,其需要用于铜部分6和通过孔插塞7,在第二绝缘层的与第一绝缘层20相反的表面上,其对应于第三表面,接地图案层可形成在下部区域和凹陷部分2a以外的区域处。设置在第二表面上的接地图案层以及设置在第三表面上的接地图案层可以通过所述通过孔插塞7连接,该插塞7穿过第二绝缘层20。
当微带线结构具有带线宽度W、绝缘层20具有相对电容率εr、多层印刷布线板2具有特征阻抗Z时,两个绝缘层20的厚度“h”可以基于下列公式(1)设定:
Z=(120π/εeff1/2)/{W/h+1.393+ln(W/h+1.444)}...(1)
其中εeff=(εr+1)/2+(εr-1)/2(1+12h/W)1/2
例如,当Z=50Ω,εr=3.5,W=300μm时,h≈135μm因此,每个绝缘层20的厚度可以大约67.5μm。
集成电路安装板1,具有上述结构,基本类似于下列情况,其中:第一绝缘层20的厚度仅在与下部区域相对应的区域处减小。因此,IC裸芯片3可以与多层印刷布线板2可靠地电连接,对于特征阻抗的影响可以降低。
根据上述实施例的每个集成电路安装板1中,金属基台30构造成用作散热器。金属基台30还可构造成用作槽缝天线。金属基台30可以由包括铜的金属制成,金属基台30可以由铜之外的金属制成。
每个根据上述实施例的集成电路安装板1中,安装一个IC裸芯片3。每个集成电路安装板1可以是多芯片模块,其中安装多个IC裸芯片3。每个集成电路安装板1可包括单层印刷布线板,代替多层印刷布线板2。
根据第一实施例的集成电路安装板1中,IC裸芯片3安装在多层印刷布线板2的凹陷部分2a上,多个铜部分6接合在绝缘层20中。如图10A到10C,IC裸芯片3还可以设置在多层印刷布线板2的表面上,一个铜部分6可以配合在绝缘层20中,从而与IC裸芯片3、电极10a和10b以及接地焊盘10c-10f相对。

Claims (10)

1.一种集成电路安装板(1),包括印刷布线板(2)和安装在印刷布线板(2)上的集成电路裸芯片(3),其中:
印刷布线板(2)包括金属基台(30)、绝缘材料制成并设置在金属基台(30)上的绝缘构件、以及设置在绝缘构件上的布线图案(10);
布线图案(10)包括电极部分(10a-10f),集成电路裸芯片(3)电连接到所述电极部分;
绝缘构件包括与电极部分(10a-10f)相对的下部区域;
金属基台(30)包括金属基底(30a)和从金属基底(30a)伸出的金属部分(6);和
金属部分(6)埋设在绝缘构件的下部区域中。
2.如权利要求1所述的集成电路安装板(1),其特征在于,绝缘材料包括热塑性树脂。
3.如权利要求1所述的集成电路安装板(1),其特征在于,
电极部分(10a-10f)包括多个电极;
下部区域包括多个区域;和
多个区域中的每一个与多个电极的其中一个相对。
4.如权利要求1所述的集成电路安装板(1),其特征在于,
绝缘构件包括多个绝缘层(20);
布线图案(10)包括多个布线层;和
多个布线层中的每一个设置在多个绝缘层(20)的其中一个上。
5.如权利要求4所述的集成电路安装板(1),其特征在于,
多个绝缘层(20)包括:第一绝缘层(20),电极部分(10a-10f)设置在其上;和第二绝缘层(20),设置在第一绝缘层(20)的与电极部分(10a-10f)相反一侧上;和
金属部分(6)从多个绝缘层(20)的靠近金属基台(30)的表面到第二绝缘层(20)的靠近第一绝缘层(20)的表面穿入所述多个绝缘层(20)。
6.如权利要求5所述的集成电路安装板(1),其特征在于,
第一绝缘层(20)的厚度小于多个绝缘层中第一绝缘层(20)之外的其它绝缘层(20)的厚度。
7.如权利要求5所述的集成电路安装板(1),其特征在于,
印刷布线板(2)还包括穿透第二绝缘层(20)的通过孔插塞(7);
布线图案(10)具有微带线结构,所述多个布线层包括带线图案层和两个接地图案层;
第一绝缘层(20)具有:第一表面,电极部分(10a-10f)设置在其上;和第二表面,靠近第二绝缘层(20);
第二绝缘层(20)具有位于与第一绝缘层(20)相反侧上的第三表面;
带线图案层设置在第一表面上;
其中一个接地图案层仅设置在与下部区域相对应的第二表面的一部分处;
接地图案层中的另一个设置在第三表面上;和
设置在第二表面上的接地图案层与设置在第三表面上的接地图案层通过通过孔插塞(7)电连接。
8.如权利要求1-7中任一项所述的集成电路安装板(1),其特征在于,
绝缘材料包括补充材料,从而绝缘构件具有的线性膨胀系数接近布线图案(10)的线性膨胀系数,和
金属基底(30a)和金属部分(6)由这样的材料制成,该材料的线性膨胀系数接近布线图案(10)的线性膨胀系数。
9.一种印刷布线板(2),包括:
金属基台(30),包括金属基底(30a)和从金属基底(30a)伸出的金属部分(6);
绝缘构件,由绝缘材料制成,设置在金属基台(30)上;和
布线图案(10),设置在绝缘构件上,包括电极部分(10a-10f),该电极部分构造成与集成电路裸芯片(3)电连接,其中
绝缘构件包括与电极部分(10a-10f)相对的下部区域,和
金属部分(6)埋设在下部区域中。
10.一种制造集成电路安装板的方法,该集成电路安装板包括印刷布线板(2)和安装在印刷布线板(2)上的集成电路裸芯片(3),其中:
印刷布线板(2)包括金属基台(30)、多个绝缘层(20)和布线图案(10);
金属基台(30)包括金属基底(30a)和从金属基底(30a)伸出的金属部分(6);
多个绝缘层(20)由绝缘材料制成,设置在金属基台(30)上;
布线图案(10)设置在多个绝缘层(20)上,包括电极部分(10a-10f),集成电路裸芯片(3)电连接到该电极部分;
多个绝缘层(20)包括:第一绝缘层(20),电极部分(10a-10f)设置在其上;和第二绝缘层(20),设置在第一绝缘层(20)的与电极部分(10a-10f)相反的一侧上;和
多个绝缘层(20)还包括与电极部分(10a-10f)相对的下部区域,该方法包括:
在下部区域中形成腔,从而腔从多个绝缘层的位于与电极部分(10a-10f)相反一侧上的表面到第二绝缘层(20)的靠近第一绝缘层(20)的表面穿入所述多个绝缘层(20),;和
以下列方式将多个绝缘层(20)设置在金属基台(30)上,金属部分(6)配合到腔中。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101998763A (zh) * 2010-09-02 2011-03-30 华为技术有限公司 裸芯片与印制电路板的连接结构及印制电路板、通信设备
CN107393887A (zh) * 2016-04-29 2017-11-24 台达电子工业股份有限公司 封装结构
CN110364496A (zh) * 2018-04-11 2019-10-22 中国科学院微电子研究所 一种芯片封装结构及其封装方法
CN110891363A (zh) * 2011-12-15 2020-03-17 法雷奥电机控制系统公司 至少一个电子部件和完全或部分金属散热器之间的导热且电绝缘链接

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9713258B2 (en) * 2006-04-27 2017-07-18 International Business Machines Corporation Integrated circuit chip packaging
US9536815B2 (en) 2009-05-28 2017-01-03 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
WO2011139619A1 (en) 2010-04-26 2011-11-10 Hsio Technologies, Llc Semiconductor device package adapter
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US8955215B2 (en) 2009-05-28 2015-02-17 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
WO2010141297A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
WO2010141295A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed flexible circuit
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
US9093767B2 (en) 2009-06-02 2015-07-28 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2013036565A1 (en) 2011-09-08 2013-03-14 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US8970031B2 (en) 2009-06-16 2015-03-03 Hsio Technologies, Llc Semiconductor die terminal
WO2010141311A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
US8618649B2 (en) 2009-06-02 2013-12-31 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US9320133B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010141303A1 (en) 2009-06-02 2010-12-09 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8984748B2 (en) 2009-06-29 2015-03-24 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US8981809B2 (en) 2009-06-29 2015-03-17 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
JP2012238687A (ja) * 2011-05-11 2012-12-06 Sony Corp 半導体パッケージ、半導体装置の製造方法、および固体撮像装置
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
JP6102106B2 (ja) 2012-07-20 2017-03-29 株式会社デンソー レーダ装置
EP2954760B1 (en) * 2013-07-11 2017-11-01 HSIO Technologies, LLC Fusion bonded liquid crystal polymer circuit structure
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
US9596751B2 (en) * 2014-04-23 2017-03-14 Kyocera Corporation Substrate for mounting electronic element and electronic device
JP6256364B2 (ja) 2015-02-03 2018-01-10 株式会社オートネットワーク技術研究所 回路構成体
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
US20200069190A1 (en) * 2016-12-13 2020-03-05 Amolifescience Co., Ltd. Patch-type sensor module
KR101989859B1 (ko) * 2016-12-15 2019-09-30 주식회사 아모그린텍 파워 릴레이 어셈블리

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6110650A (en) * 1998-03-17 2000-08-29 International Business Machines Corporation Method of making a circuitized substrate
CN1368757A (zh) * 1994-11-22 2002-09-11 索尼株式会社 半导体装置和制造半导体设备的方法
WO2007143979A1 (de) * 2006-06-12 2007-12-21 Novacard Informationssysteme Gmbh Mechanisch aktivierbare transpondervorrichtung und chipkarte
CN101131944A (zh) * 2006-08-23 2008-02-27 Tdk株式会社 半导体器件的制造方法
US20080096321A1 (en) * 2006-10-18 2008-04-24 Advanced Semiconductor Engineering, Inc. Semiconductor chip package manufacturing method and structure thereof

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5868954A (ja) * 1981-10-20 1983-04-25 Mitsubishi Electric Corp 高周波トランジスタのパツケ−ジ
DE3831873A1 (de) * 1988-09-20 1990-03-29 Basf Ag Blends von thermotropen polymeren mit polyestern und polycarbonat
JPH04159792A (ja) * 1990-10-23 1992-06-02 Tamura Seisakusho Co Ltd 金属コア基板
JPH07326848A (ja) 1994-05-30 1995-12-12 Mitsubishi Gas Chem Co Inc 金メッキ成形基板の洗浄方法
JP2614190B2 (ja) 1994-06-01 1997-05-28 日本ピラー工業株式会社 多層板用プリプレグ、積層板、多層プリント回路基板およびその製造方法
US5433476A (en) * 1994-07-27 1995-07-18 Breed Automotive Technology, Inc. Temperature compensated stored gas inflator
JPH08115989A (ja) * 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
JPH08228053A (ja) 1995-02-21 1996-09-03 Nippon Mektron Ltd プリント基板
US5729433A (en) * 1996-01-30 1998-03-17 Micromodule Systems, Inc. Multiple chip module assembly for top of mother board
JP3149398B2 (ja) * 1998-06-16 2001-03-26 株式会社アドバンスト・ディスプレイ 液晶パネル製造装置および方法
JP3886712B2 (ja) 2000-09-08 2007-02-28 シャープ株式会社 半導体装置の製造方法
TW550997B (en) * 2001-10-18 2003-09-01 Matsushita Electric Ind Co Ltd Module with built-in components and the manufacturing method thereof
TW200302685A (en) * 2002-01-23 2003-08-01 Matsushita Electric Ind Co Ltd Circuit component built-in module and method of manufacturing the same
US6936336B2 (en) * 2002-03-15 2005-08-30 Kyocera Corporation Transfer sheet and production method of the same and wiring board and production method of the same
WO2004060660A1 (ja) * 2002-12-27 2004-07-22 Nec Corporation シート材及び配線板
JP2005247953A (ja) 2004-03-03 2005-09-15 Toray Ind Inc 半導体用接着剤組成物およびそれを用いた半導体用接着剤シート
JP4182016B2 (ja) 2004-03-11 2008-11-19 日本電気株式会社 伝送線路型素子及びその作製方法
TW200638812A (en) * 2004-11-18 2006-11-01 Matsushita Electric Ind Co Ltd Wiring board, method for manufacturing same and semiconductor device
JP4858678B2 (ja) * 2005-05-24 2012-01-18 ソニーケミカル&インフォメーションデバイス株式会社 エステル基含有ポリ(イミド−アゾメチン)共重合体、エステル基含有ポリ(アミド酸−アゾメチン)共重合体及びポジ型感光性樹脂組成物
JP2007129039A (ja) 2005-11-02 2007-05-24 Nippon Pillar Packing Co Ltd フッ素樹脂プリント基板及びその製造方法
JP4334005B2 (ja) * 2005-12-07 2009-09-16 新光電気工業株式会社 配線基板の製造方法及び電子部品実装構造体の製造方法
US7687722B2 (en) * 2006-10-03 2010-03-30 Endicott Interconnect Technologies, Inc. Halogen-free circuitized substrate with reduced thermal expansion, method of making same, multilayered substrate structure utilizing same, and information handling system utilizing same
JP4902558B2 (ja) * 2007-01-31 2012-03-21 三洋電機株式会社 半導体モジュールの製造方法
JP5003260B2 (ja) * 2007-04-13 2012-08-15 日本電気株式会社 半導体装置およびその製造方法
KR100988603B1 (ko) * 2008-05-21 2010-10-18 삼성전기주식회사 낮은 열팽창계수를 가지는 유리조성물, 유리섬유,인쇄회로기판의 절연층 및 인쇄회로기판

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1368757A (zh) * 1994-11-22 2002-09-11 索尼株式会社 半导体装置和制造半导体设备的方法
CN1197137C (zh) * 1994-11-22 2005-04-13 索尼株式会社 半导体装置和制造半导体设备的方法
US6110650A (en) * 1998-03-17 2000-08-29 International Business Machines Corporation Method of making a circuitized substrate
WO2007143979A1 (de) * 2006-06-12 2007-12-21 Novacard Informationssysteme Gmbh Mechanisch aktivierbare transpondervorrichtung und chipkarte
CN101131944A (zh) * 2006-08-23 2008-02-27 Tdk株式会社 半导体器件的制造方法
US20080096321A1 (en) * 2006-10-18 2008-04-24 Advanced Semiconductor Engineering, Inc. Semiconductor chip package manufacturing method and structure thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101998763A (zh) * 2010-09-02 2011-03-30 华为技术有限公司 裸芯片与印制电路板的连接结构及印制电路板、通信设备
CN101998763B (zh) * 2010-09-02 2013-01-16 华为技术有限公司 裸芯片与印制电路板的连接结构及印制电路板、通信设备
CN110891363A (zh) * 2011-12-15 2020-03-17 法雷奥电机控制系统公司 至少一个电子部件和完全或部分金属散热器之间的导热且电绝缘链接
CN107393887A (zh) * 2016-04-29 2017-11-24 台达电子工业股份有限公司 封装结构
CN107393887B (zh) * 2016-04-29 2019-07-16 台达电子工业股份有限公司 封装结构
CN110364496A (zh) * 2018-04-11 2019-10-22 中国科学院微电子研究所 一种芯片封装结构及其封装方法

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