CN107393887B - 封装结构 - Google Patents

封装结构 Download PDF

Info

Publication number
CN107393887B
CN107393887B CN201710281753.8A CN201710281753A CN107393887B CN 107393887 B CN107393887 B CN 107393887B CN 201710281753 A CN201710281753 A CN 201710281753A CN 107393887 B CN107393887 B CN 107393887B
Authority
CN
China
Prior art keywords
chip
patterned
support plate
layer
encapsulating structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710281753.8A
Other languages
English (en)
Other versions
CN107393887A (zh
Inventor
李嘉炎
蔡欣昌
李芃昕
林孝羲
程子璿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anchorage Semiconductor Co ltd
Original Assignee
Delta Optoelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/142,588 external-priority patent/US9865531B2/en
Application filed by Delta Optoelectronics Inc filed Critical Delta Optoelectronics Inc
Publication of CN107393887A publication Critical patent/CN107393887A/zh
Application granted granted Critical
Publication of CN107393887B publication Critical patent/CN107393887B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49531—Additional leads the additional leads being a wiring board
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101—Structure
    • H01L2224/4103—Connectors having different sizes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92246—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

一种封装结构，包括基板。上述基板包括金属载板、图案化的绝缘层以及图案化的导电层。上述图案化的绝缘层设置于金属载板上且部分地覆盖金属载板，上述图案化的导电层设置于图案化的绝缘层上。上述封装结构亦包括设置于未被图案化的绝缘层所覆盖的金属载板上的第一芯片以及设置于上述图案化的导电层上的第二芯片。上述第二芯片经由导电元件电性连接至第一芯片。上述导电元件包括一或多个接合导电片、一或多个重布线层结构或上述的组合，其中上述重布线层结构包括相互堆叠的至少一线路层及一绝缘层。

Description

封装结构
技术领域
本发明涉及一种半导体封装技术；特别涉及一种包括一图案化的绝缘金属基板(patterned insulation metal substrate，PIMS)的功率模块封装，及该图案化的绝缘金属基板的制造方法。
背景技术
功率模块封装(Power module packages)已被广泛地应用在汽车、工业设备及家用电器。一般而言，在功率模块封装中，一或多个半导体功率芯片可被安装于一金属载板上，并被一环氧树脂模塑料(epoxy molding compound，简称EMC)所封装以保护其内部零件。
图1显示一现有功率模块封装1的剖面示意图。如图1所示，现有功率模块封装1主要包括一金属载板10A、位于金属载板10A上的一整面的 (full-faced)绝缘层11、位于绝缘层11上的一图案化的导电层12(前述金属载板10A、绝缘层11及导电层12构成现有功率模块封装1中的一基板)及多个功率芯片13，可电性连接导电层12的部分并可通过多个导线14彼此电性连接。
然而，由于前述基板的结构设计(金属载板10A、绝缘层11及导电层12 是互相堆叠的)，现有功率模块封装1通常具有散热能力差的问题，造成其可靠性亦受到影响。
发明内容
本发明的目的在于提供一种封装结构，以提高其散热能力及高的可靠性。
有鉴于前述现有问题点，本发明一实施例提供一种(图案化的绝缘金属) 基板，包括一金属载板、一图案化的绝缘层及一图案化的导电层，其中图案化的绝缘层设置于金属载板上，且部分地覆盖金属载板，而图案化的导电层设置于图案化的绝缘层上。
本发明另一实施例提供一种功率模块封装，包括一(图案化的绝缘金属) 基板、一第一芯片及一第二芯片。基板包括一金属载板、一图案化的绝缘层及一图案化的导电层，其中图案化的绝缘层设置于金属载板上，且部分地覆盖金属载板，而图案化的导电层设置于图案化的绝缘层上。第一芯片设置于未被图案化的绝缘层所覆盖的金属载板上。第二芯片设置于图案化的导电层上，且电性连接第一芯片。
本发明另一实施例提供一种图案化的绝缘金属基板的制造方法，包括：提供一基板，具有一绝缘层及一图案化的导电层，且图案化的导电层覆盖绝缘层的一上表面；形成一黏着面于绝缘层的一下表面；形成一开口，穿过绝缘层；以及压合一图案化的金属载板于绝缘层的黏着面。
本发明另一实施例提供一种图案化的绝缘金属基板的制造方法，包括：提供一基板，具有一绝缘层及一图案化的导电层，且图案化的导电层覆盖绝缘层的一上表面；形成一黏着面于绝缘层的一下表面；形成一开口，穿过绝缘层；压合一金属载板于绝缘层的黏着面；以及图案化上述压合后的金属载板。
本发明另一实施例提供一种封装结构，包括一(图案化的绝缘金属)基板、一第一芯片、一第二芯片以及一导电元件。基板包括一金属载板、一图案化的绝缘层及一图案化的导电层，其中图案化的绝缘层设置于金属载板上，且部分地覆盖金属载板，而图案化的导电层设置于图案化的绝缘层上。第一芯片设置于未被图案化的绝缘层所覆盖的金属载板上。第二芯片设置于图案化的导电层上，且经由上述导电元件电性连接第一芯片。
其中该导电元件可包括：一或多个接合导电片、一或多个重布线层结构或上述的组合，其中该重布线层结构包括相互堆叠的至少一线路层及一绝缘层。
为让本发明的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下。
附图说明
图1显示一现有功率模块封装的剖面示意图。
图2显示根据本发明一实施例的功率模块封装的立体示意图。
图3显示图2中的功率模块封装的分解图。
图4显示图2中的功率模块封装的剖面示意图。
图5显示根据本发明另一实施例的功率模块封装的剖面示意图。
图6显示根据本发明另一实施例的功率模块封装的剖面示意图。
图7显示根据本发明另一实施例的功率模块封装的立体示意图。
图8显示根据本发明另一实施例的功率模块封装的立体示意图。
图9A至图9E显示根据本发明一实施例的功率模块封装中的一图案化的绝缘金属基板的制造方法的剖面示意图。
图10显示根据本发明一些实施例的功率模块封装的立体示意图。
图11A至图11B显示根据本发明一些实施例的功率模块封装的剖面示意图。
图12A至图12B显示根据本发明一些实施例的功率模块封装的剖面示意图。
图13A至图13B显示根据本发明一些实施例的功率模块封装的剖面示意图。
图14A至图14D显示根据本发明一些实施例的具有重布线层结构(redistribution layer structure)的功率模块封装的剖面示意图。
图15A至图15C显示根据本发明一些实施例的具有封装材料的功率模块封装的剖面示意图。
图16显示根据本发明一些实施例的功率模块封装的立体示意图。
图17显示根据本发明一些实施例的功率模块封装的立体示意图。
图18显示根据本发明一些实施例的功率模块封装的立体示意图。
其中，附图标记说明如下：
1～现有功率模块封装；
2、3、4、5、6、7、8、9、10～功率模块封装；
10A～金属载板；
11～绝缘层；
12～导电层；
13～功率芯片；
14～导线；
20～图案化的绝缘金属基板；
22～载板、金属载板；
24～绝缘层；
26～导电层；
30～第一半导体功率芯片；
30D～第一漏极接垫；
30G～第一栅极接垫；
30S～第一源极接垫；
32～上表面；
34～下表面；
40～第二半导体功率芯片；
40G～第二栅极接垫；
40S～第二源极接垫；
42～上表面；
44～下表面；
50～被动元件；
52～第一端子；
54～第二端子；
60～导线；
100～绝缘层；
100A～上表面；
100B～下表面；
101～导电层；
102～黏着面；
103～开口；
104～金属载板；
221～第一部分；
222～第二部分；
222A～孔洞；
222B～开口；
223～第三部分；
224～第四部分；
241～第一图案化绝缘部分；
242～开口；
243～第二图案化绝缘部分；
261～第一图案化导电部分；
262～第二图案化导电部分；
P～界面材料；
S～基板；
70～导电元件；
70A、70B、70C、70D、70E、70F～接合导电片或重布线层结构；
A1-A2、B1-B2～切割线；
W～宽度；
L～脚部；
T～厚度；
Q～接合材料；
U～突出部；
M1、M2～金属化层；
I～绝缘层；
E～封装材料。
具体实施方式
以下说明本发明的较佳实施例。此说明的目的在于提供本发明的总体概念而并非用以局限本发明的范围。
在以下所说明的本发明实施例中，所称的方位“上”、“下”，仅是用来表示所附图式中相对的位置关系，并非用来限制本发明。
在以下图式或说明书描述中，相似或相同的部分皆使用相同的符号。另外，在图式中，实施例的形状或厚度可扩大，以简化或是方便标示。应了解的是，在图式中未绘示或说明书中未描述的元件，为所属技术领域中具有通常知识者所知的形式。
请参照图2至图4，其中图2显示根据本发明一实施例的功率模块封装2 的立体示意图，图3显示图2中的功率模块封装2的分解图，及图4显示图 2中的功率模块封装2的剖面示意图。根据本发明一实施例，功率模块封装2 包括一图案化的绝缘金属基板(patternedinsulation metal substrate，简称 PIMS)20、一第一半导体功率芯片30、一第二半导体功率芯片40、两个被动元件50及多条导线60。应了解的是，图2至图4中仅省略一封装层，例如一环氧树脂模塑料(epoxy molding compound，简称EMC)，用以覆盖位于图案化的绝缘金属基板20上的第一半导体功率芯片30、第二半导体功率芯片 40、被动元件50及导线60。
如图2至图4所示，图案化的绝缘金属基板20包括一载板22、一绝缘层24及一导电层26。在本实施例中，载板22为一导线架(lead frame)，具有多个图案化的及分开的部分。具体而言，载板22可由金属材质(例如铜或其他含铜的合金)制成，并具有一第一部分221、一第二部分222、一第三部分 223及一第四部分224。绝缘层24的材料可包括玻璃纤维(fiberglass)、环氧树脂钢板(epoxy fiberglass)、环氧树脂(epoxies)、硅树脂(silicones)、聚氨酯 (urethanes)、或丙烯酸酯(acrylates)，并可加入氧化铝(aluminumoxide)、氮化硼(boron nitride)、氧化锌(zinc oxide)、或氮化铝(aluminum nitride)等填料以增加其导热性。绝缘层24形成于载板22上。值得一提的是，绝缘层24为一图案化的(patterned)绝缘层，其部分地覆盖金属载板22的第二部分222。在本实施例中，图案化的绝缘层24具有至少一开口242，可使得金属载板22的第二部分222的至少一部分为暴露的。此外，导电层26亦可由金属材质(例如铜，或者于铜表面可进一步形成材质例如镀镍钯金或钛金的表面处理层) 制成，且形成于绝缘层24上。值得一提的是，导电层26为一图案化的导电层，其部分地覆盖绝缘层24。在本实施例中，图案化的导电层26为L字型、邻近绝缘层24的多个边缘，且部分地围绕绝缘层24的开口242(请参照第3 图)，但本发明并不以此为限。
如图2至图4所示，第一半导体功率芯片30设置于未被绝缘层24所覆盖的金属载板22的第二部分222上。更详细而言，第一半导体功率芯片30 设置于绝缘层24的开口242中，并直接连接金属载板22。由此，自第一半导体功率芯片30所产生的热可通过金属载板22的(未被绝缘层24所覆盖的) 一底面有效地逸散。相反地，在图1所示的现有功率模块封装1中，自功率芯片13所产生的热则无法通过金属载板10A有效地逸散，因为受到整面的(full-faced)绝缘层11的阻隔。因此，藉由图案化的绝缘层24的设计，本实施例的功率模块封装2可具有更好的散热能力，从而可提高其可靠性。
如图2至图4所示，第二半导体功率芯片40设置于导电层26上。再者，前述第一、第二半导体功率芯片30及40可分别通过一接口材料P安装于金属载板22及导电层26上，其中接口材料P可包括金属合金、锡膏、银胶或其他导电黏着剂。
在本实施例中，第一半导体功率芯片30为一水平式(lateral)半导体元件，例如为一高电压开关(High-Voltage switch，简称HV switch)，而第二半导体功率芯片40为一垂直式(vertical)半导体元件，例如为一低电压开关 (Low-Voltage switch，简称LVswitch)。
如图2及图3所示，第一半导体功率芯片30具有相对的一主动端(亦即上表面32A)及一底面端(亦即下表面32B)，其中主动端上设有多个电极(包括一第一漏极接垫(firstdrain pad)30D、一第一源极接垫(first source pad)30S及一第一栅极接垫(first gatepad)30G)，且第一半导体功率芯片30通过底面设置于金属载板22上。值得一提的是，金属载板22的第二部分222未电性连接第一半导体功率芯片30(水平式半导体元件)，而仅具有与第一半导体功率芯片30的底面相同的电性。由此，金属载板22的第二部分222的底面可直接暴露在外，从而有利于散热，且不须因为绝缘上的顾虑而使用一绝缘层以覆盖之。此外，第二半导体功率芯片40具有相对的一上表面42及一下表面44，其中上表面42上设有多个电极(包括一第二源极接垫(second source pad)40S 及一第二栅极接垫(second gate pad)40G)，而下表面44上设有一电极(一第二漏极接垫(图未示))，且第二半导体功率芯片40通过下表面44设置于导电层 26上。
如图2所示，在本实施例中，第一半导体功率芯片30的第一漏极接垫 30D通过至少一导线60电性连接金属载板22的第一部份221，第一源极接垫30S通过至少一导线60电性连接导电层26，及第一栅极接垫30G通过至少一导线60电性连接第二半导体功率芯片40的第二源极接垫40S。另外，第二半导体功率芯片40的第二源极接垫40S通过至少一导线60电性连接金属载板22的第三部分223，第二栅极接垫40G通过至少一导线60电性连接金属载板22的第四部分224，及位于第二半导体功率芯片40的下表面44上的第二漏极接垫电性连接导电层26(亦即，第二漏极接垫亦电性连接第一半导体功率芯片30的第一源极接垫30S)。
再者，在本实施例中，第一半导体功率芯片30具有多个并联的高电压晶体管(图未示)，其中每一个高电压晶体管，例如为一水平式空乏型(Depletion mode，简称D-mode)晶体管，具有与第一源极接垫30S电性连接的一第一源极(first source electrode)、与第一漏极接垫30D电性连接的一第一漏极(first drain electrode)及与第一栅极接垫30G电性连接的一第一栅极(first gate electrode)。此外，前述在第一半导体功率芯片30中的每一个高电压晶体管为一含氮的(nitride-based)晶体管，例如为一具有氮化镓(GalliumNitride)材料的高电子移动率晶体管(High Electron Mobility Transistor，HEMT))。另一方面，在本实施例中，第二半导体功率芯片40具有多个并联的低电压晶体管(图未示)，其中每一个低电压晶体管，例如为一垂直式增强型(Enhancement mode，简称E-mode)晶体管，具有与第二源极接垫40S电性连接的一第二源极 (second source electrode)、与第二漏极接垫电性连接的一第二漏极(second drain electrode)及与第二栅极接垫40G电性连接的一第二栅极(second gate electrode)。此外，前述每一个低电压晶体管为一含硅的(silicon-based)晶体管。
如图2及图3所示，两个被动元件50设置于图案化的绝缘金属基板20 上。其中，每一个被动元件50可为一电阻器、电容器、或电感器，并具有一第一端子52及一第二端子54。在本实施例中，其中一被动元件50电性连接金属载板22的第一部份221及导电层26，而另一被动元件50则电性连接导电层26及金属载板22的第三部分223。此外，前述两个被动元件50亦可分别通过一接口材料P安装于图案化的绝缘金属基板20上，且接口材料P可包括金属合金、锡膏、银胶或其他导电黏着剂。
藉由前述结构设计，可实现包括第一半导体功率芯片30、第二半导体功率芯片40及两个被动元件50的一串联开关电路(cascade switch circuit)。相较于一单一开关电路(single switch circuit)，串联开关电路适于承载较大的电压及切换速度较快。
值得一提的是，前述功率模块封装2可被应用在一功率(power)相关的产品，例如变压器或电源供应器。此外，相较于现有功率模块封装1(图1)，由于具有图案化的绝缘金属基板(PIMS)20的设计，功率模块封装2可具有更好的散热能力及更高的可靠性。
尽管前述实施例中的第一半导体功率芯片30为一水平式半导体元件，但本发明不以此为限。在一些实施例中，第一半导体功率芯片30亦可为一垂直式半导体元件，只要金属载板22的底面可由一绝缘层所覆盖。另外，在一些实施例中，第一、第二半导体功率芯片30及40亦可为其他主动元件或驱动器(drivers)，而非一高电压开关及一低电压开关。
接着，介绍本发明不同实施例的一些具有不同结构的功率模块封装。
图5显示根据本发明另一实施例的功率模块封装3的剖面示意图。其中，功率模块封装3与前述实施例(图2至图4)的功率模块封装2的差异在于，金属载板22的第二部分222更具有一孔洞222A(或一凹槽或一狭长孔)，形成于其上表面，且未被绝缘层24所覆盖(亦即孔洞222A形成于开口242中)，另外，第一半导体功率芯片30设置于孔洞222A中。由此，第一半导体功率芯片30可抵接孔洞222A的侧壁及底面，使得自第一半导体功率芯片30所产生的热可更轻易地转移到金属载板22，随后再通过金属载板22有效地逸散。
图6显示根据本发明另一实施例的功率模块封装4的剖面示意图。其中，功率模块封装4与前述实施例(图2至图4)的功率模块封装2的差异在于，金属载板22的第二部分222更具有一开口222B，贯穿第二部分222的上、下表面，且未被绝缘层24所覆盖(亦即开口222B形成于开口242中)，另外，第一半导体功率芯片30设置于开口222B中。由此，第一半导体功率芯片30 可抵接开口222B的侧壁，并由金属载板22的底面直接暴露在外，使得自第一半导体功率芯片30所产生的热可更有效地逸散。
图7显示根据本发明另一实施例的功率模块封装5的立体示意图。其中，功率模块封装5与前述实施例(图2至图4)的功率模块封装2的差异在于，绝缘层24可被图案化以具有相互分开的一第一图案化绝缘部分241及一第二图案化绝缘部分243。此外，第一半导体功率芯片30设置于第一、第二图案化绝缘部分241及243之间(亦即第一半导体功率芯片30设置于第一、第二图案化绝缘部分241及243之间的一开口242(一暴露区域)中)。换言之，第一、第二图案化绝缘部分241及243被配置于第一半导体功率芯片30的两相对侧 (相对地，第2图所示实施例中的图案化的绝缘层24则围绕第一半导体功率芯片30)，且第一半导体功率芯片30直接连接金属载板22的第二部分222。
再者，在本实施例(图7)中，导电层26可被图案化以具有相互分开的一第一图案化导电部分261及一第二图案化导电部分262，且第一、第二图案化导电部分261及262分别设置于第一、第二图案化绝缘部分241及243上并部分地覆盖第一、第二图案化绝缘部分241及243。此外，第二半导体功率芯片40设置于第一图案化导电部分261上并与其电性连接。值得一提的是，在本实施例中，第一半导体功率芯片30的第一漏极接垫30D是先电性连接位于第二图案化绝缘部分243上的第二图案化导电部分262，接着再通过多条导线60电性连接金属载板22的第一部份221，而非如同图2所示的实施例，其第一半导体功率芯片30的第一漏极接垫30D是直接通过至少一导线 60电性连接金属载板22的第一部份221。
图8显示根据本发明另一实施例的功率模块封装6的立体示意图。其中，功率模块封装6与前述实施例(图2至图4)的功率模块封装2的差异在于，导电层26可被图案化以具有相互分开的一第一图案化导电部分261及一第二图案化导电部分262，且第一、第二图案化导电部分261及262被配置于第一半导体功率芯片30的两相对侧。此外，第二半导体功率芯片40设置于第一图案化导电部分261上并与其电性连接。值得一提的是，在本实施例中，第一半导体功率芯片30的第一漏极接垫30D是先电性连接位于绝缘层24上的第二图案化导电部分262，接着再通过多条导线60电性连接金属载板22的第一部份221，而非如同图2所示的实施例，其第一半导体功率芯片30的第一漏极接垫30D是直接通过至少一导线60电性连接金属载板22的第一部份 221。
再者，尽管本实施例(图8)中的图案化的绝缘层24是围绕第一半导体功率芯片30配置，但其亦可以部分地围绕第一半导体功率芯片30，也就是说，第一半导体功率芯片30的至少一侧可不被该图案化的绝缘层24所围绕。
接着，根据本发明一实施例，介绍前述图案化的绝缘金属基板20(图2 至图8)的一种制造方法。请依序参照图9A至图9E。
如图9A所示，首先提供一基板S，具有一绝缘层100及形成于绝缘层 100的上表面100A上的一导电层101。在本实施例中，绝缘层100的材料可包括玻璃纤维(fiberglass)、环氧树脂钢板(epoxy fiberglass)、环氧树脂(epoxies)、硅树脂(silicones)、聚氨酯(urethanes)、或丙烯酸酯(acrylates)，并可加入氧化铝(aluminum oxide)、氮化硼(boronnitride)、氧化锌(zinc oxide)、或氮化铝 (aluminum nitride)等填料以增加其导热性，而导电层101可由金属材质(例如铜，或者于铜表面可进一步形成材质为镀镍钯金或钛金的表面处理层)制成。随后，如图9B所示，执行一光微影(photolithography)制程，包括曝光(exposure)、显影(developing)及蚀刻(etching)等步骤，以使得绝缘层100上的导电层101被图案化。
如图9C所示，在导电层101被图案化之后，形成一黏着面(adhesive side)102于绝缘层100的下表面100B。在本实施例中，黏着面102以施加一双面黏着剂于绝缘层100的下表面100B的方式而形成。随后，如图9D所示，执行一化学蚀刻、或一钻孔(drill)制程，例如激光或机械钻孔，以形成穿过绝缘层100的至少一开口103。应了解的是，图案化的导电层101、经过化学蚀刻或钻孔制程的绝缘层100及开口103，即分别对应于前述图案化的绝缘金属基板20(第2～8图)中的图案化的导电层26、图案化的绝缘层24及开口242。
如图9E所示，在穿过绝缘层100的开口103被形成之后，提供一图案化的金属载板104(材质例如铜或其他含铜的合金)，例如一导线架(lead frame)，随后，压合(laminate)图案化的金属载板104于绝缘层100的黏着面102，其中金属载板104对应于前述图案化的绝缘金属基板20(第2～8图)中的金属载板22，如此即完成一图案化的绝缘金属基板(PIMS)的制造，且该图案化的绝缘金属基板包括一金属载板、设置于金属载板上且部分地覆盖金属载板的一图案化的绝缘层及设置于图案化的绝缘层上的一图案化的导电层。
应了解的是，在本发明一些实施例中，在穿过绝缘层100的开口103被形成之后(图9D)，亦可先压合一未图案化的(non-patterned)金属载板104于绝缘层100的黏着面102，随后，再利用例如激光钻孔或光微影制程(包括曝光、显影及蚀刻等步骤)对压合后的金属载板104进行图案化(图9E)，以完成一图案化的绝缘金属基板(PIMS)的制造，且该图案化的绝缘金属基板包括一金属载板、设置于金属载板上且部分地覆盖金属载板的一图案化的绝缘层及设置于图案化的绝缘层上的一图案化的导电层。
综上所述，本发明提供一种包括一图案化的绝缘金属基板(PIMS)的功率模块封装。由于图案化的绝缘金属基板中的图案化的绝缘层不会阻隔安装于基板上的半导体功率芯片所产生的热的传递，故功率模块封装可具有更好的散热能力及更高的可靠性。
以下将揭露本发明一些实施例的封装结构，其中导电元件被用来连接封装结构中的不同的元件。上述导电元件可包括接合导电片(clip bond)或重布线层结构。上述接合导电片或重布线层结构相对于导线具有较大的冷却面积，而可提供更好的散热能力。
图10显示根据本发明一些实施例的功率模块封装7的立体示意图。功率模块封装7包括图案化的绝缘金属基板20，其类似于功率模块封装2的图案化的绝缘金属基板，两者之间的其中一个差异在于导电元件70被配置来连接功率模块封装7中的不同的元件。
图11A至图11B显示功率模块封装7沿着图10中的切割线A1-A2及 B1-B2的剖面示意图。在一些实施例中，导电元件70可包括多个接合导电片(例如:70A、70B、70C、70D、70E及70F)。可以适当的导电材料形成接合导电片，例如:铜、金、铝、其合金或上述的组合。任一接合导电片电性连接至第一半导体功率芯片30、第二半导体功率芯片40及图案化的绝缘金属基板 20中的至少两者。举例而言，接合导电片70A电性连接至第一半导体功率芯片30的第一栅极接垫30G以及第二半导体功率芯片40的第二源极接垫40S，接合导电片70D电性连接至图案化的导电层26及第一源极接垫30S，接合导电片70C电性连接至金属载板22及第一漏极接垫30D。如图10、11A及 11B所示，任一接合导电片具有厚度T以及宽度W。举例而言，上述厚度T 可为25-1000μm，而宽度W可为50-2000μm，其大于导线的直径(例如: 10-500μm)。
如图11A及11B所示，上述接合导电片中的至少一者可具有一脚部(leg portion)，其朝向图案化的绝缘金属基板20弯折。举例而言，接合导电片70B 具有脚部L，其朝向图案化的绝缘金属基板20弯折且电性连接至图案化的绝缘金属基板20的金属载板22，而接合导电片70D具有脚部L，其朝向图案化的绝缘金属基板20弯折且电性连接至图案化的绝缘金属基板20的图案化的导电层26。接合导电片的脚部L可远离第一半导体芯片30及第二半导体芯片40之间的区域(例如:接合导电片70B及70C)。然而，接合导电片的脚部L亦可位于第一半导体芯片30及第二半导体芯片40之间(例如:接合导电片70D)。在一些实施例中，因为接合导电片具有朝向图案化的绝缘金属基板 20弯折的脚部(例如:图11B中的接合导电片70D)，图案化的绝缘金属基板 20不须向接合导电片突出即可电性连接至接合导电片。
如图11A及图11B所示，可使用接合材料Q连接上述多个接合导电片至图案化的绝缘金属基板20、第一半导体功率芯片30或第二半导体功率芯片40。举例而言，接合材料Q可包括金属合金、锡膏、银胶或其他适当的导电胶。在一些实施例中，可将接合材料Q设计成具有不同的厚度，使得任一上述的接合导电片的上表面可与金属载板22的上表面实质平行。在一些实施例中，可将接合材料Q设计成具有不同的厚度，使得上述多个接合导电片的上表面实质上在相同的水平。
在一些实施例中，如图12A及12B所示，图案化的绝缘金属基板20可包括至少一朝向上述多个接合导电片的其中一者突出的突出部U，其电性连接至接合导电片。举例而言，如图12A所示，图案化的绝缘金属基板20可包括朝向接合导电片70B突出的突出部U，且突出部U电性连接至接合导电片 70B。在一些实施例中，不具有脚部的接合导电片可经由突出部U连接至图案化的绝缘金属基板20。举例而言，如图12A所示，不具有脚部的接合导电片70B经由突出部U连接至金属载板22，而如图12B所示，不具有脚部的接合导电片70D经由突出部U连接至图案化的导电层26。如图12B所示，突出部U可包括图案化的绝缘层24的一部分、图案化的导电层26的一部分以及金属载板22的一部分。如图12A所示，图案化的绝缘金属基板20的突出部U可远离第一半导体芯片30及第二半导体芯片40之间的区域。然而，如图12B所示，图案化的绝缘金属基板20的突出部U亦可位于第一半导体芯片30及第二半导体芯片40之间。在一些实施例中，不具有朝向图案化的绝缘金属基板20弯折的脚部的接合导电片可经由突出部U电性连接至图案化的绝缘金属基板20(例如:图12B中的金属片70D)。
在一些实施例中，如图13A及13B所示，一些接合导电片具有脚部L，其经由突出部U电性连接至图案化的绝缘金属基板20。举例而言，接合导电片70C的脚部L连接至包括金属载板22的一部分的突出部U，而接合导电片70D的脚部L则连接至包括金属载板22的一部分、图案化的绝缘层24的一部分及图案化的导电层26的一部分的突出部U。
在一些实施例中，如图14A至14D所示，可以重布线层结构(例如:图14A 的重布线层结构70B及70A、图14B的重布线层结构70A-70C、图14C的重布线层结构70D、图14D的重布线层结构70D)替换接合导电片。重布线层结构可增加布线的弹性。重布线层结构可包括相互堆叠于彼此之上的至少一线路层(例如:金属化层)及至少一绝缘层。举例而言，重布线层结构可包括金属化层M1、金属化层M2以及设置于金属化层M1及M2之间的绝缘层I。举例而言，金属化层M1及M2可由铜、金、铝、其合金或上述的组合所形成。在一些实施例中，金属化层M1及M2可具有不同的厚度(例如:较靠近基板的金属化层M1的厚度大于金属化层M2的厚度)。在一些实施例中，厚度较大的金属化层可用于高电流回路(例如:功率回路(powerloop))，厚度较小的金属化层可用于低电流回路(例如:讯号回路(signal loop))，因此可提升装置效能。
在一些实施例中，如图15A、15B及15C所示，使用封装材料E(例如: 环氧树脂模塑料)以提供机械保护并避免封装结构受到污染。封装材料E可围绕图案化的绝缘金属基板20、第一半导体芯片30、第二半导体芯片40及导电元件70。封装材料E可暴露出导电元件70的一部分。举例而言，如图15B 及15C所示，导电元件70的上表面自封装材料E露出，因而可具有更好的散热能力。在一些实施例中，如图15C所示，封装材料E的上表面与导电元件70的上表面位于相同的水平。
图16显示根据本发明一些实施例的功率模块封装8的立体示意图。功率模块封装8可包括类似于功率模块封装5的图案化的绝缘金属基板20。功率模块封装8与功率模块封装5的其中一个差异在于一些功率模块封装5的接合导线在功率模块封装8中被前述的导电元件70所替换。如图16所示，前述的导电元件70可被用来连接功率模块封装8的元件。此外，前述的突出部 U亦可用于功率模块封装8。
图17显示根据本发明一些实施例的功率模块封装9的立体示意图。功率模块封装9可包括类似于功率模块封装6的图案化的绝缘金属基板20。功率模块封装9与功率模块封装6的其中一个差异在于一些功率模块封装6的接合导线在功率模块封装9中被前述的导电元件70所替换。如图17所示，前述的导电元件70可被用来连接功率模块封装9的元件。此外，前述的突出部 U亦可用于功率模块封装9。
图18显示根据本发明一些实施例的功率模块封装10的立体示意图。如图18所示，可同时使用导电元件70与导线60以连接功率模块封装10的元件。举例而言，导线60可用来连接第一半导体功率芯片30的第一栅极接垫 30G及第二半导体功率芯片40的第二栅极接垫40G至图案化的绝缘金属基板20，而导电元件70可用来连接第一半导体功率芯片30及第二半导体功率芯片40的源极接垫或漏极接垫至图案化的绝缘金属基板20。应注意的是，设置于未被图案化的绝缘层24覆盖的金属载板22上的第一半导体功率芯片 30可为水平式半导体元件，而设置于图案化的导电层26上的第二半导体功率芯片40可为水平式半导体元件或垂直式半导体元件。
应注意的是，前述的导电元件70及突出部U可应用于前述所有实施例的功率模块封装。举例而言，前述的导电元件70及突出部U亦可应用于图5 及图6所绘示的功率模块封装3及4。
如前文所述，本发明实施例提供了具有图案化的绝缘金属基板的封装结构。因为图案化的绝缘金属基板中的图案化的绝缘层不会阻隔安装于基板上的半导体功率芯片所产生的热的传递，故功率模块封装可具有良好的散热能力及高的可靠性。此外，因为封装结构具有冷却面积较大的导电元件(例如: 接合导电片或重布线层结构)，其可具有更佳的散热能力及更高的可靠性。
虽然本发明以前述的实施例揭露如上，然其并非用以限定本发明。本发明所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可做些许的更动与润饰。因此本发明的保护范围当视所附的权利要求书所界定者为准。

Claims (18)

1.一种封装结构，包括：
一基板，包括一金属载板、一图案化的绝缘层以及一图案化的导电层，该图案化的绝缘层设置于该金属载板上且部分地覆盖该金属载板，该图案化的导电层设置于该图案化的绝缘层上；
一第一芯片，设置于未被该图案化的绝缘层所覆盖的该金属载板上；以及
一第二芯片，设置于该图案化的导电层上，且经由一导电元件电性连接至该第一芯片；
其中该导电元件包括:
一或多个接合导电片、一或多个重布线层结构或上述的组合，其中该重布线层结构包括相互堆叠的至少一线路层及一绝缘层；
其中该封装结构还包括:一封装材料，包围该基板、该第一芯片、该第二芯片及该导电元件；
其中该导电元件的一部分自该封装材料露出。
2.如权利要求1所述的封装结构，其中所述多个接合导电片或重布线层结构的任一者电性连接至该第一芯片、该第二芯片及该基板中的至少两者。
3.如权利要求1所述的封装结构，其中该基板包括朝向该导电元件突出的一突出部，且该突出部电性连接至该导电元件。
4.如权利要求3所述的封装结构，其中该基板的突出部包括该图案化的绝缘层的一部分及该图案化的导电层的一部分，且该图案化的导电层的该部分设置于该图案化的绝缘层的该部分上。
5.如权利要求3所述的封装结构，其中该基板的突出部位于该第一芯片及该第二芯片之间。
6.如权利要求3所述的封装结构，其中该导电元件包括一脚部，该脚部电性连接至该基板的突出部。
7.如权利要求1所述的封装结构，其中该导电元件包括朝向该基板弯折的一脚部，且该脚部电性连接至该基板。
8.如权利要求7所述的封装结构，其中该脚部位于该第一芯片及该第二芯片之间。
9.如权利要求7所述的封装结构，其中该脚部位于远离该第一芯片及该第二芯片之间的一区域。
10.如权利要求1所述的封装结构，其中该金属载板具有一孔洞或一凹槽，且该第一芯片设置于其中。
11.如权利要求1所述的封装结构，其中该金属载板具有一狭长孔，且该第一芯片设置于其中。
12.如权利要求1所述的封装结构，其中该金属载板具有一开口，且该第一芯片设置于其中。
13.如权利要求1所述的封装结构，其中该图案化的绝缘层包括一第一部分，该第一部分被该图案化的导电层的一部份覆盖，且该第二芯片设置于该图案化的导电层的该部分上。
14.如权利要求1所述的封装结构，其中该图案化的绝缘层包括一第一图案化绝缘部分及一第二图案化绝缘部分，该第一图案化绝缘部分被该图案化的导电层的一部份所覆盖，而该第二图案化绝缘部分被该图案化的导电层的另一部分所覆盖，且该第一芯片电性连接至该图案化的导电层的该另一部分。
15.如权利要求1所述的封装结构，其中该第一芯片直接连接该金属载板。
16.如权利要求1所述的封装结构，其中该第一芯片包括一水平式半导体元件。
17.如权利要求1所述的封装结构，其中该第二芯片包括一垂直式半导体元件。
18.如权利要求1所述的封装结构，其中该第一芯片具有相对的一主动端及一底面端，该主动端上设有多个电极，且该第一芯片通过该底面端设置于该金属载板上。
CN201710281753.8A 2016-04-29 2017-04-26 封装结构 Active CN107393887B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/142,588 US9865531B2 (en) 2016-04-29 2016-04-29 Power module package having patterned insulation metal substrate
US15/142,588 2016-04-29
US15/484,714 US10056319B2 (en) 2016-04-29 2017-04-11 Power module package having patterned insulation metal substrate
US15/484,714 2017-04-11

Publications (2)

Publication Number Publication Date
CN107393887A CN107393887A (zh) 2017-11-24
CN107393887B true CN107393887B (zh) 2019-07-16

Family

ID=60158550

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710281753.8A Active CN107393887B (zh) 2016-04-29 2017-04-26 封装结构

Country Status (3)

Country Link
US (1) US10056319B2 (zh)
CN (1) CN107393887B (zh)
TW (1) TWI633631B (zh)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6991776B2 (ja) * 2017-08-02 2022-01-13 ローム株式会社 半導体装置
US10741466B2 (en) 2017-11-17 2020-08-11 Infineon Technologies Ag Formation of conductive connection tracks in package mold body using electroless plating
JP6822939B2 (ja) * 2017-11-30 2021-01-27 株式会社東芝 半導体装置
CN110010559A (zh) 2017-12-08 2019-07-12 英飞凌科技股份有限公司 具有空气腔体的半导体封装件
CN111587488B (zh) * 2018-01-17 2024-03-19 新电元工业株式会社 电子模块
US10886201B2 (en) * 2018-02-15 2021-01-05 Epistar Corporation Power device having a substrate with metal layers exposed at surfaces of an insulation layer and manufacturing method thereof
US10593610B2 (en) * 2018-07-03 2020-03-17 Integra Technologies, Inc. Semiconductor power device including wire or ribbon bonds over device active region
US20200135632A1 (en) * 2018-10-24 2020-04-30 Texas Instruments Incorporated Die isolation on a substrate
SG10201811582WA (en) * 2018-12-24 2020-07-29 Delta Electronics Int’L Singapore Pte Ltd Package structure and manufacturing method thereof
US10796981B1 (en) * 2019-04-04 2020-10-06 Infineon Technologies Ag Chip to lead interconnect in encapsulant of molded semiconductor package
US11133281B2 (en) 2019-04-04 2021-09-28 Infineon Technologies Ag Chip to chip interconnect in encapsulant of molded semiconductor package
CN112018052A (zh) 2019-05-31 2020-12-01 英飞凌科技奥地利有限公司 具有可激光活化模制化合物的半导体封装
US11469163B2 (en) * 2019-08-02 2022-10-11 Semiconductor Components Industries, Llc Low stress asymmetric dual side module
US10861766B1 (en) * 2019-09-18 2020-12-08 Delta Electronics, Inc. Package structures
CN113410200B (zh) * 2020-03-16 2023-12-05 苏州捷芯威半导体有限公司 一种芯片封装框架和芯片封装结构
US11329025B2 (en) 2020-03-24 2022-05-10 Texas Instruments Incorporated Multi-chip package with reinforced isolation
US11587800B2 (en) 2020-05-22 2023-02-21 Infineon Technologies Ag Semiconductor package with lead tip inspection feature
TWI763213B (zh) * 2020-12-29 2022-05-01 新唐科技股份有限公司 封裝結構
DE102022122823A1 (de) 2022-09-08 2024-03-14 Infineon Technologies Ag Chip-gehäuse, chip-system, verfahren zur herstellung eines chip-gehäuses und verfahren zur herstellung eines chipsystems

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101819964A (zh) * 2009-02-27 2010-09-01 株式会社电装 集成电路安装板、印刷布线板和制造集成电路安装板方法
CN105514077A (zh) * 2014-10-13 2016-04-20 通用电气公司 具有引线接合件的功率覆层结构和制造其的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060006510A1 (en) * 2004-07-06 2006-01-12 Koduri Sreenivasan K Plastic encapsulated semiconductor device with reliable down bonds
US7683477B2 (en) * 2007-06-26 2010-03-23 Infineon Technologies Ag Semiconductor device including semiconductor chips having contact elements
DE102008017454B4 (de) 2008-04-05 2010-02-04 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit hermetisch dichter Schaltungsanordnung und Herstellungsverfahren hierzu
CN103855914B (zh) 2012-12-03 2017-04-05 台达电子工业股份有限公司 电源系统及其中的功率模块以及制作功率模块的方法
CN201845773U (zh) 2010-08-27 2011-05-25 苏州科医世凯半导体技术有限责任公司 大功率led封装模组
US9142426B2 (en) 2011-06-20 2015-09-22 Cyntec Co., Ltd. Stack frame for electrical connections and the method to fabricate thereof
US20130154123A1 (en) 2011-12-20 2013-06-20 Infineon Technologies Ag Semiconductor Device and Fabrication Method
CN103985683B (zh) * 2013-02-08 2017-04-12 精材科技股份有限公司 晶片封装体
JP2015220341A (ja) * 2014-05-19 2015-12-07 三菱電機株式会社 金属ベース基板、パワーモジュール、および金属ベース基板の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101819964A (zh) * 2009-02-27 2010-09-01 株式会社电装 集成电路安装板、印刷布线板和制造集成电路安装板方法
CN105514077A (zh) * 2014-10-13 2016-04-20 通用电气公司 具有引线接合件的功率覆层结构和制造其的方法

Also Published As

Publication number Publication date
US10056319B2 (en) 2018-08-21
TWI633631B (zh) 2018-08-21
US20170317015A1 (en) 2017-11-02
CN107393887A (zh) 2017-11-24
TW201806099A (zh) 2018-02-16

Similar Documents

Publication Publication Date Title
CN107393887B (zh) 封装结构
CN105981274B (zh) 电力用半导体模块
US9385111B2 (en) Electronic component with electronic chip between redistribution structure and mounting structure
EP3107120B1 (en) Power semiconductor module
US20170092596A1 (en) Power module and fabrication method for the same
CN105529317B (zh) 嵌入式封装装置
CN103972277B (zh) 半导体装置及其制造方法
JP2009239249A (ja) 半導体装置およびその製造方法
CN105244328B (zh) 将半导体裸片电耦合至接触焊盘的电子部件和方法
US20220122906A1 (en) Stacked transistor chip package with source coupling
KR20130006138A (ko) 전력 모듈 패키지 및 그 제조방법
CN103390612A (zh) 半导体器件、半导体器件模块以及半导体器件的制造方法
WO2021002132A1 (ja) 半導体モジュールの回路構造
CN104037152B (zh) 芯片载体结构、芯片封装及其制造方法
CN106129018B (zh) 包括金属衬底和嵌入层合体的半导体模块的电子设备
JP2012244160A (ja) パッケージ構造およびその製造方法
US9905439B2 (en) Power module package having patterned insulation metal substrate
CN103187375B (zh) 器件和用于制造电子器件的方法
CN104934398A (zh) 电子部件和引线框架
TWI650843B (zh) 基板、功率模組封裝、及圖案化的絕緣金屬基板之製造方法
CN207705191U (zh) 一种氮化镓器件及氮化镓封装结构
JP6305778B2 (ja) パワーモジュールおよびその製造方法
CN108155172A (zh) 集成电路封装
JP6538396B2 (ja) 半導体装置
JP2017011028A (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20221109

Address after: No. 252, Shanying Road, Guishan District, Taoyuan City, Taiwan, China, China (6/F)

Patentee after: Anchorage Semiconductor Co.,Ltd.

Address before: Taoyuan City, Taiwan, China

Patentee before: DELTA ELECTRONICS, Inc.

TR01 Transfer of patent right