CN101635277B - 为了无空隙的间隙填充制程的间隙壁外型塑造工程 - Google Patents
为了无空隙的间隙填充制程的间隙壁外型塑造工程 Download PDFInfo
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Abstract
本发明是有关于一种为了无空隙的间隙填充制程的间隙壁外型塑造工程,一种形成半导体元件的方法,其步骤为提供半导体基板;在半导体基板上形成栅极堆叠;紧邻栅极堆叠侧边形成栅极间隙壁;薄化栅极间隙壁;与在薄化栅极间隙壁步骤之后,在栅极间隙壁侧边形成次要栅极间隙壁。
Description
技术领域
本发明涉及一种半导体元件,特别是涉及一种金氧半导体(metal-oxide-semiconductor,MOS)元件的结构与制造方法,以改进间隙填充的问题。
背景技术
在持续缩小超大型集成电路(very large scale integrated,VLSI)的元件尺寸过程中,使得一个半导体芯片上可容纳较多的元件。此外,也改进了超大型集成电路电功率(power)的消耗与表现。然而,随着电路变的较小与较快,元件间的距离也缩小了。因此,导致了在填充相邻元件间的间隙时遭遇了问题。间隙填充的问题可利用图1A至图1D说明。请参阅图1A所示,形成相邻的栅极(即闸极,本文均称为栅极)堆叠4与14。接着,栅极间隙壁6与16分别形成于栅极堆叠4与14的侧边。请参阅图1B所示,薄化栅极间隙壁6与16,使得如图1A所示的厚度T1减少为如图1B所示的厚度T1’。在图1C中,接触蚀刻终止层(contact etch stop layer,CESL)8形成于栅极堆叠4与14之上,其中接触蚀刻终止层8延伸至栅极堆叠4与14间的间隙5。接下来,如图1D所示,形成介电材料层18以填补间隙5。
在如图1B所示的步骤中,栅极间隙壁6与16的薄化造成间隙5的长宽比缩小,此处所指间隙5的长宽比为高度H比上宽度W的值。因此,在如图1D所示的结构中,可完成较佳的间隙填充。然而,随着集成电路尺寸的缩小,造成间隙5的长宽比持续增加。因此,即使对栅极间隙壁6与16进行薄化,仍可能在介电材料层18中出现空隙19。尤其,为了进行后栅极制程(即工艺),而在栅极堆叠上形成硬质掩膜(即罩幕,本文均称为掩膜)层,造成栅极堆叠4与14的高度H增加,进而造成间隙5的长宽比增加。因此,需要可以改善间隙填充作用的新方法来形成金氧半导体元件。
由此可见,上述现有的半导体元件形成方法在方法与使用上,显然仍存在有不便与缺陷,而亟待加以进一步改进。为了解决上述存在的问题,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,而一般方法又没有适切的方法能够解决上述问题,此显然是相关业者急欲解决的问题。因此如何能创设一种新的为了无空隙的间隙填充制程的间隙壁外型塑造工程,实属当前重要研发课题之一,亦成为当前业界极需改进的目标。
发明内容
本发明的目的在于,克服现有的半导体元件形成方法存在的缺陷,而提供一种新的为了无空隙的间隙填充制程的间隙壁外型塑造工程,所要解决的技术问题是使其改善间隙填充的问题,尤其是小尺寸集成电路的间隙填充问题,非常适于实用。
本发明的目的及解决其技术问题是采用以下技术方案来实现的。依据本发明提出的一种半导体元件的形成方法,该形成方法包含以下步骤:提供一半导体基板;形成一栅极堆叠于该半导体基板上;形成一栅极间隙壁紧邻该栅极堆叠侧边;薄化该栅极间隙壁;以及在薄化该栅极间隙壁后,形成一次要栅极间隙壁于该栅极间隙壁的侧边。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体元件的形成方法,其更包含在该栅极堆叠侧边形成一密封层位于该栅极堆叠和该栅极间隙壁之间,其中该栅极间隙壁底边与该半导体基板的顶面接触。
前述的半导体元件的形成方法,其中在形成该栅极间隙壁的步骤后与薄化该栅极间隙壁的步骤前,该方法更包含:形成一源极/漏极区紧邻该栅极堆叠;以及形成一源极/漏极金属硅化物区于该源极/漏极(即汲极,本文均称为漏极)区上。
前述的半导体元件的形成方法,其中所述的次要栅极间隙壁的一外侧边缘直接位于该源极/漏极金属硅化物区之上。
前述的半导体元件的形成方法,其更包含:形成一接触蚀刻终止层于该栅极堆叠的上;进行一化学机械研磨以移除位于该栅极堆叠上的该接触蚀刻终止层的一部分;移除该栅极堆叠以形成一开口;以及在该开口中形成一栅极介电层与一栅极。
前述的半导体元件的形成方法,其中所述的栅极间隙壁为包含氮化硅的一单层间隙壁,以及该次要栅极间隙壁包含一氮化硅层与位于该氮化硅层上的一氧化层。
前述的半导体元件的形成方法,其中所述的次要栅极间隙壁的顶边低于该栅极间隙壁的顶边。
本发明的目的及解决其技术问题还采用以下技术方案来实现。依据本发明提出的一种半导体元件的形成方法,该形成方法包含以下步骤:提供一半导体基板;形成一栅极堆叠于该半导体基板上;形成一密封层于该栅极堆叠的侧边;形成一轻掺杂源极/漏极区于该半导体基板内;形成一栅极间隙壁于该密封层的侧边;形成一源极/漏极区,具有一内侧边缘与该栅极间隙壁的一外侧边缘对齐;形成一源极/漏极金属硅化物区于该源极/漏极区上;在形成该源极/漏极区与该源极/漏极金属硅化物区后,薄化该栅极间隙壁;以及在形成该源极/漏极金属硅化物区后,形成一次要栅极间隙壁于该栅极间隙壁的侧边,其中该次要栅极间隙壁的顶边较低于该栅极间隙壁的顶边。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体元件的形成方法,其更包含:形成一接触蚀刻终止层于该栅极堆叠、该次要栅极间隙壁与该源极/漏极金属硅化物区之上;形成一层间介电层于该接触蚀刻终止层之上;进行一化学机械研磨以移除该栅极堆叠上的部分的该接触蚀刻终止层与部分的该层间介电层;移除该栅极堆叠以形成一开口;以及在该开口中形成一栅极介电层与一栅极。
前述的半导体元件的形成方法,其更包含:在该开口中形成该栅极介电层与该栅极后,形成一附加的层间介电层于该层间介电层之上;以及形成一触孔栓塞于该层间介电层与该附加的层间介电层中,其中该触孔栓塞电性连接至该栅极。
前述的半导体元件的形成方法,其中使用一湿式蚀刻法薄化该栅极间隙壁。
前述的半导体元件的形成方法,其中形成该次要栅极间隙壁的步骤包含:地毯式形成一次要栅极间隙壁层;以及干式蚀刻该次要栅极间隙壁层。
本发明的目的及解决其技术问题另外再采用以下技术方案来实现。依据本发明提出的一种半导体元件的形成方法,该形成方法包含以下步骤:提供一半导体基板;形成一绝缘区,其至少一部分于该半导体基板中;形成一第一栅极堆叠与一第二栅极堆叠于该半导体基板上,其中该第一栅极堆叠与该第二栅极堆叠彼此相邻,且该第二栅极堆叠位于该绝缘区上;形成一轻掺杂源极/漏极区紧邻该第一栅极堆叠;形成一第一栅极间隙壁与一第二栅极间隙壁分别紧邻该第一栅极堆叠与该第二栅极堆叠的侧边;形成一源极/漏极区,具有一内侧边缘与该第一栅极间隙壁的一外侧边缘重合;形成一源极/漏极金属硅化物区于该源极/漏极区上;在形成该源极/漏极区与该源极/漏极金属硅化物区后,薄化该第一栅极间隙壁与该第二栅极间隙壁;在薄化该第一栅极间隙壁与该第二栅极间隙壁后,分别形成一第一次要栅极间隙壁与一第二次要栅极间隙壁于该第一栅极间隙壁与该第二栅极间隙壁的侧边;形成一接触蚀刻终止层于该第一栅极堆叠、该第二栅极堆叠与该源极/漏极金属硅化物区之上;以及填充一介电材料至该第一栅极间隙壁与该第二栅极间隙壁间的间隙,其中该介电材料位于该接触蚀刻终止层之上。
本发明的目的及解决其技术问题还可采用以下技术措施进一步实现。
前述的半导体元件的形成方法,其中所述的第一次要栅极间隙壁与该第二次要栅极间隙壁的顶端分别较低于该第一栅极间隙壁与该第二栅极间隙壁的顶端。
前述的半导体元件的形成方法,其中所述的第一次要栅极间隙壁的外侧边缘直接位于该源极/漏极金属硅化物区上。
本发明与现有技术相比具有明显的优点和有益效果。借由上述技术方案,本发明为了无空隙的间隙填充制程的间隙壁外型塑造工程至少具有下列优点及有益效果:本发明的优点特征为改善间隙填充的问题,尤其是小尺寸集成电路的间隙填充问题。
综上所述,本发明一种形成半导体元件的方法,其步骤为提供半导体基板;在半导体基板上形成栅极堆叠;紧邻栅极堆叠侧边形成栅极间隙壁;薄化栅极间隙壁;与在薄化栅极间隙壁步骤之后,在栅极间隙壁侧边形成次要栅极间隙壁。本发明在技术上有显著的进步,具有明显的积极效果,诚为一新颖、进步、实用的新设计。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,而可依照说明书的内容予以实施,并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂,以下特举较佳实施例,并配合附图,详细说明如下。
附图说明
图1A至图1D是传统的间隙填充制程示意图。
图2至图12是使用后栅极制程制造本发明一较佳实施例的中间阶段制程的剖面图。
图12是利用前栅极制程形成的实施例的剖面图。
4、14:栅极堆叠 5、44:间隙
6、16:栅极间隙壁 8、40:接触蚀刻终止层
18:介电材料 19:空隙
30:基板 42:层间介电层
56:层间介电层 58:触孔栓塞
100、200:区域 104、204:栅极介电质
106、206:栅极 108、208:硬质掩膜层
110、210;密封层 112:轻掺杂源极/漏极区
114、214:栅极间隙壁 120:源极/漏极区
122:金属硅化物区 130:介电层
1301:第一子层 1302:第二子层
132:次要间隙壁 1321/2321:第一部分
1322/2322:第二部分 136、236:顶点
150:栅极介电层 152:栅极
202:浅沟槽隔离区 H、H1、H2:高度
T1、T1’、T2、T3、T4:厚度 W:宽度
具体实施方式
为更进一步阐述本发明为达成预定发明目的所采取的技术手段及功效,以下结合附图及较佳实施例,对依据本发明提出的为了无空隙的间隙填充制程的间隙壁外型塑造工程其具体实施方式、方法(制造方法、加工方法)、步骤、特征及其功效,详细说明如后。
有关本发明的前述及其他技术内容、特点及功效,在以下配合参考图式的较佳实施例的详细说明中将可清楚呈现。通过具体实施方式的说明,当可对本发明为达成预定目的所采取的技术手段及功效得一更加深入且具体的了解,然而所附图式仅是提供参考与说明之用,并非用来对本发明加以限制。
请参阅图2所示,为提供基板30。基板30具有相邻的区域100与区域200。在一实施例中,区域100用来形成金氧半导体元件,而区域200用来形成假栅极,通常指虚拟多晶硅。虚拟多晶硅可连接至另一个金氧半导体元件的栅极,也可不连接。或者,形成金氧半导体元件于区域100与200,并共用相同的源极或相同的漏极,其中每一个金氧半导体元件都必须与区域100上的金氧半导体元件一样,如图11与图12所示。在基板30上形成浅沟槽隔离(shallow trench isolation,STI)区202。接下来的图示中所讨论的实施例里,区域200为用来形成虚拟多晶硅,因此浅沟槽隔离区202形成于区域200内。区域100与200彼此相邻。基板30较佳为块状硅,但也可为其他常用材料或结构,例如硅化锗(SiGe)、绝缘层上覆硅(siliconon insulator,SOI)、绝缘层上覆硅化锗或上述相似材料或结构。栅极堆叠形成于区域100中,具有栅极介电层104与栅极106。同样地,虚拟栅极堆叠形成于区域200中,具有栅极介电层204与栅极206。如现有习知所知,栅极介电层104与204为介电材料,例如氧化硅、氮化硅、高介电是数材料或上述的相似物。栅极106与206为多晶硅或其他常用导电材料,如金属、金属氮化物、金属硅化物或上述的相似物。硬质掩膜层108与208可选择性地形成于栅极堆叠顶端,其中硬质掩膜层108与208为氮化硅。
请参阅图3所示,为形成密封层110与210。在一实施例中,密封层110与210为氮化硅。密封层110与210的厚度T2较佳为约小于40埃。然而,在所有叙述中提及的尺寸仅为举例,如为使用不同的形成技术,则可改变为其他尺寸。地毯式沉积介电层与图案化此介电层以形成密封层110与210,图案化介电层的方法如干式蚀刻法。当厚度够小时,密封层110与210顶端不会具有实质上的水平面。
同样如图3所示,密封层110与210形成之后,以植入法形成轻掺杂源极/漏极(lightly-doped drain/source,LDD)区112。可在区域100中植入N型杂质或P型杂质,植入的杂质类型取决于欲形成的金氧半导体形式。也可以植入法形成凹槽区(未绘示),其中凹槽区具有相反的导电形式,如同轻掺杂源极/漏极区112。
图4是说明栅极间隙壁114与214的图案化步骤。较佳为,形成介电层后以蚀刻步骤形成栅极间隙壁114与214。可用干式蚀刻法蚀刻介电层形成栅极间隙壁114与214。在一实施例中,栅极间隙壁114与214的厚度T3约为340埃。因将在后续图示中详细讨论利用后栅极(gate-last)制程形成金氧半导体元件的栅极。所以,介电层(亦即栅极间隙壁114与214)是由单层氮化硅所构成的,纵使介电层可为两层或两层以上的复合层,且每一层由不同的材料形成。在另一实施例中,金氧半导体元件的栅极也可利用前栅极(gate-first)制程形成,因此介电层可为复合层,例如可为氧化硅衬底上具有氮化硅层。
图5是说明源极/漏极区120的形成。在较佳实施例中,利用植入杂质至半导体基板中形成源极/漏极区120,因此源极/漏极区120的内侧边缘实质上与栅极间隙壁114的外侧边缘对齐。源极/漏极区120的形成方法为现有习知技术,因此不在此重复其细节。此外,形成源极/漏极区120可包含沿着栅极间隙壁114的外侧边缘形成凹槽(未绘示),以及利用半导体应变层(stressors)填补凹槽,例如硅化锗或碳化硅,取决于金氧半导体元件的导电形式。
图5也说明金属硅化物区122的形成。如现有习知所知,金属硅化物层122可为在源极/漏极区120上进行自我对准金属硅化制程(salicideprocess)而形成。为了形成金属硅化物层122,地毯式沉积金属以形成薄金属层,金属如钴、镍、钛或上述的相似物。然后个别的晶圆进行退火以让沉积的金属层与底下暴露的硅之间反应形成金属硅化物层,形成如图5所示的结构。
接着,如图6所示,薄化栅极间隙壁114与214。在一实施例中,利用湿式蚀刻法薄化栅极间隙壁114与214。因此栅极间隙壁114与214的厚度从如图3所示的T3减少为如图6所示的T4。在一实施例中,厚度T4约小于厚度T3的90%。也就是说,厚度T4约比厚度T3小50埃。在薄化之后,栅极间隙壁114的外侧边缘与金属硅化物区122的内侧边缘间具有空隙。栅极间隙壁114与214的薄化有益于减少间隙44的长宽比。
如图7所示,介电层130形成于区域100与区域200之上。在较佳实施例中,介电层130为具有第一子层1301与第二子层1302的复合层。第一子层1301与第二子层1302较佳为具有不同蚀刻特性的材料,例如氧化硅、氮化硅、氮氧化硅及上述的相似物。第一子层1301与第二子层1302为利用一般所使用的技术形成,例如等离子体(即电浆,本文均称为等离子体)增强型化学气相沉积(plasma enhanced chemical vapor deposition,PECVD)、低压化学气相沉积(low-pressure chemical vapor deposition,LPCVD)、次常压化学气相沉积(sub-atmospheric chemical vapor deposition,SACVD)等等。在一实施例中,第一子层1301为氮化层以及第二子层1302为氧化层。介电层130较佳的厚度小于约150埃,且更佳的厚度为大约50埃至大约150埃。
请参阅图8所示,蚀刻介电层130以形成次要间隙壁132与232,蚀刻方法如干式蚀刻法。当介电层130具有第一子层1301与第二子层1302,每一个次要间隙壁132与232则具有第一部分1321/2321以及第二部分1322/2322位于第一部分1321/2321上。在一实施例中,第二部分1322/2322为氧化硅,第一部分1321/2321为氮化硅。次要间隙壁132与232的顶点136与236较佳为分别低于间隙壁114与214的顶端。为了具有理想的间隙填充效果,次要间隙壁132与232的高度H1更佳约为间隙壁114与214的高度H2的10%~20%。此外,顶点136与236也可分别低于栅极106与206的顶面。次要间隙壁132的外侧边缘分别与金属硅化物区122的内侧边缘间具有空隙,或是两者为相连在一起。亦或是,次要间隙壁132的外侧边缘分别位在金属硅化物区122上,如图8所示。
请参阅图9所示,形成接触蚀刻终止层(contact etch stop layer,CESL)40。根据形成的金氧半导体元件的形式,选用适当的材料与合适的制程形成接触蚀刻终止层40,以提供压缩应力或扩张应力给下方的金氧半导体元件的通道区。接触蚀刻终止层40的材料如氮化物、氮氧化物、氧化物、碳化硅、氮氧化硅或上述的任意组合。
图9也是说明层间介电层42的形成,其可为氧化物、含碳介电质、硼磷硅酸盐玻璃(boronphosphorous silicate glass,BPSG)、磷硅酸盐玻璃(phosphorous silicate glass,PSG)、旋涂玻璃(spin-on glass)、四乙氧基硅烷(tetraethylorthosilicate,TEOS)氧化物或上述的相似物。形成层间介电层42的方法可为高密度等离子体化学气相沉积(high-density plasma chemical vapor deposition,HDPCVD)、高纵深比填沟制程(high-aspect ratio process,HARP)或上述的相似制程。
由于次要间隙壁132与232的形成,因此在层间介电层42形成前,栅极间隙壁114与214间的间隙44的底部角落可局部被接触蚀刻终止层40填补。因此之后需被层间介电层42填补的间隙44比没有次要间隙壁132与232的间隙有较多的倾斜侧边(使得间隙44呈现V的形状)。因此,在层间介电层42中形成空隙的可能性降低。
图10是说明在利用后栅极制程形成金氧半导体元件的栅极后所造成的结构。形成如图10所示结构的简短制程讨论如下。第一,进行化学机械研磨(chemical mechanical polish,CMP)。化学机械研磨停止于栅极106与206的顶部表面。因此,接触蚀刻终止层40以及栅极间隙壁114与214的顶部表面和栅极106与206的顶部表面齐平。在化学机械研磨之后,暴露出栅极106与206的顶部表面。
接着,移除栅极106与栅极介电层104以形成开口(此空间的后形成特征150与152)。再接下来,地毯式形成栅极介电层于开口中,紧接着填补导电材料至开口中,栅极介电层较佳为高介电系数的介电材料。再次进行化学机械研磨以移除多出于层间介电层42的栅极介电层与导电材料。开口中剩下的栅极介电层与金属材料形成金氧半电晶体元件的栅极介电层150与栅极152。虽然未绘示,但栅极介电层204与栅极206也可利用后栅极制程取代或是继续保留。
请参阅图11所示,形成附加的层间介电层56,紧接着于层间介电层56中形成触孔栓塞58。触孔栓塞58电性连接至栅极152与金属硅化物区122。
图12是说明利用前栅极制程形成的金氧半导体元件栅极的结构。在此实施例中,选择性的形成硬质掩膜层108与208(请见图2),以及栅极间隙壁114与214可为氧化硅层。除了栅极106与栅极介电层104没有被栅极152与栅极介电层150取代,以及形成触孔58以电性连接至栅极106或栅极106上的金属硅化物之外,金氧半导体元件栅极形成的制程相似于图2至图11所示。
在上述图示中所讨论的实施例里,栅极堆叠的特征为在浅沟槽隔离区202上形成虚拟特征,包含栅极介电层204与栅极206。或者是,栅极堆叠可用来形成金氧半导体元件,并与形成于区域100上的金氧半导体共用相同的源极或相同的漏极。在此实施例中,区域100与200中的金氧半导体元件非常靠近,因此薄化栅极间隙壁114与214(请参阅图11与图12)以及形成次要间隙壁132与232可有益于以层间介电层42填充间隙。此领域中熟习此技艺者可了解应用前述图示所提供的技术完成相同结构的制程步骤。
在本发明的实施例中,栅极间隙壁114与214的薄化可缩小栅极间隙壁114与214间间隙44的高宽比。次要间隙壁132与232更使得间隙44的侧边倾斜。因此,在以层间介电层42填充间隙44时,降低了在间隙44中形成空隙的可能性。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (13)
1.一种半导体元件的形成方法,其特征在于该形成方法包含以下步骤:
提供一半导体基板;
形成一栅极堆叠于该半导体基板上;
形成一栅极间隙壁紧邻该栅极堆叠侧边;
形成一源极/漏极区紧邻该栅极堆叠;
形成一源极/漏极金属硅化物区于该源极/漏极区上;
薄化该栅极间隙壁;以及
在薄化该栅极间隙壁后,形成一次要栅极间隙壁于该栅极间隙壁的侧边,其中该次要栅极间隙壁的顶边低于该栅极间隙壁的顶边。
2.根据权利要求1所述的半导体元件的形成方法,其特征在于其更包含在该栅极堆叠侧边形成一密封层位于该栅极堆叠和该栅极间隙壁之间,其中该栅极间隙壁底边与该半导体基板的顶面接触。
3.根据权利要求1所述的半导体元件的形成方法,其特征在于其中所述的次要栅极间隙壁的一外侧边缘直接位于该源极/漏极金属硅化物区之上。
4.根据权利要求1所述的半导体元件的形成方法,其特征在于其更包含:
形成一接触蚀刻终止层于该栅极堆叠的上;
进行一化学机械研磨以移除位于该栅极堆叠上的该接触蚀刻终止层的一部分;
移除该栅极堆叠以形成一开口;以及
在该开口中形成一栅极介电层与一栅极。
5.根据权利要求1所述的半导体元件的形成方法,其特征在于其中所述的栅极间隙壁为包含氮化硅的一单层间隙壁,以及该次要栅极间隙壁包含一氮化硅层与位于该氮化硅层上的一氧化层。
6.一种半导体元件的形成方法,其特征在于该形成方法包含以下步骤:
提供一半导体基板;
形成一栅极堆叠于该半导体基板上;
形成一密封层于该栅极堆叠的侧边;
形成一轻掺杂源极/漏极区于该半导体基板内;
形成一栅极间隙壁于该密封层的侧边;
形成一源极/漏极区,具有一内侧边缘与该栅极间隙壁的一外侧边缘对齐;
形成一源极/漏极金属硅化物区于该源极/漏极区上;
在形成该源极/漏极区与该源极/漏极金属硅化物区后,薄化该栅极间隙壁;以及
在形成该源极/漏极金属硅化物区后,形成一次要栅极间隙壁于该栅极间隙壁的侧边,其中该次要栅极间隙壁的顶边较低于该栅极间隙壁的顶边。
7.根据权利要求6所述的半导体元件的形成方法,其特征在于其更包含:
形成一接触蚀刻终止层于该栅极堆叠、该次要栅极间隙壁与该源极/漏极金属硅化物区之上;
形成一层间介电层于该接触蚀刻终止层之上;
进行一化学机械研磨以移除该栅极堆叠上的部分的该接触蚀刻终止层与部分的该层间介电层;
移除该栅极堆叠以形成一开口;以及
在该开口中形成一栅极介电层与一栅极。
8.根据权利要求7所述的半导体元件的形成方法,其特征在于其更包含:
在该开口中形成该栅极介电层与该栅极后,形成一附加的层间介电层于该层间介电层之上;以及
形成一触孔栓塞于该层间介电层与该附加的层间介电层中,其中该触孔栓塞电性连接至该栅极。
9.根据权利要求6所述的半导体元件的形成方法,其特征在于其中使用一湿式蚀刻法薄化该栅极间隙壁。
10.根据权利要求6所述的半导体元件的形成方法,其特征在于其中形成该次要栅极间隙壁的步骤包含:
地毯式形成一次要栅极间隙壁层;以及
干式蚀刻该次要栅极间隙壁层。
11.一种半导体元件的形成方法,其特征在于该形成方法包含以下步骤:
提供一半导体基板;
形成一绝缘区,其至少一部分于该半导体基板中;
形成一第一栅极堆叠与一第二栅极堆叠于该半导体基板上,其中该第一栅极堆叠与该第二栅极堆叠彼此相邻,且该第二栅极堆叠位于该绝缘区上;
形成一轻掺杂源极/漏极区紧邻该第一栅极堆叠;
形成一第一栅极间隙壁与一第二栅极间隙壁分别紧邻该第一栅极堆叠与该第二栅极堆叠的侧边;
形成一源极/漏极区,具有一内侧边缘与该第一栅极间隙壁的一外侧边缘重合;
形成一源极/漏极金属硅化物区于该源极/漏极区上;
在形成该源极/漏极区与该源极/漏极金属硅化物区后,薄化该第一栅极间隙壁与该第二栅极间隙壁;
在薄化该第一栅极间隙壁与该第二栅极间隙壁后,分别形成一第一次要栅极间隙壁与一第二次要栅极间隙壁于该第一栅极间隙壁与该第二栅极间隙壁的侧边;
形成一接触蚀刻终止层于该第一栅极堆叠、该第二栅极堆叠与该源极/漏极金属硅化物区之上;以及
填充一介电材料至该第一栅极间隙壁与该第二栅极间隙壁间的间隙,其中该介电材料位于该接触蚀刻终止层之上。
12.根据权利要求11所述的半导体元件的形成方法,其特征在于其中所述的第一次要栅极间隙壁与该第二次要栅极间隙壁的顶端分别较低于该第一栅极间隙壁与该第二栅极间隙壁的顶端。
13.根据权利要求11所述的半导体元件的形成方法,其特征在于其中所述的第一次要栅极间隙壁的外侧边缘直接位于该源极/漏极金属硅化物区上。
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TW408354B (en) * | 1999-03-02 | 2000-10-11 | United Microelectronics Corp | Structure of field effect transistor and its manufacture method |
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CN101170066A (zh) * | 2006-10-24 | 2008-04-30 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
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CN101635277A (zh) | 2010-01-27 |
TW201005834A (en) | 2010-02-01 |
US20120025329A1 (en) | 2012-02-02 |
US8461654B2 (en) | 2013-06-11 |
US20100022061A1 (en) | 2010-01-28 |
TWI382475B (zh) | 2013-01-11 |
US8048752B2 (en) | 2011-11-01 |
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