CN101326634A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN101326634A
CN101326634A CNA2005800522392A CN200580052239A CN101326634A CN 101326634 A CN101326634 A CN 101326634A CN A2005800522392 A CNA2005800522392 A CN A2005800522392A CN 200580052239 A CN200580052239 A CN 200580052239A CN 101326634 A CN101326634 A CN 101326634A
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Prior art keywords
film
semiconductor device
pad electrode
wiring
layer
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CNA2005800522392A
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CN101326634B (zh
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王文生
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Fujitsu Semiconductor Memory Solution Ltd
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Fujitsu Ltd
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Abstract

提供一种具有增加了探针接触强度的焊盘的半导体器件。半导体器件具有：半导体衬底；半导体元件，其形成在半导体衬底上；绝缘膜，其覆盖半导体元件，并且形成在半导体衬底的上方；多层布线结构，其形成在绝缘膜中；焊盘电极结构，其与多层布线结构连接，并形成在绝缘膜上，而且具有导电紧贴膜、导电焊盘电极以及导电性氢阻挡膜，其中，该导电焊盘电极形成在导电紧贴膜的上方，该导电性氢阻挡膜形成在导电焊盘电极的上方。

Description

半导体器件
技术领域
本发明涉及一种半导体器件，尤其涉及一种具有用于与外部电路连接及检查的焊盘的半导体器件。
背景技术
半导体集成电路器件在与最上布线层相同层或者其上具有抵接用于进行检查的探针或者接合用于连接外部电路的引线的焊盘。焊盘相比较于布线的其它图案具有较大的尺寸，并且焊盘上表面露出，从而能够抵接探针或者接合连接引线。进行多次检查，直到完成半导体集成电路器件为止，对最终认定为优良产品的器件进行封装。
在检查中，若将探针触到焊盘，则在焊盘上有时发生龟裂。即使发生龟裂，也能够在焊盘上接合引线，并且能够实现成品化。但是，进行了引线接合之后，焊盘表面也处于露出的状态，因此水分、氢容易从龟裂侵入。若侵入的水分、氢到达布线或者氧化物，则发生化学反应，给半导体器件的性能带来影响。
近年来，推进着对铁电存储器(FeRAM：Ferroelectric Random AccessMemory)的开发，该铁电存储器使用铁电电容器，并利用铁电体的极化颠倒记忆信息。铁电存储器是一种即使切断电源也不会丢失所记忆的信息的非易失性存储器，并且可期待实现高集成度、高速驱动、高持久性以及低耗电。
铁电存储器利用铁电体的磁滞特性存储信息。将铁电膜作为电容器电介质膜的夹在一对电极之间的铁电电容器根据电极之间外加的电压产生极化，即使去掉外加电压极化也不变化。若颠倒外加电压的极性，则极化的极性也颠倒。若检测出该极化，就能够读出信息。主要使用剩余极化值大的例如10μC/cm2～30μC/cm2左右的PZT(Pb(Zr1-x Tix)O3)、SBT(SrBi2Ta2O9)等钙钛矿结晶结构的氧化物铁电体作为铁电膜的材料。为了形成具有良好特性的氧化物铁电膜，需在氧化环境中进行成膜或者进行热处理，并且下部电极(根据需要上部电极也)多由难以被氧化的贵金属，或者即便被氧化也具有导电能力的贵金属或贵金属氧化物来形成。
制作铁电电容器之前，晶体管已形成在硅衬底。在形成了与晶体管连接的W等导电插塞之后，形成铁电电容器的情况下，需使成膜铁电膜时的氧化环境不给下部结构带来恶劣影响。
使用氧化硅来形成半导体集成电路器件的层间绝缘膜的情况多。氧化硅对水分的亲和力大。若水分从外部侵入，则水分能够通过层间绝缘膜到达至布线、电容器、晶体管等。若水分到达电容器尤其是铁电电容器，则电介质膜特别是铁电膜的特性发生劣化。若由侵入的水分产生的氢导致铁电膜被还原，发生氧缺陷，则结晶性降低。发生剩余极化值以及介电常数降低等特性劣化现象。长时间使用也会导致发生同样的现象。若氢侵入，则比水分更加直接地引起特性劣化。在形成硅膜或者氧化硅膜之际，用作硅源的硅烷是氢化硅，若将其分解则产生氢。这样的氢也是导致铁电膜劣化的原因之一。
可以认为在已制作的半导体集成电路器件中，最易受到外部侵入的水分、氢的影响的区域是焊盘及其周边部。例如，覆盖包含焊盘的最上布线，形成氧化硅膜等层间绝缘膜、氮化硅膜、聚酰亚胺膜，但是为了实现与焊盘的电接触，除去位于焊盘上的聚酰亚胺膜、氮化硅膜及氧化硅膜。虽然氮化硅膜对水分、氢具有阻挡能力，但是在焊盘上将其除去，因此水分、氢能够直接接触焊盘电极。
JP特开2003-174146号公报(申请人：富士通)提出了如下方案，即用2种氧化贵金属膜的层叠层来形成上部电极。为了使形成铁电膜时的氧化环境不带来恶劣影响，使用如氮化硅膜、氮氧化硅膜等具有氧阻挡能力的绝缘阻挡膜来覆盖形成在半导体衬底的晶体管。为了使在还原环境中进行的热处理不导致铁电电容器的特性发生劣化，使用氧化铝等具有氢阻挡能力的绝缘阻挡膜来覆盖铁电电容器。
JP特开2005-39299号公报(申请人：松下电气产业)提出了如下的方案，铁电膜覆盖形成在层间绝缘膜上的下部电极，将在其上形成了上部电极的铁电电容器的上部电极覆盖，进而在层间绝缘膜上形成具有突出的突出部分的导电性氢阻挡膜。在形成了覆盖铁电电容器的上层层间绝缘膜之后，形成到达导电性氢阻挡膜突出部分的通孔，并在通孔内形成导电插塞。示教了作为导电性氢阻挡膜优选地使用Ti膜、Ta膜、TiON膜、TiN膜、TaN膜、TiAlN膜、TiAlON膜或者包含它们的合金膜。
JP特开2003-86589号公报(申请人：富士通)提出了一种焊盘结构，焊盘电极成为在Al合金膜的上下配置了TiN阻挡金属膜的结构，上侧的TiN阻挡金属膜除去中央部，形成露出Al合金膜的接触部。根据这种结构，示出了TiN阻挡金属膜对水分、氢具有阻挡能力。
发明内容
发明所要解决的问题
本发明的目的在于，提供一种即使进行检查也能够保持耐水分、氢的能力的半导体器件。
本发明的另一目的在于，提供一种具有增强了探针接触强度的焊盘的半导体器件。
用于解决问题的方法
根据本发明的第一技术方案，提供了一种半导体器件，其特征在于，具有：半导体衬底；半导体元件，其形成在所述半导体衬底上；绝缘膜，其覆盖所述半导体元件，并且形成在所述半导体衬底的上方；多层布线结构，其形成在所述绝缘膜中；焊盘电极结构，其与所述多层布线结构连接，并形成在所述绝缘膜上，而且具有导电紧贴膜、导电焊盘电极以及导电性氢阻挡膜，其中，所述导电焊盘电极形成在所述导电紧贴膜的上方，所述导电性氢阻挡膜形成在所述导电焊盘电极的上方。
发明效果
由于增强了焊盘电极结构的硬度，因此即使探针接触也难以发生龟裂。
由于焊盘电极结构很难产生龟裂，因此氢、水分难于侵入。
附图说明
图1A-1L是表示第一实施例的半导体器件的制造方法主要工序的半导体器衬底剖视图。
图2是表示各种导电材料硬度的表。
图3是表示第一实施例半导体器件的成品率测定检查时的状态的剖视图。
图4A、4B是第一实施例的变形例的剖视图。
图5A-5E是表示第二实施例的半导体器件的制造方法主要工序的半导体衬底剖视图。
图6A-6F是表示第三实施例的半导体器件的制造方法主要工序的半导体衬底剖视图。
图7是表示其它变形例的剖视图。
图8A-8D是表示另外的变形例的剖视图。
附图标记的说明：
11半导体衬底(硅晶片)
STI浅沟槽隔离
13P阱
14栅绝缘膜
15栅电极
16盖膜(氮化硅膜)
17LDD区域
SW侧壁隔离层
S/D源极/漏极区域
18层间绝缘膜(IL)
18a保护膜
18b氧化硅膜
18c氮化硅膜
18dTEOS氧化硅膜
21Ti紧贴膜
22Pt膜
BEL下部电极层
23电介质膜
FER铁电膜
24IrO2膜
TEL上部电极层
26层间绝缘膜
VH通孔
T晶体管
C电容器
28胶膜
29W膜
PL插塞
30布线层
30aTi膜(阻挡膜)
30bTiN膜(阻挡膜)
30cAl-Cu合金膜
30dTi膜(阻挡膜)
30eTiN膜(阻挡膜)
BARC底面反射防止膜
RP抗蚀图案
31层间绝缘膜
31a绝缘阻挡膜(氧化铝膜)
31bTEOS氧化硅膜
32插塞(PL)
34布线层
35层间绝缘膜(IL)
36插塞(PL)
41导电紧贴膜
41aTi膜
41bTiAlN膜
42布线膜
43导电性氢阻挡(TiAlN)膜
44硬掩模
45层间绝缘(TEOS氧化硅)膜
46上部保护(氮化硅)膜
47聚酰亚胺膜(PI)
51导电紧贴膜
52主焊盘布线膜(高硬度布线膜)
53导电性氢阻挡膜
54第五层间绝缘膜
55导电紧贴膜
56高硬度导电膜
57导电性氢阻挡膜
CP导电保护膜
58绝缘膜
59上部保护膜
60、61、62、63绝缘阻挡膜
具体实施方式
参照图1A-1L来说明第一实施例的半导体器件的制造方法。
如图1A所示，在半导体衬底11上形成浅沟槽隔离STI来作为划定有源区域的元件分离区域，该半导体衬底11为N型或者P型硅晶片。例如，通过氮化硅膜等的CMP阻止膜，对半导体衬底11蚀刻300nm左右深度的浅沟槽，并且通过根据需要的氧化硅膜、氮化硅膜等衬垫(liner)，通过高密度等离子体(HDP)化学气相沉积(CVD)法沉积无掺杂硅玻璃(USG：Un-dopedSilicate Glass)膜，并通过利用了CMP阻止膜的化学机械研磨(CMP)法除去沉积膜的无需部分，并通过蚀刻工艺除去CMP阻止膜。在n隧道晶体管区域的有源区域，以离子注入剂量3×1013cm-2(下面，标记成3E13)、加速能量300KeV来离子注入p型杂质例如B，从而形成p阱13。在p隧道晶体管区域离子注入n型杂质，从而形成n阱。下面，虽然对n隧道晶体管区域举例进行说明，但是在p隧道晶体管区域中进行将导电类型颠倒的处理。
对有源区域表面进行热氧化处理，形成由例如厚度为大致3nm的氧化硅膜构成的栅绝缘膜14。在将栅绝缘膜变薄的情况下，也可以形成氧化硅膜之后，导入氮。在栅绝缘膜14上，通过CVD法沉积由例如厚度为180nm左右的多晶硅膜构成的栅电极膜15。在栅电极膜15上，通过CVD法沉积由例如厚度为29nm左右的氮化硅膜构成的盖膜16。形成栅电极形状的抗蚀图案，并对盖膜16、栅电极膜15以及栅绝缘膜14进行蚀刻，从而形成绝缘栅电极结构。将盖膜16作为掩模，通过以离子注入剂量为5E14、加速能量为10KeV的条件离子注入n型杂质例如As，从而形成LDD(lightly doped drain：轻掺杂漏极)(或者延伸区)区域17。
虽然示出了并排形成2个晶体管栅电极的结构，但是这些晶体管将中间源极/漏极区域(下面，按照所需设为源极区域)与共同位线连接，在两侧的源极/漏极区域(下面，按照所需设为漏极区域)连接存储电容器，使用这些晶体管。因为是左右对称的结构，所以电容器仅仅示出了右侧的结构。
如图1B所示，以覆盖栅电极结构的方式，在半导体衬底的整个面上通过CVD法沉积例如氧化硅膜，通过回蚀工艺仅在栅电极结构侧面上残留侧壁隔离层SW。经由盖层16、侧壁隔离层SW，以离子注入剂量为5E14、加速能量为13KeV的条件，将n型杂质例如P分四次离子注入到有源区域，形成与LDD区域17重叠且比LDD区域浓度高的源极/漏极区域S/D。
沉积如图1C所示绝缘层叠层，形成第一层间绝缘膜18。首先，通过CVD法沉积膜厚为20nm左右的氧化硅膜18a，通过等离子体增强(PE)CVD法在其上沉积膜厚为20nm左右的氧化硅膜18b、膜厚为80nm左右的氮化硅膜18c、将膜厚为1000nm左右的TEOS(正硅酸乙酯)作为原料的氧化硅膜18d。通过以热CVD法形成最下层氧化硅膜18a，从而能够保护有源区域不受等离子体的影响。氮化硅膜18c作为阻挡水分、氢侵入的阻挡膜发挥作用。其后，通过CMP法对TEOS氧化硅膜18d进行研磨，从而使其平坦，进而使整体厚度为700nm左右。
如图1D所示，在进行过平坦化处理的第一层间绝缘膜18上形成铁电电容器。例如，通过溅射法沉积由膜厚为20nm左右的Ti膜形成的导电紧贴膜21，在其上通过溅射法沉积由厚度为150nm左右的Pt膜形成的主下部电极膜22。如此地形成了下部电极层叠层。此外，主下部电极膜不仅限于Pt膜。优选地，使用选自由Pt、Ir、Ru、Rh、Re、Os、Pd、它们的氧化物、SrRuO3组成的组中的至少1种材料的膜，或者这些膜的层叠层。
在下部电极层上，通过RF(射频)溅射法沉积膜厚为200nm左右的、例如由PZT构成的铁电膜23。沉积铁电膜之后，进行快速热退火(RTA)处理，从而使铁电膜23结晶。其后，在铁电膜23上，通过反应溅射法沉积例如由厚度为200nm左右的IrO2膜形成的上部电极层24。此外，铁电膜不仅限于PZT。能够使用由一般式ABO3来示出的氧化物铁电膜。优选使用掺杂了微量的PZT、La、Sr、Ca等添加物的PZT、BLT(Bi4-xLaxTiO3)、SBT、Bi类层状化合物的铁电体。上部电极层也不仅限于IrO2。优选地，使用选自由Pt、Ir、Ru、Rh、Re、Os、Pd、它们的氧化物、SrRuO3组成的组中的至少1种材料的膜，或者这些膜的层叠层。
在形成了铁电电容器之后，形成第二层间绝缘膜26。例如，通过PE-CVD法沉积膜厚为1400nm左右的TEOS氧化硅膜，并通过CMP法进行研磨直到厚度为1000nm左右为止。为了进行了CMP之后对第二层间绝缘膜进行脱水处理，例如在N2O等离子体中实施退火处理。
如图1E所示，形成贯通层间绝缘膜的导电插塞PL。首先，通过采用抗蚀掩模的干蚀刻，贯通第二层间绝缘膜，形成到达铁电电容器下部电极BEL(21、22)、上部电极TEL(24)的通孔VHC。将通孔的直径设为例如0.5μm左右。上部电极TEL、下部电极BEL起到作为对氧化硅膜进行蚀刻时的蚀刻阻止膜的功能。即使上部电极TEL及下部电极BEL的高度不同，对于通孔的形成也不会发生问题。接下来，例如在氧环境中，以500℃进行60分钟的恢复铁电电容器结构所受到损伤的退火处理。
形成相对晶体管源极/漏极的通孔VHT。例如，通过使用抗蚀掩模的干蚀刻工艺，将源极/漏极区域的硅表面作为蚀刻阻止膜，对第二层间绝缘膜26及第一层间绝缘膜18进行蚀刻。将通孔VHT的直径设为例如0.3μm左右。
在形成了通孔VHC、VHT之后，为了除去有可能形成在硅表面上的氧化膜，而进行以氧化硅膜蚀刻换算为例如10nm左右的RF前处理，接着，通过溅射法沉积例如厚度为75nm左右的TiN基底胶膜28，以覆盖通孔的内表面。接着通过CVD法沉积W膜29，以填埋通孔。其后，将第二层间绝缘膜用作CMP阻止膜，通过CMP法除去第二层间绝缘膜上的W膜29、TiN膜28。如此地形成导电插塞PL。
如图1F所示，在形成有导电插塞的第二层间绝缘膜26上形成第一布线30。首先，通过溅射法等工艺，在衬底的整个面上沉积下部阻挡金属膜、布线膜以及上部阻挡金属膜。形成例如厚度为60nm左右的Ti膜30a以及厚度为30nm左右的TiN膜30b而作为下部阻挡金属膜。形成例如厚度为360nm左右的Al合金(例如Al-Cu)膜30c而作为布线膜。形成例如厚度为5nm左右的Ti膜30d以及厚度为70nm左右的TiN膜30e而作为上部阻挡金属膜。该布线结构与同一规格的逻辑电路相同，能够保证高可靠性。
如图1G所示，在第一布线膜结构上，形成作为底面反射防止膜的SiON膜或者类似抗蚀剂组成的有机反射防止膜BARC，并在其上形成抗蚀图案RP。将抗蚀图案RP作为蚀刻掩模，对底面反射防止膜BARC及布线膜30进行蚀刻，形成第一布线图案。其后，例如通过灰化处理除去抗蚀图案RP及底面反射防止膜BARC。此外，也能够通过使用Cu或者Cu合金的镶嵌布线来形成第一布线。
如图1H所示，以覆盖第一布线30的方式，形成具有氢阻挡能力的绝缘阻挡膜31a。绝缘阻挡膜31a用于抑制在其后的工序中铁电电容器所能受到的损伤，通过溅射法形成具有氢阻挡能力的金属氧化膜、例如厚度为20nm左右的氧化铝膜。接下来，在绝缘阻挡膜31a上形成厚度为700nm左右的氧化硅膜，进一步地，通过PE-CVD法形成TEOS氧化硅膜31b，并使其使整体的厚度为1100nm左右，通过CMP法对表面进行研磨，形成膜厚为750nm左右的氧化硅绝缘膜31b。此外，方便起见使绝缘阻挡膜31a和氧化硅绝缘膜31b合并而称作第三层间绝缘膜31。
如图1I所示，形成贯通第三层间绝缘膜31，并引出第一布线的导电插塞32。首先，形成具有与第一布线的连接部相对应的开口的抗蚀图案，并形成贯通第三层间绝缘膜31、到达第一布线30且直径为0.25μm左右的通孔。该导电插塞的制造工序与图1E所示导电插塞PL的制造工序相同。
另外，在形成有导电插塞32的第三层间绝缘膜31上，形成第二布线34。第二布线的制造工序与参照图1F、1G所说明的第一布线的制造工序相同。以覆盖第二布线34的方式形成第四层间绝缘膜35。能够将第四层间绝缘膜35形成为与第三层间绝缘膜31相同。但是，也可以省略绝缘阻挡膜。按照与导电插塞32相同的工序，形成贯通第四层间绝缘膜35并到达第二布线34的导电插塞36。能够任意地选择多层布线的层数。
在形成有导电插塞35的第四层间绝缘膜35的整个面上，形成导电紧贴膜41、高硬度布线膜42以及导电性氢阻挡膜43。例如，通过溅射法形成厚度为30nm左右的Ti膜41a及厚度为50nm左右的TiAlN膜41b，从而形成导电紧贴膜41。导电紧贴膜是用于提高与其下方的层间绝缘膜及其上方的布线膜之间的紧贴性的膜，并且不仅限于TiAlN/Ti层叠层。使用选自由Ti膜、TiN膜、TiAlN膜、Ir膜、IrOx膜、Pt膜、Ru膜、RuOx膜、Os膜、Ta膜组成的组中的至少1种材料的单层膜，或者多层膜来形成导电紧贴膜。
例如形成厚度为200nm的Ir膜而作为高硬度布线膜42。Ir比Al-Cu电阻率低，而且能够以100-200nm左右的厚度形成与厚度为350nm左右的Al-Cu相同导电性的布线。虽因成膜方法而异，但即使将Ir改为IrO也能够得到大致相同的导电性。高硬度布线膜是具有即使将探针触到焊盘也很难发生龟裂的硬度的膜，而且不仅限于Ir膜、IrO膜。能够以包括选自由硬度高的贵金属(Ir、Ru、Rh、Re、Os)、它们的合金以及它们的氧化物组成的组中的至少一种材料的单层膜，或者多层膜来形成高硬度布线膜。
例如通过溅射法形成100nm厚度的TiAlN膜而作为导电性氢阻挡膜43。与TiN相比时TiAlN难于被氧化，对氧具有阻挡特性，从而难于被剥离，比TiN硬度高，对于氢具有与TiN相同程度的阻挡特性。替换现有的厚度为50nm左右的TiN膜，能够使用厚度为20-100nm左右的TiAlN膜。能够形成提高了阻挡特性的高硬度的导电膜。若不足20nm则难于得到充分的阻挡特性，若厚度超过100nm则成本增加。导电性氢阻挡膜为具有导电性及氢阻挡特性的膜，并不仅限于TiAlN。能够由Ti、TiAl、Ta、TaAl中任一种材料的氮化物、氮氧化物或者它们的混合物当中的任意一种层，或这些层的层叠层来形成导电性氢阻挡膜。
例如Ir、IrOx、Ru、RuOx、Os既能够作为导电紧贴膜也能够作为高硬度布线膜来使用。在这种情况下，也可以成为使导电紧贴膜和高硬度布线膜一体化的结构。焊盘电极结构的整体的强度和阻挡特性由各构成层来决定。例如，在由相同材料形成导电紧贴膜和导电阻挡膜的情况下，能够作为总的厚度的膜来考虑阻挡特性及强度等。如此地，能够将强度、阻挡特性作为层叠结构整体的性能来考虑。
在导电性氢阻挡膜43上，在焊盘电极结构的蚀刻工序中，沉积也作为硬掩模发挥作用的例如厚度为800nm的氧化硅膜44。在氧化硅膜44上形成抗蚀图案RP，将抗蚀图案作为蚀刻掩模进而对氧化硅膜44进行蚀刻，从而形成硬掩模。使用该硬掩模，并使用Ar+Cl2作为蚀刻气体，对导电性氢阻挡膜43、高硬度布线膜42以及导电紧贴膜41进行蚀刻。此外，也可以不使用硬掩模，而将厚的抗蚀图案作为蚀刻掩模，进行蚀刻。其后，除去抗蚀图案RP、氧化硅膜44。如此地形成包括焊盘电极结构的第三布线。
如图1J所示，以覆盖第三布线的方式形成第五层间绝缘膜以及上部保护膜。例如，通过CVD法沉积TEOS氧化硅膜45a，以便添埋第三布线，并进行将第三布线作为阻止膜的CMP法，对表面进行平坦化处理。在此阶段，由于第三布线露出，所以进一步地通过CVD法沉积绝缘膜、例如TEOS氧化硅膜45b，从而在第三布线上形成具有100nm厚度的第五层间绝缘膜45。在第五层间绝缘膜上，沉积具有对水分、氢的阻挡能力的上部保护膜46例如350nm厚度的氮化硅膜。在上部保护膜46上，形成用于在焊盘电极结构的接触部开口的抗蚀图案RP。抗蚀图案RP的开口在俯视观察时为位于电极内的形状，焊盘电极侧面上的绝缘膜没有被蚀刻。将抗蚀图案RP作为蚀刻掩模，对上部保护膜46、第五层间绝缘膜45进行干蚀刻。其后，通过灰化处理等来除去抗蚀图案RP。
如图1K所示，用第五层间绝缘膜、上部保护膜覆盖焊盘电极的周边部分，从而形成露出焊盘电极主要部分的焊盘电极结构。
如图1L所示，涂敷例如厚度为3300nm左右的聚酰亚胺膜47，并图案成形为包围焊盘电极用开口的形状。在使用感光聚酰亚胺的情况下，能够通过曝光、显影来图案成形。这样地，能够制作出具有铁电电容器的半导体器件。
在本实施方式中，导电紧贴膜不但能够增强层间绝缘膜与最上布线膜之间的紧贴性之外，而且对水分、氢具有出色的阻挡特性，能够有效地降低电容器的劣化。
图2是表示各种材料硬度的表。用于高硬度布线膜42的Ir、Ru、Rh、Re、Os与例如常用作焊盘布线材料的Al、Al-Cu相比具有格外高的硬度。能够用作导电性氢阻挡膜的TiN、TiAlN、TaN也具有比Al和Cu高的硬度。虽然没有包括在表内，但是TaAlN也具有高的硬度。用作导电紧贴膜的Ti、TiN、TiAlN、Ir、Ru、Os、Ta也具有高的硬度。
图3示出了第一实施例的半导体器件的成品率测定检查时的情况。将第一、第二、第三、第四、第五层间绝缘膜标记为IL1、IL2、IL3、IL4、IL5。将绝缘阻挡膜标记为BL，上部保护膜标记为PS。将除去焊盘布线之外的金属布线层标记为M1、M2。将导电插塞标记为PL。将聚酰亚胺膜标记为PI。通过层叠导电紧贴膜AM、主焊盘布线膜MM、导电性氢阻挡膜MB构成焊盘电极结构PD。针触到焊盘，从上方施加应力。在此状态下，以高温、高湿状态进行加速试验。
由于能够提高焊盘电极结构的硬度，因此即使检查时将针触到焊盘也难以发生龟裂。而且，还能够获得对水分、氢的阻挡能力，因此能够有效防止水分、氢向内部侵入，从而保持铁电电容器的特性变得容易。此外，若由导电紧贴膜、导电性氢阻挡膜获得充分的硬度以及对水分、氢的阻挡能力，则也能够由除了贵金属及它们的氧化物以外的材料来形成焊盘布线膜。
图4A示出了第一实施例的变形例。以作为最上布线层的金属布线膜M2形成下层焊盘，仅在焊盘电极的部位，中间隔着多个导电插塞PL在其上方形成由导电紧贴膜AM、主焊盘电极膜MM、导电性氢阻挡膜MB的层叠层构成的焊盘电极结构。除了层叠层结构以外的结构与第一实施例的结构相同。
图4B示出了其它变形例。由与第一实施例相同的导电紧贴膜51、Al-Cu主焊盘布线膜52以及与第一实施例相同的导电性氢阻挡膜53形成焊盘电极结构。虽然主焊盘布线膜52由与现有技术相同的Al合金形成，但是由于以导电性氢阻挡膜53(以及导电紧贴膜51)提高了硬度，因此难以产生龟裂。而且，提高了对于来自外部的水分、氢侵入的阻挡能力。
图5A-5E是表示第二实施例的半导体器件的制造方法主要工序的剖视图。图5A示出了已形成图4B所示的变形例的焊盘电极结构的状态。由导电紧贴膜51、Al-Cu主焊盘电极膜52以及导电性氢阻挡膜53的层叠层来形成焊盘电极结构PD。没有特别限定基底50，但是，例如为第一实施例的第四层间绝缘膜下方的半导体器件结构。
如图5B所示，用第五层间绝缘膜54覆盖焊盘电极结构，并对表面进行平坦化处理。在已平坦的第五层间绝缘膜54上，层叠导电紧贴膜55、高硬度导电膜56以及导电性氢阻挡膜57来形成导电保护层CP。导电紧贴膜是提高其下方的层间绝缘膜与其上方的导电膜之间的紧贴性的膜，而且以包括选自由Ti膜、TiN膜、TiAlN膜、Ir膜、IrOx膜、Ru膜、RuOx膜、Os膜、Ta膜组成的组中的至少一种材料、而且厚度为20-100nm的单层膜或者多层膜形成。
高硬度导电膜是既具有高硬度又对水分、氢具有阻挡能力的膜，而且以包括选自由硬度高的贵金属(Ir、Ru、Rh、Re、Os)、它们的合金以及它们的氧化物组成的组中的至少一种材料且厚度为20-200nm的单层膜，或者多层膜来形成该高硬度导电膜。
导电性氢阻挡膜是具有导电性和氢阻挡特性的膜，而且能够用Ti、TiAl、Ta、TaAl中任一种材料的氮化物、氮氧化物或者它们的混合物当中的任意一种形成且厚度为20-100nm的单层或者它们的层叠层来形成导电性氢阻挡膜。
例如Ir、IrOx、Ru、RuOx、Os既能用作导电紧贴膜又能用作高硬度导电膜。在此情况下，也可以作为使导电紧贴膜和高硬度导电膜一体化的结构。虽然使用导电材料来形成上述结构，但是导电性不是特别需要的。代替高硬度导电膜及导电性氢阻挡膜，也可以使用TiO及AlO。
为了除去焊盘电极结构上方的导电保护层CP，在导电保护层CP上形成抗蚀图案RP，并对导电保护层CP进行蚀刻。
如图5C所示，在包含焊盘电极结构PD的区域，除去导电保护层CP，然后通过灰化等处理除去抗蚀图案RP。导电保护层CP的内边从焊盘电极结构PD的外边远离规定距离。焊盘电极结构处于被第五层间绝缘膜54覆盖着的状态。
如图5D所示，以覆盖进行过图案成形的导电保护层CP的方式沉积绝缘膜58、上部保护膜59。使用例如厚度为100nm左右的氧化硅膜来形成绝缘膜58。使用例如厚度为350nm左右的氮化硅膜来形成上部保护膜59。以反映导电保护膜的阶梯差的方式，在绝缘膜58、上部保护膜59在焊盘电极结构上方形成凹部。在上部保护膜59上形成抗蚀图案RP。抗蚀图案RP在位于凹部内的区域具有开口。位于阶梯部的上部保护膜59被抗蚀图案RP覆盖。将抗蚀图案RP作为蚀刻掩模对上部保护膜59、绝缘膜58进行干蚀刻。
如图5E所示，形成露出焊盘电极结构的主要部分的开口。通过灰化等来除去抗蚀图案RP。氮化硅的上部保护膜59以向阶梯侧面伸出的方式残留在阶梯部，因此对于水分、氢的阻挡能力提高。在上部保护膜59上形成聚酰亚胺膜PI。
由于焊盘以外区域的几乎整个面被导电保护层CP覆盖，因此能够获得如下性能的结构：在半导体芯片的几乎整个面上，抗应力特性以及对于外部的水分、氢的抗侵入特性都高。
图6A-6F是表示第三实施例半导体器件的制造方法主要工序的剖视图。第三实施例的结构是，在第二实施例的多层布线的中间高度处附近配置了对水分、氢具有阻挡能力的绝缘阻挡膜的结构。
如图6A所示，在基底结构50上，形成由导电紧贴膜、Al-Cu主焊盘电极膜以及氢阻挡膜的层叠层构成的焊盘电极结构PD，并用氧化硅等绝缘膜54a来覆盖，并将焊盘电极结构PD作为CMP阻止膜进行CMP处理，从而使其表面平坦。进一步地，对氧化硅膜进行干蚀刻，对绝缘膜54a进行回蚀，从而将绝缘膜54a的表面降低至焊盘电极结构PD的中间高度。
如图6B所示，通过溅射法，沉积对于水分、氢具有阻挡能力的绝缘阻挡膜60例如氧化铝膜、TiOx膜或者它们的层叠层到厚度为20nm左右。通过CVD法，在绝缘阻挡膜60上，沉积绝缘膜54b例如TEOS氧化硅膜，以填埋焊盘电极结构PD。进行将焊盘电极结构作为阻止膜的CMP处理，使其表面平坦。
如图6C所示，进一步地，通过CVD法，沉积绝缘膜54c例如TEOS氧化硅膜。然后，进行对应图5B-5E的工序。
图6D所示，在已进行过平坦化处理的绝缘膜54c上，层叠导电紧贴膜55、高硬度导电膜56以及导电性氢阻挡膜57，以形成导电保护层CP。
为了除去焊盘电极结构上方的导电保护层CP，在导电保护层CP上形成抗蚀图案RP，对导电保护层CP进行蚀刻。由于焊盘以外区域的几乎整个面也被导电保护层CP覆盖，因此能够获得具有如下性能的结构：在半导体芯片的几乎整个面上，抗应力特性以及对于外部的水分、氢的抗侵入特性都高。
如图6E所示，在内置焊盘电极结构PD的区域，除去导电保护层CP，并通过灰化(ashing)等除去抗蚀图案RP。焊盘电极结构处于被绝缘膜54c覆盖着的状态。
以覆盖进行过图案成形的导电保护层CP的方式沉积绝缘膜58、上部保护膜59。使用例如厚度为100nm左右的氧化硅膜来形成绝缘膜58。使用例如厚度为350nm左右的氮化硅膜来形成上部保护膜59。以反映导电保护膜的阶梯的方式，绝缘膜58、上部保护膜59在焊盘电极结构上方形成凹部。在上部保护膜59上形成抗蚀图案RP。抗蚀图案RP在位于凹部内的区域具有开口。位于阶梯部的上部保护膜59被抗蚀图案RP覆盖。将抗蚀图案RP作为蚀刻掩模对上部保护膜59、绝缘膜58进行干蚀刻。
如图6F所示，形成露出焊盘电极结构的主要部分的开口。通过灰化等来除去抗蚀图案RP。由于在阶梯部氮化硅的上部保护膜59以向阶梯侧面突出的方式残留，因此对于水分、氢的阻挡能力提高。在上部保护膜59上形成聚酰亚胺膜PI。
根据本实施例，在多层布线的中间高度形成了对水分、氢具有阻挡能力的绝缘阻挡膜。形成绝缘阻挡膜及其相交叉的布线图案共同覆盖衬底整个面的结构。更完全地防止水分、氢侵入到基底结构。此外，使绝缘阻挡膜也可以代替与布线图案交叉，而使其与导电插塞交叉。
图7示出了在第一实施例中引入与导电插塞相交叉的绝缘阻挡膜的变形例。铁电电容器的下部电极BEL、铁电膜FER、上部电极TEL、导电插塞PL1、PL2、PL3、层间绝缘膜IL2、IL3、IL4、IL5、金属布线M1、M2、焊盘电极结构PD、绝缘阻挡膜BL、上部保护膜PS、聚酰亚胺膜PI与第一实施例相同。在与导电插塞PL2交叉的高度以及与导电插塞PL3交叉的高度，形成了对水分、氢具有阻挡能力的绝缘阻挡膜61、62，该绝缘阻挡膜61、62由TiO、AlO、它们的混合物或者它们的层叠层形成。
图8A-8D表示其它变形例。在这些图中，IL(IL4、IL5)表示(第四、第五)层间绝缘膜，M2表示第二金属布线，PD表示与第一实施例相同的、由导电紧贴膜、焊盘主布线膜、导电性氢阻挡膜的层叠层构成的焊盘电极结构，PS表示由氮化硅构成的上部保护膜，PI表示聚酰亚胺膜，PL表示导电插塞。
在图8A中，形成第一实施例的焊盘电极结构PD同时地以同样的层叠结构形成了类似于第二实施例的导电保护膜CP，并由沟槽电性分离。不增加工序数目，就能够形成导电保护膜。
在图8B中，在与第二金属布线M2交叉的高度，形成有绝缘阻挡膜60。
图8C中，在与导电插塞PL交叉的高度，形成有绝缘阻挡膜62，其中，该导电插塞PL连接第二金属布线和焊盘电极结构。
在图8D中，在与图8A所示焊盘电极结构PD和导电保护膜CP的上表面相接触的高度，形成有绝缘阻挡膜63。在这种结构中，从上部侵入的水分、氢只要不透过绝缘阻挡膜63、焊盘电极结构PD或者导电保护膜CP中任意一个，就不能进入到下部结构。此外，在与焊盘电极、导电保护膜相交叉的高度配置绝缘阻挡膜，从而能够获得同样的效果。
虽然按照上述实施例说明了本发明，但是本发明不仅限于此。例如可进行各种的变更、改善以及组合，这对本领域技术人员来说是显而易见的。

Claims (20)

1.一种半导体器件，其特征在于，具有：
半导体衬底；
半导体元件，其形成在所述半导体衬底上；
绝缘膜，其覆盖所述半导体元件，并形成在所述半导体衬底的上方；
多层布线结构，其形成在所述绝缘膜中；
焊盘电极结构，其与所述多层布线结构连接，并形成在所述绝缘膜上，而且具有导电紧贴膜、导电焊盘电极以及导电性氢阻挡膜，其中，所述导电焊盘电极形成在所述导电紧贴膜的上方，所述导电性氢阻挡膜形成在所述导电焊盘电极的上方。
2.根据权利要求1所述的半导体器件，其特征在于，所述导电焊盘电极包括由如下材料形成的层，该材料是选自由Ir、Ru、Rh、Re、Os以及它们的氧化物组成的组中的至少一种材料。
3.根据权利要求1所述的半导体器件，其特征在于，所述导电焊盘电极包括由如下材料形成的层，该材料是选自由Al、Cu、W以及它们的合金组成的组中的至少一种材料。
4.根据权利要求1～3中任一项所述的半导体器件，其特征在于，
还具有电容器，该电容器形成在所述半导体衬底的上方，而且包括下部电极、氧化物电介质膜以及上部电极，
所述多层布线结构配置在所述电容器的上方。
5.根据权利要求3所述的半导体器件，其特征在于，所述氧化物电介质膜是由一般式ABO3来示出的铁电体的膜。
6.根据权利要求5所述的半导体器件，其特征在于，所述铁电体是在PZT、掺杂了微量的添加物的PZT、BLT、SBT、Bi类层状化合物中的任一种材料。
7.根据权利要求4～6中任一项所述的半导体器件，其特征在于，所述下部电极包括选自由Pt、Ir、Ru、Rh、Re、Os、Pd、它们的氧化物以及SrRuO3组成的组中的至少一种材料的膜。
8.根据权利要求4～7中任一项所述的半导体器件，其特征在于，所述上部电极包括选自由Pt、Ir、Ru、Rh、Re、Os、Pd、它们的氧化物以及SrRuO3组成的组中的至少一种材料的膜。
9.根据权利要求1～8中任一项所述的半导体器件，其特征在于，所述导电性氢阻挡膜包括，在Ti、TiAl、Ta、TaAl中的任一种材料的氮化物、氮氧化物或它们的混合物中的任一种材料的层，或者这些层的层叠层。
10.根据权利要求1～9中任一项所述的半导体器件，其特征在于，所述导电紧贴膜包括选自由Ti膜、TiN膜、TiAlN膜、Ir膜、IrOx膜、Pt膜、Ru膜、RuOx膜、Os膜、Ta膜组成的组中的至少一种膜。
11.根据权利要求2所述的半导体器件，其特征在于，所述导电紧贴膜与所述导电焊盘电极成为一体，而且是在Ir膜、IrOx膜、Ru膜、RuOx膜、Os膜中的任一种膜。
12.根据权利要求1～11中任一项所述的半导体器件，其特征在于，还具有导电保护膜，该导电保护膜与所述焊盘电极结构电绝缘，而且包围所述焊盘电极结构。
13.根据权利要求12所述的半导体器件，其特征在于，所述导电保护膜包括，在Ir、Ru、Rh、Re、Os、它们的氮化物、Ti、TiAl、Ta、TaAl中的任一种材料的氮化物、氮氧化物或者它们的混合物中的任一种材料的层，或者这些层的层叠层。
14.根据权利要求12所述的半导体器件，其特征在于，所述导电保护膜具有与所述焊盘电极结构相同的层结构。
15.根据权利要求12～14中任一项所述的半导体器件，其特征在于，所述导电保护膜覆盖除了所述焊盘电极结构的形成位置以外的所述半导体衬底上方的整个面。
16.根据权利要求1～15中任一项所述的半导体器件，其特征在于，还具有绝缘阻挡膜，该绝缘阻挡膜配置在所述绝缘膜中或者绝缘膜的上方，并包括由氧化铝和氧化钛中的至少一种材料形成的膜。
17.根据权利要求16所述的半导体器件，其特征在于，所述绝缘阻挡膜配置在与所述多层布线交叉的高度，并且与所述多层布线一起覆盖所述半导体衬底的整个面。
18.根据权利要求17所述的半导体器件，其特征在于，所述多层布线包括通孔导电体和布线图案，所述绝缘阻挡膜配置在与所述布线图案交叉的高度。
19.根据权利要求17所述的半导体器件，其特征在于，所述多层布线包括通孔导电体和布线图案，所述绝缘阻挡膜配置在与所述通孔导电体交叉的高度。
20.根据权利要求16所述的半导体器件，其特征在于，所述绝缘阻挡膜与所述焊盘电极结构接触。
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