CN101055761B - 半导体存储器件 - Google Patents
半导体存储器件 Download PDFInfo
- Publication number
- CN101055761B CN101055761B CN2007101068073A CN200710106807A CN101055761B CN 101055761 B CN101055761 B CN 101055761B CN 2007101068073 A CN2007101068073 A CN 2007101068073A CN 200710106807 A CN200710106807 A CN 200710106807A CN 101055761 B CN101055761 B CN 101055761B
- Authority
- CN
- China
- Prior art keywords
- signal
- refresh
- ref
- timing
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000001514 detection method Methods 0.000 description 60
- 230000004044 response Effects 0.000 description 42
- 238000010586 diagram Methods 0.000 description 29
- 238000012360 testing method Methods 0.000 description 28
- 230000000630 rising effect Effects 0.000 description 24
- 230000007423 decrease Effects 0.000 description 13
- 238000000034 method Methods 0.000 description 6
- 230000001186 cumulative effect Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000008929 regeneration Effects 0.000 description 1
- 238000011069 regeneration method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (3)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002231644A JP4188640B2 (ja) | 2002-08-08 | 2002-08-08 | 半導体記憶装置、半導体記憶装置の制御方法及び半導体記憶装置の試験方法 |
JP2002231644 | 2002-08-08 | ||
JP2002-231644 | 2002-08-08 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB031496598A Division CN100346422C (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件及其控制和测试方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101055761A CN101055761A (zh) | 2007-10-17 |
CN101055761B true CN101055761B (zh) | 2012-06-20 |
Family
ID=30437773
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101068069A Expired - Fee Related CN101051525B (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件 |
CN2007101068073A Expired - Fee Related CN101055761B (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件 |
CNB2007101068088A Expired - Fee Related CN100555447C (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件控制方法 |
CNB031496598A Expired - Fee Related CN100346422C (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件及其控制和测试方法 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007101068069A Expired - Fee Related CN101051525B (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件 |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2007101068088A Expired - Fee Related CN100555447C (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件控制方法 |
CNB031496598A Expired - Fee Related CN100346422C (zh) | 2002-08-08 | 2003-08-05 | 半导体存储器件及其控制和测试方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7287142B2 (zh) |
EP (1) | EP1388865B1 (zh) |
JP (1) | JP4188640B2 (zh) |
KR (1) | KR100919270B1 (zh) |
CN (4) | CN101051525B (zh) |
TW (1) | TWI223279B (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6356485B1 (en) * | 1999-02-13 | 2002-03-12 | Integrated Device Technology, Inc. | Merging write cycles by comparing at least a portion of the respective write cycle addresses |
JP3998539B2 (ja) * | 2002-08-28 | 2007-10-31 | 富士通株式会社 | 半導体記憶装置 |
US20050068829A1 (en) * | 2003-09-25 | 2005-03-31 | Infineon Technologies North America Corp. | Refresh rate adjustment |
US7257811B2 (en) | 2004-05-11 | 2007-08-14 | International Business Machines Corporation | System, method and program to migrate a virtual machine |
JP2006155841A (ja) * | 2004-12-01 | 2006-06-15 | Nec Electronics Corp | 半導体記憶装置及びリフレッシュ制御方法 |
CN105656472B (zh) * | 2015-12-30 | 2018-10-16 | 中国电力科学研究院 | 一种优先权判断电路 |
KR102350957B1 (ko) * | 2017-10-26 | 2022-01-14 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 메모리 시스템의 리프레시 제어 방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2265035A (en) * | 1992-03-12 | 1993-09-15 | Apple Computer | Method and apparatus for improved dram refresh operations |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5826394A (ja) * | 1981-08-06 | 1983-02-16 | Fujitsu Ltd | 競合回路 |
US5343047A (en) * | 1992-06-27 | 1994-08-30 | Tokyo Electron Limited | Ion implantation system |
JPH09251783A (ja) * | 1996-03-14 | 1997-09-22 | Hitachi Ltd | リフレッシュ制御方法、半導体記憶装置、データ処理装置 |
US5641969A (en) * | 1996-03-28 | 1997-06-24 | Applied Materials, Inc. | Ion implantation apparatus |
JP3204190B2 (ja) * | 1997-12-26 | 2001-09-04 | 日本電気株式会社 | 半導体記憶装置 |
JP3313641B2 (ja) * | 1998-02-27 | 2002-08-12 | エヌイーシーマイクロシステム株式会社 | 半導体記憶装置 |
US7002982B1 (en) * | 1998-07-08 | 2006-02-21 | Broadcom Corporation | Apparatus and method for storing data |
JP2001076500A (ja) * | 1999-06-28 | 2001-03-23 | Mitsubishi Electric Corp | 半導体記憶装置 |
CN1152421C (zh) * | 1999-07-14 | 2004-06-02 | 国际商业机器公司 | 测试电路的方法 |
JP2001167574A (ja) * | 1999-12-08 | 2001-06-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP3778417B2 (ja) * | 2000-02-29 | 2006-05-24 | 富士通株式会社 | 半導体記憶装置 |
JP4000242B2 (ja) * | 2000-08-31 | 2007-10-31 | 富士通株式会社 | 半導体記憶装置 |
JP3531602B2 (ja) * | 2000-11-08 | 2004-05-31 | セイコーエプソン株式会社 | 半導体メモリ装置内のワード線の活性化 |
KR100367690B1 (ko) * | 2000-12-04 | 2003-01-14 | (주)실리콘세븐 | 디램 셀을 이용한 비동기식 에스램 호환 메모리 장치 및그 구동 방법 |
JP4743999B2 (ja) * | 2001-05-28 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
-
2002
- 2002-08-08 JP JP2002231644A patent/JP4188640B2/ja not_active Expired - Fee Related
-
2003
- 2003-07-24 EP EP03016890.0A patent/EP1388865B1/en not_active Expired - Fee Related
- 2003-07-24 TW TW092120220A patent/TWI223279B/zh not_active IP Right Cessation
- 2003-08-05 CN CN2007101068069A patent/CN101051525B/zh not_active Expired - Fee Related
- 2003-08-05 CN CN2007101068073A patent/CN101055761B/zh not_active Expired - Fee Related
- 2003-08-05 KR KR1020030054009A patent/KR100919270B1/ko active IP Right Grant
- 2003-08-05 CN CNB2007101068088A patent/CN100555447C/zh not_active Expired - Fee Related
- 2003-08-05 CN CNB031496598A patent/CN100346422C/zh not_active Expired - Fee Related
- 2003-08-06 US US10/634,758 patent/US7287142B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2265035A (en) * | 1992-03-12 | 1993-09-15 | Apple Computer | Method and apparatus for improved dram refresh operations |
Also Published As
Publication number | Publication date |
---|---|
CN101055761A (zh) | 2007-10-17 |
JP4188640B2 (ja) | 2008-11-26 |
EP1388865B1 (en) | 2013-08-28 |
EP1388865A2 (en) | 2004-02-11 |
TW200403685A (en) | 2004-03-01 |
CN101055762A (zh) | 2007-10-17 |
US20040027882A1 (en) | 2004-02-12 |
CN100346422C (zh) | 2007-10-31 |
KR100919270B1 (ko) | 2009-09-30 |
KR20040014274A (ko) | 2004-02-14 |
CN101051525B (zh) | 2012-07-04 |
EP1388865A3 (en) | 2004-03-31 |
US7287142B2 (en) | 2007-10-23 |
JP2004071097A (ja) | 2004-03-04 |
CN100555447C (zh) | 2009-10-28 |
CN1480949A (zh) | 2004-03-10 |
TWI223279B (en) | 2004-11-01 |
CN101051525A (zh) | 2007-10-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: FUJITSU MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: FUJITSU LIMITED Effective date: 20081024 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20081024 Address after: Tokyo, Japan, Japan Applicant after: Fujitsu Microelectronics Ltd. Address before: Kanagawa Applicant before: Fujitsu Ltd. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: SUOSI FUTURE CO., LTD. Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR CO., LTD. Effective date: 20150512 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20150512 Address after: Kanagawa Patentee after: Co., Ltd. Suo Si future Address before: Kanagawa Patentee before: Fujitsu Semiconductor Co., Ltd. |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120620 Termination date: 20190805 |
|
CF01 | Termination of patent right due to non-payment of annual fee |