CN100578762C - 电路装置及混合集成电路装置 - Google Patents
电路装置及混合集成电路装置 Download PDFInfo
- Publication number
- CN100578762C CN100578762C CN200510074718A CN200510074718A CN100578762C CN 100578762 C CN100578762 C CN 100578762C CN 200510074718 A CN200510074718 A CN 200510074718A CN 200510074718 A CN200510074718 A CN 200510074718A CN 100578762 C CN100578762 C CN 100578762C
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- Prior art keywords
- wiring layer
- connecting portion
- circuit element
- insulating barrier
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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Abstract
一种电路装置,提高了散热性。本发明混合集成电路装置(10)的制造方法中,在第一配线层(18A)上设有仿真图案(D1)。另外,在第二配线层(18B)上设有第二仿真图案(D2)。而且,第一仿真图案D1和第二仿真图案D2通过贯通绝缘层17的连接部25连接。因此,可主动地介由仿真图案散热。另外,即使在构成多层配线时,也可以确保散热性。
Description
技术领域
本发明设计电路装置,特别是涉及具有介由绝缘层层积的多个配线层的电路装置。
背景技术
参照图17说明现有的混合集成电路装置100的结构(例如参照专利文献1)。图17(A)是混合集成电路装置100的立体图,图17(B)是图17(A)的X-X’线的剖面图。
现有的混合集成电路装置100具有矩形的衬底106和设于衬底106表面的绝缘层107。在该绝缘层107上构图配线层108。另外,在配线层108上固定有电路元件104,电路元件104和配线层108通过金属线15电连接。和配线层108电连接的引线101导出到外部。另外,混合集成电路装置100的整体被密封树脂102密封。作为利用密封树脂102密封的方法有使用热塑性树脂的注入模模制和使用热硬性树脂的传递模模制。
专利文献1:特开平6-177295号公报
但是,在上述的混合集成电路装置100中,为提高散热性,而采用由金属构成的衬底106,但由于形成于衬底106表面的绝缘层107的热电阻大,故难于将内部产生的热有效地排出到外部。作为提高绝缘层107的散热性的方法,有在绝缘层107中混入无机填充物的方法。但是,和铜等金属相比,存在混入有无机填充物的绝缘层107的散热性不足的问题。
发明内容
本发明是鉴于上述问题点而开发的,本发明的主要目的在于,提供一种电路元件搭载用基板,通过形成仿真图案,提高散热性。
本发明提供一种电路元件搭载用基板,其具有多个绝缘层和多个配线层,所述绝缘层和所述配线层交替层积,,其特征在于,包括所述配线层由与内装的电路元件电连接构成电路的一部分的导电图案、和不通过电路的电信号的仿真图案。
另外,本发明提供一种电路元件搭载用基板,其具有多个绝缘层和多个配线层,所述绝缘层和所述配线层交替层积,其特征在于,包括所述配线层由与内装的电路元件电连接使电信号通过的导电图案、和不通过所述电信号的仿真图案;设于所述各配线层的所述仿真图案相互之间通过贯通所述绝缘层的连接部热接合;所述连接部由从位于所述绝缘层下层的所述配线层向上方凸状延伸的第一连接部和从位于绝缘层上层的配线层向下方凸状延伸的第二连接部构成,所述第一连接部和所述第二连接部在所述绝缘层的厚度方向的中间部接触。
另外,在本发明的电路元件搭载用基板中,其特征在于,在各所述配线层上设置所述仿真图案。
在本发明的电路元件搭载用基板中,其特征在于,在未形成所述导电图案的几乎所有区域设置所述仿真图案。
在本发明的电路元件搭载用基板中,其特征在于,矩形形状相等大小的所述仿真图案等间隔地排列。
在本发明的电路元件搭载用基板中,其特征在于,所述第一连接部通过蚀刻加工一张铜箔形成,所述第二连接部由镀膜构成。
在本发明的电路元件搭载用基板中,其特征在于,在表面被绝缘处理的电路衬底的表面形成所述第一配线层及所述第二配线层。
根据本发明的电路元件搭载用基板,通过设置不通过电信号的仿真图案,可介由仿真图案进行热传导,将内部产生的热顺畅地排出导外部。另外,通过利用连接部将设于多层配线的各层的仿真图案连接,可进一步实现散热性的提高。
附图说明
图1是说明本发明电路装置的立体图(A)、剖面图(B)、剖面图(C);
图2是说明本发明电路装置的剖面图(A)、剖面图(B)、立体图(C);
图3(A)-(C)是说明本发明电路装置的剖面图;
图4(A)-(C)是说明本发明电路装置制造方法的剖面图;
图5(A)-(D)是说明本发明电路装置制造方法的剖面图;
图6是说明本发明电路装置制造方法的剖面图(A)、剖面图(B)、平面图(C);
图7(A)-(C)是说明本发明电路装置制造方法的剖面图;
图8(A)-(C)是说明本发明电路装置制造方法的剖面图;
图9是说明本发明电路装置制造方法的剖面图(A)、剖面图(B);
图10(A)-(C)是说明本发明电路装置制造方法的剖面图;
图11(A)、(B)是说明本发明电路装置制造方法的剖面图;
图12是说明本发明电路装置制造方法的剖面图;
图13(A)、(B)是说明本发明电路装置的剖面图;
图14(A)-(E)是说明本发明电路装置制造方法的剖面图;
图15(A)-(E)是说明本发明电路装置制造方法的剖面图;
图16(A)、(B)是说明本发明电路装置制造方法的剖面图;
图17是说明现有的电路装置的立体图(A)、剖面图(B)。
具体实施方式
第一实施形态
在本形态中,作为电路装置之一例,以图1等所示的混合集成电路装置为例进行说明。但是,下述的本形态也可以适用于其它种类的电路装置。
参照图1说明本发明的混合集成电路装置10的结构。图1(A)是混合集成电路装置10的立体图,图1(B)是图1(A)的X-X’平面的剖面图。
在混合集成电路装置10中,参照图1(A)及图1(B),在作为支承衬底起作用的电路衬底16表面形成有由配线层18及电路元件14构成的电路。另外,形成于电路衬底16表面的电路利用密封树脂12密封。在电路衬底16的周边部,引线11被固定在最上层的配线层18上,引线11的端部从密封树脂12导出到外部。在本形态中,配线层18具有多层配线结构,在此,实现由第一配线层18A及第二配线层18B构成的两层配线结构。各配线层18介由绝缘层层积。另外,在第一配线层上形成有第一仿真图案D1,在第二配线层上形成有第二仿真图案D2。在此,第一仿真图案D1及第二仿真图案D2介由连接部25热接合。而且,半导体元件14A搭载于多个第二仿真图案D2的上方。下面将详细说明具有这种概略结构的混合集成电路装置10。
电路衬底16是由金属或陶瓷等构成的衬底,这从散热的意义上来说是理想的。另外,作为电路衬底16的材料,作为金属可采用Al、Cu或Fe等,作为陶瓷可采用Al2O3、AlN。除此之外,也可以采用机械强度或散热性优良的其他材料作为电路衬底16的材料。
另外,电路衬底16可采用挠性衬底、印刷线路板、玻璃环氧树脂衬底等。
在本形态中,在由铝构成的电路衬底16的表面形成绝缘层17,在绝缘层17表面形成配线层18。另外,在本形态中,也可以采用以铜为主体的金属作为电路衬底16的材料。由于铜是导热性优良的材料,故可提高装置整体的散热性。另外,在采用Al时,考虑机械强度,至少可以在表面形成氧化铝。
第一绝缘层17A在电路衬底16的表面形成,覆盖电路衬底16的实质上整个区域。第一绝缘层17A可采用填充有填充物的树脂。在此,填充物例如可采用铝化合物、钙化合物、砷化合物、镁化合物或硅化合物。另外,为提高装置整体的散热性,而在第一绝缘层17A中含有比其它绝缘层多量的填充物,其重量填充率例如为60%~80%。另外,通过在第一绝缘层17A中混入直径50μm或其以上的大径填充物,也可以提高散热性。第一绝缘层17A的厚度根据要求的耐压而变化,但优选约50μm~数百μm程度。
第一配线层18A由铜等金属构成,在第一绝缘层17A表面进行构图。该第一配线层18A和上层的第二配线层18B电连接,具有主要回绕设置图案的功能。
第二绝缘层17B在电路衬底16表面形成,覆盖第一配线层18A。而且,在第二绝缘层17B上贯通形成电连接第一配线层18A和第二配线层18B的连接部25。因此,第二绝缘层17B为了容易形成连接部25,故和第一绝缘层17A相比较可以混入少量的填充物。这意味着填充物的含有率小。另外,根据相同的理由,第二绝缘层17B中含有的填充物的平均粒径也可以比第一绝缘层17A中含有的填充物的平均粒径小。
第二配线层18B形成于第二绝缘层17B的表面。第二配线层18B形成载置电路元件14的接合面、和电路元件上的电极连接的焊盘、电连接该焊盘的配线部、及固定引线11的焊盘等。另外,第二配线层18B和第一配线层18A可平面交叉地形成。因此,即使在半导体元件14A具有多个电极的情况下,也可以利用本申请的多层配线结构进行交叉,可自由地进行图案的盘绕设置。该第二配线层18B和上述的第一配线层18A介由连接部25在所希望的位置连接。当然,也可以根据半导体元件的电极数量、元件的安装密度增加到3层、4层、5层或5层以上。
连接部25是贯通第二绝缘层17B将第一配线层18A和第二配线层18B电连接的部位。在本形态中,连接部25由从第一配线层18A连续延伸的第一连接部25A和从第二配线层18B连续延伸的第二连接部25B构成。
电路元件14固定于第二配线层18B上,由电路元件14和配线层18构成规定的电路。电路元件14采用晶体管、二极管、IC或系统LSI等有源元件,或电容、电阻等无源元件。另外,功率类半导体元件等发热量大的元件也可以介由由金属构成的散热片固定在电路衬底16上。在此,半导体元件14A是面朝上型,故介由金属细线15和第二配线层18B电连接。但也可以通过面朝下结合法安装。
半导体元件14A是在其表面具有数十个~数百个焊盘的半导体元件。另外,也可以采用所谓的系统LSI作为半导体元件14A。在此,系统LSI是指具有模拟运算电路、数字运算电路或存储部等,且由一个LSI实现系统功能的大规模的元件。因此,和现有的LSI相比,系统LSI伴随大量的发热而动作。
在半导体元件14A的背面和接地电位连接时,半导体元件14A的背面利用焊料或导电膏等固定。在半导体元件14A的背面浮置时,使用绝缘性粘结剂固定半导体元件14A的背面。另外,在半导体元件14A通过面朝下结合法安装时,介由由焊锡等构成的补片电极安装。
可采用控制大电流的功率类晶体管、例如功率功率管理操作系统、GTBT、IGBT、半导体开关元件等作为半导体元件14A。也可以采用功率类IC作为半导体元件14A。
近年来,由于芯片尺寸小且薄型高功能化,故如图1所示,从装置整体、或模块整体来看,产生的热量逐年增大。例如,控制计算机的CPU就是其一例。另一方面,Si芯片本身更薄、更小型化。因此,每单位面积的热的产生量逐年增加。而且,由于安装多个这种IC或晶体管,故作为装置整体产生的热大幅度增大了。
引线11在电路衬底16的周边部固定在第二配线层18B上,具有例如和外部进行输入·输出的作用。在此,在一边上设有多个引线11,但也可以配置于对向的两个边、四个边。引线11和图案的粘接介由焊锡等焊料19进行。
密封树脂12通过使用热硬性树脂的传递模模制或使用热塑性树脂的注入模模制形成。在此,形成密封树脂12,使其密封电路衬底16及形成于其表面的电路,电路衬底16的背面从密封树脂12露出。另外,模制以外的密封方法例如可使用罐封进行的密封、壳体件进行的密封等众所周知的密封方法。参照图1(B),为使从载置于电路衬底16表面的电路元件14产生的热顺畅地排出到外部,电路衬底16的背面从密封树脂12露出到外部。另外,为提高装置整体的耐湿性,也可以利用密封树脂12密封也含有电路衬底16背面的整体。
在本形态中,通过在各配线层上形成仿真图案,在仿真图案上固定半导体元件14A,实现散热性的提高。另外,通过介由连接部25将形成于各配线层的仿真图案连接,实现散热性的进一步提高。另外,通过使仿真图案与电路独立,可保护半导体元件14A不受电噪声干扰。下面详细叙述本形态的仿真图案。
本形态的各配线层18由和内装的电路元件电连接且通过电信号的导电图案和不通过电信号的仿真图案构成。在此,仿真图案可考虑两个形态。第一仿真图案的形态是物理分离形成的图案,其和导电图案不导通。另一种仿真图案是虽然和电信号通过的导电图案导通但不能通过电信号的图案。电信号通过的导电图案其两端与电路元件14或引线11等连接。与此相对,这里的仿真图案一侧端部虽然与导电图案连接,但另一侧端部不和其它电路元件等连接,形成终端。
第一仿真图案D1是由第一配线层18A的一部分构成的导电图案。在此,在LSI元件即半导体元件14A的下方形成有多个第一仿真图案D1。在此,相同程度大小的第一仿真图案D1等间隔地形成。具体地说,可以间隔100μm程度配置例如300μm左右见方的大小的正方形第一仿真图案D1。即,这里,在半导体元件14A下方的区域具有未形成和电路元件14电连接而构成电路的图案的部分。而且,在该部分形成有第一仿真图案D1。由此,介由仿真图案D1可将从半导体装置14A产生的热有效地传递到电路衬底16上。
第二仿真图案D2是由第二配线层18B的一部分构成的图案,其详细情况和上述的第一仿真图案D1相同。第一仿真图案D1和第二仿真图案D2介由贯通第二绝缘层17B形成的连接部25连接。该连接部25由从下层的第一仿真图案D1向上方突出的第一连接部25A和从上层的第二绝缘层17B向下方突出的第二连接部25B构成。而且,第一连接部25A和第二连接部25B在第二绝缘层17B的厚度部分的中间部接触。由此,可提高连接部25相对于热应力的可靠性。
在半导体元件14A的背面不和外部电连接而浮置时,第一仿真图案D1及第二仿真图案D2最好和接地电位连接。这是由于,考虑使两个仿真图案电独立时,在使用状况下,两个仿真图案的电位变化,有可能导致半导体元件14A误动作。
另外,在纸面上,第一仿真图案D1及第二仿真图案D2位于半导体元件14A的下方,但可以在半导体元件14A的一部分的下方形成这些仿真图案。在半导体元件14A的表面具有局部产生大的热量的位置(发热点)。具体地说,从外部输入时钟脉冲的部分多产生大量的热。因此,通过在对应这样的发热点的下方的区域配置本形态的仿真图案,可提高散热性。另外,也可以在半导体元件14A下方之外的区域形成仿真图案。
在各配线层18上,本形态的仿真图案最好埋入未设置构成电路的导电图案的位置。由此,可在各配线层18的实质整个区域配置由导热性优良的金属构成的图案,故可极大地提高装置整体的散热性。另外,在配置伴随发热而动作的电路元件14的区域配置仿真图案后,也可以将电信号通过的导电图案配置在其余的区域。由此,可实现最大限度考虑了散热性的图案的布置。
参照图1(C),在此,形成于各配线层18上的仿真图案未通过连接部25连接。即使是这种结构的仿真图案,也可以可靠地提高装置整体的散热性。
参照图2(A)及图2(B),详细说明将各配线层18相互连接的连接部25。
参照图2(A),在此,在第一配线层18A上设有与其连续而向上方突出的第一连接部25A。另外,在第二配线层18B上形成有与其连续的向下方突出的第二连接部25B。通过使第一连接部25A和第二连接部25B在第二绝缘层17B的厚度方向的中间部接触,形成连接部25。这样,通过使两者在第二绝缘层17B的中间部接触,可提高连接强度。特别是在本形态的仿真图案上大量的热通过,但即使在这种情况下,也可以确保连接部25相对于热应力的连接可靠性。
参照图2(B),在此,形成有从第二配线层18B连续向下方延伸的连接部25。即使是该图所示的结构的连接部25,也可以将形成于各配线层18的仿真图案热接合。
参照图2(C)的立体图说明形成于电路衬底16表面的第二配线层18B的具体形状之一例。在同图的图示中,省略了密封整体的树脂。
参照同图,第二配线层18B构成安装电路元件14的接合焊盘的部分和固定引线11的焊盘26等。另外,在半导体元件14A的周边部形成多个引线接合金属细线15的焊盘。在载置有具有多个接合焊盘的半导体元件14A的情况下,仅通过第二配线层18B构成的单层的图案,由于受配线密度限制,故有可能不能充分的回绕设置。在本形态中,通过在电路衬底16的表面构筑多层配线结构,实现了复杂的图案的回绕设置。
参照图3说明其它形态的电路装置的结构。
首先,参照图3(A),在此,第一仿真图案D1介由连接部25和电路衬底16热连接。因此,可将从半导体元件14A产生的热迅速地导向电路衬底16,可提高散热性。在此,将设于各配线层18的仿真图案介由连接部25沿厚度方向连接。另外,最下层的第一仿真图案D1介由连接部25和电路衬底16连接。因此,具有即使在形成有多层配线结构的情况下,也可以介由形成于各层的仿真图案将热良好地传递到电路衬底16的优点。
参照图3(B),在此构成四层配线,在各配线层上形成有分割成多个的仿真图案组。另外,在第一配线层18A形成有第一仿真图案D1。在第二配线层18B形成有第二仿真图案D2。在第三配线层18C上形成有第三仿真图案D3。在第四配线层18D上形成有第四仿真图案D4。而且,形成于各配线层的仿真图案通过连接部25电连接,但和在装置内部构成的电路电气上独立。
在此,通过将形成于各配线层的仿真图案配置在搭载半导体元件14A的区域的正下方,可缩短热的传导距离,提高散热性。
参照图3(C),在此,在载置焊盘数量多的半导体元件14A的区域的电路衬底16表面形成有多层配线结构,在固定电路元件14B的区域的电路衬底16表面形成有单层的配线结构。
另外,多层形成的部分的第二导电图案18B和单层形成的部分的第一导电图案18A介由金属细线15电连接。
电路元件14B例如是功率类半导体元件,是伴随大量发热的开关元件。形成由第一导电图案18A构成的单层配线结构的部分的电路衬底16比其它区域的散热效果大。因此,如电路元件14B那样发热量大的分立的晶体管最好直接固定在构成单层配线的第一导电图案18A上。
在此,半导体元件14A是伴随大量发热而动作的元件。因此,通过将半导体元件14A固定在第二仿真图案D2上,提高散热性。具体的散热经路是:第二仿真图案D2→第一仿真图案D1→第一绝缘层17A→电路衬底16→外部。在本形态中,在第二仿真图案D2的正下方形成第一仿真图案D1。因此,可将产生的热以最短距离排出到外部,提高散热性。另外,在本形态中,第一仿真图案D1和第二仿真图案D2热连接。因此,可将从半导体元件14A产生的热迅速地向外部排出。另外,第一仿真图案D1和第二仿真图案D2与电路电气独立。因此,电噪声产生的影响不会施加在半导体元件14A上,故可实现可靠性高的电路装置。
其次,作为电路装置之一例,以混合集成电路装置为例进行制造方法的说明。但是,下述的本形态的制造方法也可以适用于其它种类的电路装置的制造方法。
首先,参照图4(A),在电路衬底16的表面涂敷第一绝缘层17A,层积第一导电膜28A。电路衬底16可采用厚度1.5mm程度的金属板。另外,作为第一导电膜28A,可采用以铜为主材料的材料、以Fe-Ni或Al为主材料的材料。第一导电膜28A的厚度需要为将予定形成的配线层18A的厚度和第一连接部25A的高度相加的厚度或其以上。具体地说,第一导电膜28A的厚度为例如20μm~150μm程度的范围。抗蚀剂29覆盖预定形成第一连接部25A的区域的第一导电膜28A的表面。在利用抗蚀剂29覆盖的状态下,进行蚀刻,另外,第一绝缘层17A可采用在环氧树脂等绝缘性树脂中混入了无机填充物的物质。在此,混入的无机填充物为SiO2、Al2O3、SiC、AlN等。
图4(B)表示进行蚀刻后的状态的剖面。在此,由抗蚀剂29覆盖的区域凸状地突出。利用该凸状突出的部位形成第一连接部25A。而且,在表面露出的状态下进行蚀刻的区域的第一导电膜28A的厚度同样变薄。在本工序结束后,将抗蚀剂29剥离。在此,第一连接部25A突出的高度被调整为数十μm程度。图4(C)表示剥离抗蚀剂29后的状态的第一连接部25A。
其次,参照图5(A)~图5(C),利用抗蚀剂29覆盖也含有第一连接部25A上面的第一导电膜28A。选择地形成抗蚀剂29。然后,进行介由抗蚀剂29的蚀刻,进行第一配线层18A的构图。在第一配线层18A的蚀刻结束后,将抗蚀剂29剥离。
参照图5(D),其次,介由覆盖第一配线层18A的第二绝缘层17B层积第二导电膜28B。该方法考虑以下三个方法。第一个方法是覆盖第一配线层18A形成第二绝缘层17B,然后,在第二绝缘层17B的表面形成由镀膜构成的第二导电膜28B的方法。第二个方法是在进行第二绝缘层17B的形成后,将由轧制铜箔等构成的第二导电膜28B压装在第二绝缘层17B的表面的方法。根据该第二个方法,使第二绝缘层17B和第二导电膜28B粘接的强度提高。第三个方法是层积背面附着有第二绝缘层17B的第二导电膜28B,使其覆盖第一配线层18A的方法。该第三个方法,也可以提高第二绝缘层17B和第二导电膜28B粘接的强度。
另外,第一连接部25A的侧面构成圆锥形状,由此,具有容易地对第二树脂层17B埋入第一连接部25A的优点。
参照图6,其次,部分地除去形成连接部25的位置的第二绝缘层17B及第二导电膜28B,形成通孔。首先,参照图6(A),部分地除去对应形成通孔32的予定区域的第二导电膜28B。具体地说,除形成通孔32的予定区域外,在第二导电膜28B的表面形成抗蚀剂29,然后,进行蚀刻。由此,部分地除去第二导电膜28B,形成通孔32。另外,通过除去其下方的第二绝缘层17B,加深通孔32。然后,使第一配线层18A的表面在通孔32的下面露出。在此,使设于第一配线层18A的第一连接部25A的上面在通孔32的下面露出。
参照图6(B)进一步详细叙述通孔32的形成方法。在本形态中,通过埋入第一连接部25A,减薄通孔32下方的第二绝缘层17B。而且,通过使用激光等除去变薄的区域的第二绝缘层17B,在通孔32的下部露出第一连接部25A。在大部分的区域,第二绝缘层17B的厚度T2为例如50μm程度。与此相对,对应通孔32下方的区域的第二绝缘层17B的厚度T1例如薄至10μm~25μm程度。
因此,在假定利用激光形成相同宽高比的通孔32的情况下,根据本形态,可形成直径小的通孔32。在上述这样的条件下,由于可将通孔的直径形成一半左右,故可将通孔32占有的面积减小到1/4程度。这有利于装置整体的小型化。另外,为确保散热性,在第二绝缘层17B中混入无机填充物,由此,利用激光形成通孔稍有困难。在这种情况下,为形成通孔32,减薄形成通孔32的区域的第二绝缘层17A也是有意义的。
参照图6(C)详细说明形成通孔32的上述工序。该图表示形成于第一配线层18A上的第一仿真图案D1和通孔32的平面位置关系。在此,正方形形状的仿真图案D1等间隔地配置成矩阵状。各仿真图案D1的大小例如为一个边的长度为300μm四方的正方形。仿真图案D1相互之间例如相互间隔100μm程度而配置。
激光的照射区域A1是圆形区域,其直径为250μm程度。而且,通孔32位于照射区域A1的区域内部。通孔32也具有圆形形状,其直径例如为150μm程度。即,在本形态中,将具有比照射区域A1小若干的尺寸的通孔32的第二导电膜28B作为掩膜使用,利用激光进行除去。这种工序称为保形通路。另外,本形态的第一仿真图案D1成为比激光的照射区域A1大一些尺寸的矩形。
图7(A)表示利用上述方法形成通孔32后的剖面。第一连接部25A的上面从各通孔32的下面露出。而且,混入第二绝缘层17B中的填充物从利用激光处理形成的通孔32的侧壁露出。为提高散热性,在本形态的第二绝缘层17B中混入有多种直径的填充物。因此,通孔32的侧壁形成具有凹凸的形状。作为这些填充物,代表性的是Al2O3、AlN等。另外,在上述的激光处理使通孔32的底部残存残渣时,要进行用于清除该残渣的清洗。
第一连接部25A的平面大小比形成于其上方的通孔32大。换句话说,由于通孔32及第一连接部25A的平面的形状是圆形,故第一连接部25A的直径形成的比通孔32的直径大。列举一例,在通孔32的直径W1为100μm程度时,第一连接部25A的直径W2为150μm~200μm程度。另外,在通孔32的直径W1为30μm~50μm程度时,第一连接部25A的直径W2调整为50μm~70μm程度。这样,通过使第一连接部25A的平面大小比通孔32的大,即使在多少伴随位置偏差而形成通孔32时,也可以使通孔32位于第一连接部25A的上方。因此,可防止该位置偏差造成的连接可靠性降低。另外,也可以采用圆形之外的形状作为第一连接部25A的平面形状。
参照图7(B),在此,通过在第一连接部25A的上面照射激光,设置凹部20。该凹部20的形成可通过在从通孔32的底部露出第一连接部25A的上面后连续照射激光来进行。另外,在本形态中,可利用二氧化碳激光或YAG激光进行上述利用激光的除去。在考虑凹部29的形成时,最好使用YAG激光。采用YAG激光的波长带的激光是由于作为第一连接部25A的材料的铜的反射率小,可容易地形成凹部。
通过设置上述凹部20,可提高之后的工序中形成于通孔32内壁的镀膜和第一连接部25A接合的强度。因此,可提高连接各配线层相互之间的连接部25的连接可靠性。埋入凹部20的部分的镀膜相对于来自横向的龟裂具有强的抵抗性。
参照图7(C),通过上述工序,在各通孔32的下部使第一连接部25A的上面露出。在上述的说明中,在层积第二导电箔28B后,形成通孔32,但也可以在形成通孔32后,层积第二导电箔28B。
另外,为在以下的工序进行镀敷处理,进行作为前处理的锌酸盐处理。在此,锌酸盐处理是通过使用含有Zn离子的碱溶液进行无电解镀敷处理使镀敷处理容易的处理。
参照图8及图9,其次,说明通过在通孔32中形成镀膜,形成第二连接部25B,使第一配线层18A和第二导电膜28B导通的工序。该镀膜的形成考虑两个方法,第一方法是在利用无电解镀敷形成镀膜后,利用电解镀敷再次形成镀膜的方法。第二个方法是仅通过电解镀敷处理形成镀膜的方法。
参照图8说明形成镀膜的上述第一方法。首先,参图8(A),在也含有通孔32侧壁的第二导电膜28B的表面通过无电解镀敷处理形成镀膜34。该镀膜34的厚度为3μm~5μm程度即可。
其次,参照图8(B),在镀膜34的上面利用电解镀敷法形成新的镀膜35。具体地说,将形成镀膜34的第二导电膜28B作为阴极电极,利用电解镀敷法形成镀膜35。利用上述的无电解镀敷法在通孔32的内壁形成镀膜34。因此,这里形成的镀膜35包括通孔32的内壁也形成一样的厚度。由此,形成由镀膜构成的第二连接部25B。具体的镀膜35的厚度例如为20μm程度。上述的镀膜34及镀膜35的材料可采用和第二导电膜28B相同的材料即铜。另外,也可以采用铜以外的金属作为镀膜34及镀膜35的材料。
参照图8(C),在此,通过进行填充镀敷,利用镀膜35埋入通孔32。通过进行该填充镀敷,可提高第二连接部25B的机械强度。
其次,参照图9说明使用电解镀敷法形成第二连接部25B的方法。
参照图9(A),首先,使含有金属离子的溶液接触通孔32。在此,镀膜的材料可采用铜、金、银、钯等。而且,当以第二导电膜28B作为阴极电极流过电流时,金属在作为阴极电极的第二导电膜28B上析出,形成镀膜。在此,由36A、36B表示镀膜成长的状况。在电解镀敷法中,在电场强的位置优先形成镀膜。在本形态中,该电场在面向通孔32周边部的部分的第二导电膜28B增强。因此,如该图所示,从面向通孔32周边部的部分的第二导电膜28B优先成长镀膜。在形成的镀膜与第一连接部25A接触的时刻,第一配线层18A和第二导电膜28B导通。然后,同样在通孔32内部形成镀膜。由此,在通孔32的内部形成和第二导电膜28B一体化的第二连接部25B。
参照图9(B),其次说明形成第二连接部25B的另一方法。在此,通过在通孔32的周边部设置遮檐13,容易利用电解镀敷法形成第二连接部25B。在此,遮檐是指,覆盖通孔32周边部由突出的第二导电膜28B构成的部位。遮檐13的具体的制造方法在利用激光形成通孔32时,可通过增大该激光的功率进行。通过增大激光的功率,使基于激光的第二导电膜28B的除去沿横向进行,由此,遮檐13下方区域的树脂被除去。通过利用上述条件进行以第二导电膜28B为阴极电极的电解镀敷处理,从遮檐13的部分优先成长镀膜。通过从遮檐13成长镀膜,与图9(A)的情况相比,可优先向下方成长镀膜。因此,可可靠地进行基于镀膜的通孔32的埋入。
如上所述,本形态的通孔32的侧壁构成具有凹凸的形状。另外,在通孔32的侧壁露出混入第二绝缘层17B中的无机填充物。由此,难于在通孔32的侧壁形成镀膜。通常,在作为无机物的填充物表面难于附着镀膜,特别是在AlN在通孔32的侧壁露出时,难于形成镀膜。因此,在本形态中,通过使用上述电解镀敷法的方法形成第二连接部25B。
在本形态中,通过在通孔32中形成镀膜,必然也在第二导电膜28B的表面形成镀膜,其厚度增厚。但是,在本形态中,如上所述,由于在10μm程度的浅的通孔32中形成镀膜,故可减薄形成的镀膜的总厚度。因此,由于镀膜附着带来的第二导电膜28B的厚度的增加量小,故可将第二导电膜28B保持在薄的状态下。因此,可微细地形成由第二导电膜28B形成的第二配线层18B。
另外,即使在通过施行填充镀敷,埋入通孔32时,如上所述,由于通孔32较浅地形成,因此,可容易地进行填充镀敷。
参照图10(A),通过形成第二连接部25B,形成由第一连接部25A及第二连接部25B构成的连接部25。另外,参照图10(B),通过进行使用抗蚀剂29的选择性蚀刻,形成第二配线层18B。进一步参照图10(C),在此,形成由第一配线层18A、第二配线层18B、第三配线层18C构成的三层的多层配线。此时,在第二配线层18B上,在上面及下面两面形成凸状突出的连接部25。
参照图11(A),其次,介由焊锡或导电膏等将电路元件14固定在第二配线层18B(岛)上。在此,利用面朝上接合法安装半导体元件,但也可以根据需要利用面朝下接合法进行。另外,参照图11(B),介由金属细线15进行电路元件14和第二配线层18B的电连接。
在上述工序结束后,进行各单元24的分离。各单元24的分离可通过使用冲压机的冲切、切割、折曲等进行。另外,在通过切割或折曲进行分割时,可通过在各单元24的分界设置槽而使分离容易进行。然后,在各单元24的电路衬底16上固定引线11。
参照图12,其次,进行各电路衬底16的树脂密封。在此,通过使用热硬性树脂的传递模模制进行密封。即,在由上模型30A及下模型30B构成的模型30中收纳电路衬底16,然后,通过将两模型咬合,进行引线11的固定。然后,通过向模腔31中封入树脂,进行树脂密封的工序。利用以上的工序制造例如图1所示结构的混合集成电路装置。
第二实施形态
参照图13说明本发明电路装置的结构。在本形态中,说明图13所示的极薄型的具有多层配线的电路装置的结构及其制造方法。在这种多层配线中,也可以通过在第二仿真图案D2上进行固定,得到和上述的电路装置相同的效果。
首先,参照图13(A),本形态的电路装置具有由第一配线层40A、第二配线层40B、将上述第一配线层40A和上述第二配线层40B粘接成片状的绝缘层41构成的多层配线。另外,在第二配线层40B上固定有半导体元件14A及电路元件14。第一配线层40A和第二配线层40B在所希望的位置利用连接部25接合。另外,第一配线层40A含有和电路独立的第一仿真图案D1。第二配线层40B含有和电路独立的第二仿真图案D2。另外,第二仿真图案D2形成于第一仿真图案D1的正下方,和第一仿真图案D1电连接。
在此,半导体元件14A是伴随大量发热而动作的元件。因此,通过将半导体元件14A固定在第二仿真图案D2上,提高散热性。具体的散热经路是:第二仿真图案D2→第一仿真图案D1→外部。在本形态中,在第二仿真图案D2的正下方形成第一仿真图案D1。因此,可将产生的热以最短距离排出向外部,提高散热性。另外,在本形态中,第一仿真图案D1和第二仿真图案D2电连接。因此,可将从半导体元件14A产生的热迅速地排出向外部。另外,第一仿真图案D1和第二仿真图案D2与电路电气独立。因此,由于不会将电噪声产生的影响给予半导体元件14A,故可实现可靠性高的电路装置。另外,通过在第一仿真图案D1上形成外部电极,并和安装衬底连接,可进一步提高散热性。
参照图13(B)说明本形态的电路装置的另一结构。基本的结构和使用图13(A)说明的电路装置相同。在此,配线层形成4层,在各配线层上设有分割成多个的仿真图案组。在第一配线层40A上形成有第一仿真图案D1。在第二配线层40B上形成有第二仿真图案D2。在第三配线层40C上形成有第三仿真图案D3。在第四配线层40D上形成有第四仿真图案D4。而且,形成于各配线层的仿真图案通过连接部25电连接,但和电路电气独立。
即使这样的多层配线结构,也可以通过将半导体元件14A固定在第四仿真图案D4上,得到和上述第一实施例相同的效果。
其次,参照图14~图16说明本形态的电路装置的制造方法。但是,下述的本形态的制造方法也可以适用于其它种类的电路装置的制造方法。
首先,参照图14(A),准备第一导电片50A,在其表面构图抗蚀剂29。在此,抗蚀剂29覆盖较厚地形成的予定位置。另外,第一导电片50A的材料可优选采用以Cu为主材料的材料或公知的引线架的材料。第一导电片50A的厚度根据形成的配线层的厚度不同而不同。如予定形成的导电图案的厚度为数百μm程度,则采用该厚度或其以上的膜厚的第一导电片50A。
参照图14(B),以抗蚀剂29为蚀刻掩膜,进行湿式蚀刻,进行不形成抗蚀剂29的主面的蚀刻。通过该蚀刻未由抗蚀剂29覆盖的区域的第一导电片50A的表面被蚀刻,形成第一连接部25A。
参照图14(C),在通过蚀刻在第一导电片50A上形成第一连接部25A后,将抗蚀剂29剥离。
参照图14(D),在第一导电片50A上粘附绝缘层52。此时,第一连接部25A被埋入绝缘层52。当由真空压力机进行该粘附时,可防止第一导电片50A和绝缘层52之间的空气产生的空隙。另外,通过各向同性蚀刻形成的第一连接部25A的侧面构成圆滑的曲面。因此,在将第一导电片50A压入绝缘层52时,沿该曲面浸入树脂,消除未填充部。因此,利用这样的第一连接部25A的侧面形状也可抑制空隙的产生。另外,通过将第一连接部25A埋入绝缘层52,可提高第一导电片50A和绝缘层52的粘附强度。
参照图14(E),将第二导电片50B粘附在绝缘层52上。另外,通过利用上述的真空压力机进行粘附,可防止第二导电片50B和绝缘层52之间的空气产生的空隙。
参照图15(A),由抗蚀剂29进行覆盖,仅露出形成第二导电片50B的通孔32的部分。其次,介由抗蚀剂29蚀刻第二导电片50B。第二导电片50B是以Cu为主材料的片,故蚀刻液使用氯化铁或氯化铜进行化学蚀刻。另外,在进行该蚀刻时,第二导电片50B由粘接性的片等覆盖,以保护其不受蚀刻液侵蚀。但是,如第二导电片50B本身十分厚,为在蚀刻后也可以维持平坦性的膜厚,则稍微被蚀刻也没关系。
参照图15(B),在去除抗蚀剂29后,以第二导电片50B为掩膜,利用激光去除通孔32正下方的绝缘层52,使第一导电片50A的背面在通孔32的底部露出。激光最好使用二氧化碳激光。另外,在利用激光蒸发绝缘树脂后,在开口部的底部存在残渣时,利用过锰酸钠或过硫酸铵等进行湿式蚀刻,去除该残渣。
参照图15(C),在包括通孔32的第二导电片50B的整个面上形成镀膜,由此,形成将第一导电片50A和第二导电片50B电连接的第二连接部25B。该镀膜通过无电解镀敷或电解镀敷及无电解镀敷和电解镀敷的组合形成。
参照图15(D),在第一导电片50A和第二导电片50B上重新涂敷抗蚀剂29。其次,在第一导电片50A上构图抗蚀剂29,使其形成第一配线层40A。同样,也构图涂敷于第二导电片50B的抗蚀剂29。
参照图15(E),通过介由如上形成的抗蚀剂29蚀刻第一导电片50A及第二导电片50B,形成第一配线层40A及第二配线层40B。在蚀刻结束后,将抗蚀剂29剥离。
参照图16(A),介由焊锡或导电膏等将半导体元件14A及电路元件14固定在第二配线层40B(岛)上。然后,介由金属细线15将电路元件14和导电图案电连接。在此,半导体元件14A被固定在第二仿真图案D2上。另外,第二仿真图案D2和半导体元件14A没有电连接。
参照图16(B),进行电路元件14、金属细线15及第二配线层40B的树脂密封。树脂密封的方法可采用传递模模制、注入模模制、或浸渍。作为树脂材料,环氧树脂等热硬性树脂可通过传递模模制实现,聚酰亚胺树脂、硫化聚苯等热塑性树脂可通过注入模模制实现。在进行树脂密封后,利用绝缘性树脂覆盖第一配线层40A,设置外部电极45,由此完成电路装置。
Claims (16)
1、一种电路元件搭载用基板,具有多个绝缘层和多个配线层,所述绝缘层和所述配线层交替层积,其特征在于,所述配线层包括与搭载的电路元件电连接且构成电路的一部分的导电图案、和不通过电路的电信号的仿真图案,所述仿真图案形成在所述电路元件的下方;设于所述各配线层的所述仿真图案相互之间利用贯通所述绝缘层的连接部导热地接合;所述连接部由从位于所述绝缘层下方的所述配线层向上方凸状延伸的第一连接部和从位于绝缘层上层的配线层向下方凸状延伸的第二连接部构成,所述第一连接部和所述第二连接部在所述绝缘层的厚度方向的中间部接触。
2、如权利要求1所述的电路元件搭载用基板,其特征在于,对各所述配线层设置所述仿真图案。
3、如权利要求1所述的电路元件搭载用基板,其特征在于,在未形成所述导电图案的大部分区域设置所述仿真图案。
4、如权利要求1所述的电路元件搭载用基板,其特征在于,矩形形状的相等大小的所述仿真图案等间隔地排列。
5、如权利要求1所述的电路元件搭载用基板,其特征在于,所述第一连接部通过蚀刻加工一张铜箔而形成,所述第二连接部由镀膜构成。
6、如权利要求1所述的电路元件搭载用基板,其特征在于,在表面被绝缘处理的电路衬底的表面形成所述配线层。
7、如权利要求6所述的电路元件搭载用基板,其特征在于,所述电路元件由密封树脂覆盖。
8、一种混合集成电路装置,其特征在于,在权利要求1所述的电路元件搭载用基板上搭载有所述电路元件。
9、一种电路元件搭载用基板,具有多个绝缘层和多个配线层,所述绝缘层和所述配线层交替层积,其特征在于,所述配线层包括与搭载的电路元件电连接、且通过电信号的导电图案和不通过上述电信号的仿真图案,所述仿真图案形成在所述电路元件的下方;设于所述各配线层的所述仿真图案相互之间利用贯通所述绝缘层的连接部导热地接合;所述连接部由从位于所述绝缘层下层的所述配线层向上方凸状延伸的第一连接部和从位于绝缘层上层的配线层向下方凸状延伸的第二连接部构成,所述第一连接部和所述第二连接部在所述绝缘层的厚度方向的中间部接触。
10、如权利要求9所述的电路元件搭载用基板,其特征在于,在各所述配线层上设置所述仿真图案。
11、如权利要求9所述的电路元件搭载用基板,其特征在于,在未形成所述导电图案的区域的大部分设置所述仿真图案。
12、如权利要求9所述的电路元件搭载用基板,其特征在于,矩形形状的相等大小的所述仿真图案等间隔地排列。
13、如权利要求9所述的电路元件搭载用基板,其特征在于,所述第一连接部通过蚀刻加工一张铜箔而形成,所述第二连接部由镀膜构成。
14、如权利要求9所述的电路元件搭载用基板,其特征在于,在表面被绝缘处理的电路衬底的表面形成所述配线层。
15、如权利要求14所述的电路元件搭载用基板,其特征在于,所述电路元件由密封树脂覆盖。
16、一种混合集成电路装置,其特征在于,在权利要求9所述的电路元件搭载用基板上搭载有所述电路元件。
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JP2004162658A JP4471735B2 (ja) | 2004-05-31 | 2004-05-31 | 回路装置 |
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JP4359110B2 (ja) * | 2003-09-24 | 2009-11-04 | 三洋電機株式会社 | 回路装置 |
DE102004057494A1 (de) * | 2004-11-29 | 2006-06-08 | Siemens Ag | Metallisierte Folie zur flächigen Kontaktierung |
JP5115153B2 (ja) * | 2007-11-07 | 2013-01-09 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
US7875140B2 (en) * | 2007-11-20 | 2011-01-25 | Seiko Epson Corporation | Method for manufacturing multilayer ceramic substrate |
KR101951956B1 (ko) * | 2012-11-13 | 2019-02-26 | 매그나칩 반도체 유한회사 | 반도체 패키지용 연성회로기판 |
CN103887257A (zh) * | 2012-12-20 | 2014-06-25 | 浙江大学 | 低寄生电感电力电子模块封装结构 |
US9899330B2 (en) * | 2014-10-03 | 2018-02-20 | Mc10, Inc. | Flexible electronic circuits with embedded integrated circuit die |
JPWO2016080333A1 (ja) * | 2014-11-21 | 2017-08-24 | 株式会社村田製作所 | モジュール |
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JPWO2019198154A1 (ja) * | 2018-04-10 | 2021-04-15 | 株式会社メイコー | 部品内蔵基板、及び部品内蔵基板の製造方法 |
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JP2698278B2 (ja) | 1992-01-31 | 1998-01-19 | 三洋電機株式会社 | 混成集積回路装置 |
JP4040140B2 (ja) * | 1997-05-14 | 2008-01-30 | 富士通株式会社 | 半導体装置及びそのアクセスタイム調整方法 |
US6309956B1 (en) * | 1997-09-30 | 2001-10-30 | Intel Corporation | Fabricating low K dielectric interconnect systems by using dummy structures to enhance process |
JP3466929B2 (ja) * | 1998-10-05 | 2003-11-17 | 株式会社東芝 | 半導体装置 |
JP2001077543A (ja) * | 1999-09-03 | 2001-03-23 | Fujitsu Ltd | 多層配線基板 |
JP2001196372A (ja) * | 2000-01-13 | 2001-07-19 | Mitsubishi Electric Corp | 半導体装置 |
JP2001345398A (ja) | 2000-05-31 | 2001-12-14 | Mitsubishi Electric Corp | 高周波モジュール及び高周波モジュール装置 |
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JP2003008186A (ja) | 2001-06-21 | 2003-01-10 | Sony Corp | 半導体装置 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
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JP2006140326A (ja) * | 2004-11-12 | 2006-06-01 | Toshiba Corp | 半導体装置 |
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