CN100388469C - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
- Publication number
- CN100388469C CN100388469C CNB2005100747148A CN200510074714A CN100388469C CN 100388469 C CN100388469 C CN 100388469C CN B2005100747148 A CNB2005100747148 A CN B2005100747148A CN 200510074714 A CN200510074714 A CN 200510074714A CN 100388469 C CN100388469 C CN 100388469C
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- Prior art keywords
- insulating barrier
- conductive pattern
- filler
- circuitry substrate
- circuit arrangement
- Prior art date
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Abstract
一种电路装置及其制造方法,具有多层配线结构,且散热性也优良。本发明的电路装置(10)中,具有第一导电图(18A)及第二导电图案(18B)的多层配线结构形成于电路衬底(16)的表面。在电路衬底表面的整个区域形成第一绝缘层(17A)。第一导电图案(18A)和第二导电图案(18B)通过第二绝缘层(17B)绝缘。第二绝缘层(17B)中含有的填充物的量比第一绝缘层(17A)中含有的填充物少,且其直径小。因此,容易贯通第二绝缘层(17B)连接两导电图案。
Description
技术领域
本发明涉及电路装置及其制造方法,特别是涉及在电路衬底表面形成多层导电图案的电路装置及其制造方法。
背景技术
参照图14说明现有混合集成电路装置的结构(例如参照专利文献1)。图14(A)是混合集成电路装置100的立体图,图14(B)是图14(A)的X-X’线剖面图。
现有的混合集成电路装置100具有如下这样的结构。其包括:矩形衬底106;绝缘层107,其设于衬底106的表面;导电图案108,其形成于该绝缘层107上;电路元件104,其固定在导电图案108上;金属细线105,其将电路元件104和导电图案108电连接;引线101,其和导电图案108电连接。另外,混合集成电路装置100的整体利用密封树脂102密封。
专利文献1:特开平6-177295号公报(第4页、第1图)
目前,高功能且高输出的系统LSI等元件内装于混合集成电路装置中。为内装这种引脚数极多的元件,需要在装置内部形成更复杂的图案,且确保高散热性。但是,在上述的混合集成电路装置100中,由于导电图案108为单层的配线结构,故难于使配线相互交叉。为使导电图案108交叉,也考虑使用跨接线的结构。但是,在使用跨接线时,有可能在该跨接线的部分产生寄生电感。另外,当考虑在电路衬底106的表面形成多层配线时,还存在装置整体的散热性降低的问题。
另外,在考虑使用具有多层配线的印刷线路板作为电路衬底106时,由于印刷线路板的散热性劣化,故存在难于内装发热量大的元件的问题。另外,在考虑采用陶瓷衬底时,存在配线电阻增大的问题。
发明内容
本发明是鉴于上述问题点而开发的,本发明的主要目的在于,提供具有多层配线结构且散热性也优良的电路装置及其制造方法。
本发明电路装置包括:电路衬底;第一绝缘层,其形成于所述电路衬底表面;第一导电图案,其形成于所述第一绝缘层表面;第二绝缘层,其覆盖所述第一导电图案;第二导电图案,其介由所述第二绝缘层层积在所述第一导电图案上,在所述各绝缘层中混入填充物,在所述第一绝缘层中混入比所述第二绝缘层量多的所述填充物。
另外,本发明的电路装置包括:电路衬底;第一绝缘层,其形成于所述电路衬底表面;第一导电图案,其形成于所述第一绝缘层表面;第二绝缘层,其覆盖所述第一导电图案;第二导电图案,其介由所述第二绝缘层层积在所述第一导电图案上,在所述各绝缘层中混入填充物,所述第一绝缘层中含有的所述填充物的平均粒径比所述第二所述绝缘层中含有的所述填充物的平均粒径大。
本发明电路装置的制造方法包括:准备电路衬底的工序;在所述电路衬底表面形成混入有填充物的第一绝缘层的工序;在所述第一绝缘层表面形成第一导电图案的工序;形成比所述第一绝缘层填充物的含有量少的第二绝缘层,使其覆盖所述第一导电图案的工序;形成贯通所述第二绝缘层和所述第一导电图案电连接的第二导电图案的工序。
另外,本发明电路装置的制造方法包括:准备电路衬底的工序;在所述电路衬底表面形成混入有填充物的第一绝缘层的工序;在所述第一绝缘层表面形成第一导电图案的工序;形成含有的填充物的最大粒径比所述第一绝缘层的小的第二绝缘层,以覆盖所述第一导电图案的工序;形成贯通所述第二绝缘层和所述第一导电图案电连接的第二导电图案的工序。
根据本发明,介由混入有填充物的绝缘层在电路衬底表面层积多层导电图案,在形成于所述电路衬底表面的绝缘层上混入比其它绝缘层的量多的填充物。另外,使第一绝缘层含有的填充物的平均粒径比其它绝缘层中含有的填充物的平均粒径大。因此,可得到使散热性提高的具有多层配线的电路装置。
另外,根据本发明电路装置的制造方法,在形成将各层导电图案相互连接的连接部的绝缘层中混入有比其它绝缘层少量的填充物。因此,可贯通该绝缘层,将导电图案相互电连接。另外,通过使设置该连接部的绝缘层中含有的填充物的平均粒径比其它绝缘层中含有的填充物的平均粒径小,也可以使连接部的形成容易。
附图说明
图1是本发明混合集成电路装置的立体图(A)、剖面图(B)、剖面图(C);
图2是本发明混合集成电路装置的立体图;
图3(A)、(B)是本发明混合集成电路装置的剖面图;
图4是表示适用于本发明混合集成电路装置的填充物的特性的特性图(A)、特性图(B);
图5是本发明混合集成电路装置的剖面图(A)、剖面图(B);
图6(A)-(D)是说明本发明混合集成电路装置的制造方法的剖面图;
图7(A)-(D)是说明本发明混合集成电路装置的制造方法的剖面图;
图8(A)、(B)是说明本发明混合集成电路装置的制造方法的剖面图;
图9是说明本发明混合集成电路装置的制造方法的剖面图;
图10(A)-(E)是说明本发明混合集成电路装置的制造方法的剖面图;
图11(A)、(B)是说明本发明混合集成电路装置的制造方法的剖面图;
图12(A)、(B)是说明本发明混合集成电路装置的制造方法的剖面图;
图13是说明本发明混合集成电路装置的制造方法的剖面图;
图14(A)是现有混合集成电路装置的立体图,(B)是剖面图。
具体实施方式
在本形态中,作为电路装置之一例,以混合集成电路装置为例进行说明。参照图1说明本发明混合集成电路装置10的结构。图1(A)是混合集成电路装置10的立体图,图1(B)是图1(A)的X-X’剖面的剖面图。图1(C)是放大连接部25附近的剖面的图。
电路衬底16是由金属或陶瓷等构成的衬底,散热方面是理想的。另外,作为电路衬底16的材料,作为金属可采用Al、Cu或Fe等,作为陶瓷可采用Al2O3、AlN。也可以采用其他的机械强度及散热性好的材料作为电路衬底16的材料。在本形态中,在由铝构成的电路衬底16的表面形成绝缘层17,在绝缘层17的表面形成导电图案18。另外,在本形态中,最好采用以铜为主体的金属作为电路衬底16的材料。由于铜是导热性优良的材料,故可提高装置整体的散热性。另外,在采用Al作为电路衬底16的材料时,也可以在电路衬底16的表面形成氧化膜。
第一绝缘层17A在电路衬底16的表面形成,覆盖电路衬底16的实质上整个区域。第一绝缘层17A可采用填充有填充物的树脂。在此,填充物例如可采用铝化合物、钙化合物、砷化合物、镁化合物或硅化合物。另外,用于密封树脂12的树脂可全部采用热塑性树脂或热硬性树脂两者。另外,为提高装置整体的散热性,而在第一绝缘层17A中含有比其它绝缘层的量大的填充物,其重量填充率为例如60%~80%。另外,在第一绝缘层17A中混入直径等于或大于50μm的大径的填充物,也可以提高散热性。第一绝缘层17A的厚度虽然根据要求的耐压,其厚度变化,但优选约50μm~数百μm左右。
第一导电图案18A由铜等金属构成,被构图在绝缘层17A表面。该第一导电图案18A和上层的第二导电图案18B电连接,主要具有使图案回绕设置的功能。
第二绝缘层17B在电路衬底16的表面形成,覆盖第一导电图案18A。而且,在第二绝缘层17B上贯通形成电连接第一导电图案18A和第二导电图案18B的连接部25。因此,为容易形成连接部25,在第二绝缘层17B中混入比第一绝缘层17A量少的填充物。另外,根据相同的理由,第二绝缘层17B中含有的填充物的平均粒径比第一绝缘层17A中含有的填充物的平均粒径小。
第二导电图案18B形成于第二绝缘层17B的表面。第二导电图案18B形成载置电路元件14的焊盘、连接该各焊盘的配线部、固定引线11的焊盘等。第二导电图案28B和第一导电图案18A可平面交叉地形成。因此,即使半导体元件14A具有多个电极时,也可以利用本申请的多层配线结构自如进行图案的环绕形成。
连接部25是贯通第二绝缘层17B,将第一导电图案18A和第二导电图案18B电连接的部位。
电路元件14固定于第二导电图案18B上,由电路元件14和导电图案18构成规定的电路。电路元件14采用晶体管、二极管等有源元件,或电容、电阻等无源元件。另外,功率类半导体元件等发热量大的元件也可以介由由金属构成的散热片固定在电路衬底16上。在此,利用面朝上接合法安装的有源元件等介由金属细线15和第二导电图案18B电连接。
半导体元件14A是在其表面具有数十~数百个焊盘的半导体元件。另外,也可以采用所谓的系统LSI作为半导体元件14A。在此,系统LSI有模拟运算电路、数字运算电路或存储部等,是以一个LSI实现系统功能的元件。因此,和现有的LSI相比,系统LSI伴随大量的发热而动作。
在半导体元件14A的背面和接地电位连接的情况下,半导体元件14A的背面利用焊料或导电膏等固定。另外,在半导体元件14A的背面浮置时,使用绝缘性粘接剂固定半导体元件14A的背面。另外,在半导体元件14A利用面朝下接合法安装时,介由由焊锡等构成的补片电极安装。
另外,可采用控制大电流的功率类晶体管、例如功率管理操作系统、GTBT、IGBT、半导体开关元件等作为半导体元件14A。也可以采用功率类IC作为半导体元件14A。近年来,由于芯片尺寸减小,且薄型、高功能化,故产生的热量增大。例如,控制电脑的CPU等是其一例。
引线11在电路衬底16的周边部固定在第二配线层18B上,例如具有和外部进行输入·输出的作用。在此,在一边设有多个引线11。引线11和图案的粘接介由焊锡等焊料19进行。
密封树脂12通过使用热硬性树脂的传递膜模制或使用热塑性树脂的注入膜模制形成。在此,密封电路衬底16及形成于其表面的电路形成密封树脂12,电路衬底16的背面从密封树脂12露出。另外,模制密封之外的密封方法也可以适用于本形态的混合集成电路装置,例如可使用树脂罐装进行的密封、壳体部件进行的密封等众所周知的密封方法。参照图1(B),为使从载置于电路衬底16表面的电路元件14产生的热顺畅地排出到外部,电路衬底16的背面从密封树脂12露出到外部。另外,为提高装置整体的耐湿性,也可以利用密封树脂12密封也含有电路衬底16背面的整体。
参照图1(C)的剖面图详细说明连接部25。该剖面图是放大连接部25及其附近的混合集成电路装置10的剖面图得到的图。连接部25是贯通绝缘层17使层积的导电图案相互导通的部位。另外,也可以使用连接部25作为用于进行配线层18相互的热接合的热通路(サ-マルビア)。
在本形态中,形成有由第一连接部25A及第二连接部25B构成的连接部25。第一连接部25A是从第一导电图案18A连续而沿厚度方向突出的部位。在此,第一连接部25A向上方突出,埋入第二绝缘层17B内。第二连接部25B是从第二导电图案18B连续而沿厚度方向突出的部位,在此,向下方突出,被埋入第二绝缘层17B中。
第一连接部25A是通过蚀刻加工沿厚度方向突出形成的部位,由以镀敷或轧制形成的Cu箔构成。另外,第一连接部25A也可以利用蚀刻加工之外的方法形成。具体地说,通过使电解镀敷膜或无电解镀敷膜在第一导电图案18A的表面凸状成膜,可形成第一连接部25A。另外,在第一导电图案18A的表面设置焊锡等焊料或银膏等导电性材料,也可以形成第一连接部25A。在本形态中,使第一连接部25A和第二连接部25B接触的区域位于第二绝缘层17B的厚度方向的中间部。因此,可提高两者接触的部分的连接可靠性。
参照图2的立体图说明形成于电路衬底16表面的第二导电图案18B的具体形状之一例。在同图中省略密封整体的树脂。
参照同图,第二导电图案18B构成安装电路元件14的接合焊盘的部分和固定引线11的焊盘26等。另外,在半导体元件14A的周边部形成多个引线接合金属细线15的焊盘。在载置有具有多个接合焊盘的半导体元件14A的情况下,在仅由第二导电图案18B构成的单层的图案上,由于配线密度有限,故有可能不能充分地环绕设置。在本形态中,通过在电路衬底16的表面构筑多层的配线结构,实现复杂的图案的回绕设置。
参照图3说明另一形态的混合集成电路装置的结构。图3(A)及图3(B)是另一形态的混合集成电路装置的剖面图。
参照图3(A),在此,贯通第二绝缘层17B形成热通路。热通路27是金属填充在贯通第二绝缘层17B的孔中的部位,是作为向外部排出热的经路起作用的部位。因此,热通路27也可以不导通。具体地说,热通路27与固定半导体元件14A的接合面状的第二导电图案18B的下面接触而形成。因此,即使从半导体元件14A产生大量的热时,其热也可以介由多个热通路27传导到电路衬底16上。此时的热的经路是半导体元件14A→第二导电图案18B→热通路27→第一绝缘层17A→电路衬底16→外部。
参照图3(B),在此,在第一绝缘层17A及第二绝缘层17B两者上设有热通路27。如上所述,含有大量填充物的第一绝缘层17A的散热性优良。因此,如同图所示,通过在第一绝缘层17A上设置热通路27,可进一步提高散热性。设于第一绝缘层17A上的热通路27也最好设于对应伴随发热的半导体元件14A下方的区域。
其次,参照图4详细说明填充于上述的绝缘层的填充物。图4(A)是表示各绝缘层中含有的填充物的量的图解,图4(B)是表示各层中含有的填充物的粒径分布的曲线。
参照图4(A)的图解,其纵轴表示填充物的重量填充率。在第一绝缘层17A中,向树脂中高填充填充物,填充物的填充率有时会达到80重量%。因此,第一绝缘层17A的导热率极大。具体地说,第一绝缘层17A的导热率例如为5W/m·K~10W/m·K。
与此相对,在第二绝缘层17B中,填充物的填充率比第一绝缘层17A的少。这是由于,在第二绝缘层17B中要穿设用于将导电图案18相互连接的连接部25。即,当在第二绝缘层17B中混入大量的填充物时,难于形成用于形成连接部25的孔。因此,第二绝缘层17B在可以使用于形成连接部25的操作性和散热性同时成立的范围内,决定填充物的填充率。
参照图4(B)说明填充于各绝缘层17中的填充物的粒径分布。该图所示的曲线的横轴表示填充物的粒径,纵轴表示该粒径的填充物占整体的比例。
第一绝缘层17A中含有的填充物的粒径分布曲线构成峰值为35μm程度的正态分布的分布形状。另外,由于粒径的分布的宽度宽,故在第一绝缘层17A中含有的填充物含有各种不同大小的粒子。因此,在大粒子的填充物相互的间隙中存在小径的填充物。因此,基于填充物的散热性飞跃性提高。在此,粒径分布的峰值在35μm附近,但也可以使该峰值移动。另外,也可以采用具有形成多个峰值这样的粒径分布的填充物。
第二绝缘层17B中含有的填充物的粒径分布曲线与上述的第一绝缘层17A中含有的填充物的分布曲线相比,向粒径小的一侧移动。即,第二绝缘层17B中含有的填充物的粒径比第一绝缘层17A中含有的填充物的小。详细地说,第二绝缘层17B中含有的填充物的平均粒径及最大粒径比第一绝缘层17A中含有的填充物的小。由于含有的填充物的量少,且其粒径小,从而容易使用激光等在第二绝缘层17B上形成通孔。其详细情况后述。
参照图5进一步说明再一形态的混合集成电路装置的结构。图5(A)及图5(B)是混合集成电路装置的剖面图。
参照图5(A),在此,通过介由绝缘层17层积导电图案18,构成四层配线结构。具体地说,在第一绝缘层17A上面形成第一导电图案18A。第二导电图案18B~第四导电图案18D介由第二绝缘层17B~第四绝缘层17D层积。这样,通过增加导电图案18的层数,可提高配线密度。为将各层相互的导电图案连接,在第二绝缘层17B~第四绝缘层17D上形成连接部25。因此,在第二绝缘层17B上层的绝缘层17上混入比第一绝缘层17A的量少的填充物。由此,容易形成连接部25。
参照图5(B),在此,在载置焊盘数多的半导体元件14A的区域的电路衬底16的表面形成多层配线结构,在固定电路元件14B的区域的电路衬底16的表面形成有单层的配线结构。
如上所述,半导体元件14A是具有数十~数百个电极的元件。因此,为回绕设置和半导体元件14A的电极连接的图案,在半导体元件14A的周边部形成多层配线结构。具体地说,形成由第一导电图案18A及第二导电图案18B构成的多层配线。
另外,多层形成的部分的第二导电图案18B和单层形成的部分的第一导电图案18A介由金属细线15电连接。
电路元件14B是例如功率类半导体元件,是伴随大量发热的开关元件。形成由第一导电图案18A构成的单层配线结构的部分的电路衬底16比其它区域的散热效果大。因此,如电路元件14B这样的发热量大的单个的晶体管最好直接固定在构成单层配线的第一导电图案18A上。
其次,参照图6及其以后的附图,说明上述的混合集成电路装置的制造方法。
首先,参照图6(A),介由第一绝缘膜17A在电路衬底16表面压装第一导电膜28A。该工序可通过在电路衬底16的表面涂敷第一绝缘层17A,然后,将第一导电膜28A粘贴在第一绝缘层17A上进行。另外,该工序也可以将背面设有第一绝缘层17A的第一导电膜28A粘贴在电路衬底16的表面来进行。电路衬底16的材料可采用以铜为主材料的材料或以Fe-Ni或Al为主材料的材料。为机械支承形成于表面的图案,电路衬底16的厚度在1~2mm程度的范围内选择。另外,在采用铜作为电路衬底16的材料时,由于铜是导热性极其优良的材料,故可提高散热效果。
其次,参照图6(B),通过构图第一导电膜28A,得到第一导电图案18A。该构图可通过使用蚀刻剂的湿式蚀刻进行。
其次,参照图6(C),覆盖第一导电图案18A涂敷第二绝缘层17B。在该第二绝缘层17B中混入与上述的第一绝缘层17A相比少量的填充物。因此,可进行抑制空隙产生的第二绝缘层17B的形成。第二绝缘层17B的形成可利用使用真空压力机粘贴片状树脂膜的方法进行。另外,涂敷液状的树脂也可以形成第二绝缘层17B。
其次,参照图16(D),在第二绝缘层17B的上面粘贴第二导电膜28B。在上述的说明中,是分别形成第二绝缘层17B和第二导电膜28B。但是,也可以将粘附于背面附着有第二绝缘层17B的第二导电膜28B覆盖第一导电图案18A而粘附。
其次,参照图7(A)~图7(C),形成将第一导电图案18A和第二导电膜28B电连接的连接部25。
参照图7(A),部分地除去形成连接部25的予定区域的第二导电膜28B,形成通孔27。该通孔27的形成可通过使用蚀刻掩模的湿式蚀刻进行。
参照图7(B),利用激光等除去方法除去从通孔27露出的部分的第二绝缘层17B。露出的第二绝缘层17B的除去可通过照射二氧化碳激光或激态复合物激光进行。通过本工序,在通孔27最下部露出第一导电图案18A的表面。
在利用激光除去第二绝缘层17B时,含有的填充物与树脂相比,难于利用激光进行除去。在含有的填充物的量多,且填充物的直径大时,更难于利用激光除去树脂层。因此,在本形态中,在第二绝缘层17B中含有较少量的直径小的填充物。因此,在本形态中,可利用激光进行第二绝缘层17B的除去。
参照图7(C),通过在含有通孔25的第二导电膜28B的表面形成导电膜,形成连接部25。该连接部25的形成通过电解镀敷、无电解镀敷或将无电解镀敷及电解镀敷两者组合使用的方法形成。作为具体的连接部25的形成方法,首先,利用无电解镀敷在至少含有通孔27的第二导电膜28B的整个面上形成厚度约2μm的金属膜(例如铜)。然后,进行电解镀敷,镀敷约20μm厚度的金属膜。由此,通孔27被埋入金属膜,形成连接部25。另外,当进行填充镀敷时,也可以选择地仅埋入通孔27。另外,镀膜可以采用Au、Ag、Pd等。也可以使用掩模进行局部镀敷。另外,在本工序中,图3所示的热通路也可以同时利用相同的方法形成。
然后,参照图7(D),构图第二导电膜28B,得到第二导电图案18B。利用上述工序形成和下层的第一导电图案18A电连接的第二导电图案18B。
之后,详细说明进行导电图案的形成后的工序。
参照图8(A),首先,介由焊锡或导电膏等将电路元件14固定在第二导电图案18B上。在此,在一张电路衬底16上形成多个构成一个混合集成电路装置的单元24。而且,各单元24可一并进行装片及引线接合。在此,是利用面朝上接合法安装半导体元件14A,但根据需要也可以利用面朝下接合法安装。在半导体元件14A的背面和外部导通时,可介由导电性的粘接剂进行半导体元件14A的固定。另外,在半导体元件14A的背面不和外部导通时,介由绝缘性粘接剂进行半导体元件14A的固定。
参照图8(B),介由金属细线15进行半导体元件14A和导电图案18的电连接。
在上述工序结束后,进行各单元24的分离。各单元的分离可利用使用压力机的冲切、切割、折曲等进行。然后,将引线11固定在各单元的电路衬底16上。
参照图9,进行各电路衬底16的树脂密封。在此,利用使用热硬性树脂的传递膜模制进行密封。即,在由上模型30A及下模型30B构成的模型30中收纳电路衬底16,然后,通过使两模型咬合,进行引线11的固定。然后,通过向模腔31中封入树脂,进行密封树脂的工序。利用以上的工序制造图1所示的混合集成电路装置。
近年来,伴随电子设备及家用电器制品的高功能化,在其中使用的半导体元件的集成度逐年增加,要求应付耗电量的增大。另外,为将这些设备小型化,强烈要求其搭载的半导体元件或电子部件小型·薄型化。
即,当考虑在混合集成电路衬底上高密度地安装了数量大的大规模LSI的装置时,与以前相比,更多地产生与热量相关联的问题。混合集成电路衬底的外形尺寸越小,该与热关联的问题越大。
本发明是用于解决这些的发明。目前的设想考虑将混合集成电路衬底例如金属衬底作为以提高散热性为目的的部件。但是,本申请考虑包括在其上形成的多层绝缘层构成用于散热的部件。因此,在本申请中,通过在绝缘层中混入填充物来实现。
但是,当在绝缘层中混入大量填充物时,出现了各种问题。如考虑导热性,则填充物的填充率越高越好。但是,当向树脂中大量混入粒径小的填充物时,存在其表面积增大,形成绝缘层时液状树脂形成高粘度的问题。即,当混入了填充物的液状树脂在衬底上滴下并扩散时,操作性会变得极其恶劣。
如混入粒径大的填充物,则树脂的粘性降低,可确保操作性。但是,在该大的填充物中,形成大量间隙,难于提高树脂的热传导。因此,在本申请中,增大填充物的粒径分布,在粒径大的填充物相互之间形成的间隙填充粒径小的填充物。
另一方面,在混合集成电路衬底上形成多层配线时,无论如何都需要通孔,在此为连接部25。但是,如加入填充物,则孔的加工性成为问题。
这是因为,由于填充物是由氧化铝、氧化硅膜等金属或半导体的氧化物等构成的填充物,故难于利用激光进行除去。另外,在通孔侧面出现露出的填充物,在通孔的内侧面形成凹凸。
因此,在本形态中,不需要通孔的最下层的绝缘层中混入大的填充物和填充于其间的小径的填充物,可实现高的导热率。但是,上层的绝缘层需要填充比最下层绝缘层的尺寸小的填充物。由此,可减少在树脂层上形成通孔时需要的激光的能量,而且,可减小通孔侧面的凹凸。如减小通孔侧面的凹凸,则形成于通孔内部的镀膜的成膜性也提高。
另外,需要利用比二氧化碳激光波长更短的激光进行开口。例如,通过采用YGA激光的第二高次谐波(532nm)、第三高次谐波(355nm)等,提高加工性。
以上,当在混合集成电路衬底上实现多层配线时,最下层的树脂层由于未设置通孔,故采用填充了粒径大的填充物和填充于其间的粒径小的填充物的绝缘层。另外,上层的绝缘层至少形成通孔的绝缘层中混入比填充于最下层绝缘层中的平均粒径小的尺寸的填充物,一次实现了散热性和通孔的加工性。
参照图10~图13说明另一形态的电路装置的制造方法。在上述说明中,在电路衬底16的表面形成多层导电图案,但在下述的形态中,在另外形成多层配线的片后,将该片层积于电路衬底16的表面。下面详细叙述这种制造方法。
首先,参照图10说明准备绝缘树脂片40的工序。
绝缘树脂片40是在绝缘树脂41的表面及背面整个面覆盖导电箔而形成的绝缘树脂片。另外,绝缘树脂41的材料是由聚酰亚胺树脂或环氧树脂等高分子构成的绝缘材料。另外,第一导电箔42及第二导电箔43最好是以Cu为主材料的材料或公知的引线架的材料。导电膜的厚度可为9μm~数百μm程度。
绝缘树脂41最好是聚酰亚胺树脂或环氧树脂等。在使用涂敷膏状物质构成片的模铸法时,其膜厚为10μm~100μm程度。另外,在考虑导热性时,向绝缘树脂41中混入填充物。混入绝缘树脂41中的填充物的量比形成于电路衬底16表面的第一绝缘层17A少即可。另外,也可以向绝缘树脂41中混入平均粒径比第一绝缘层小的填充物。由此,之后工序中的通孔形成变得容易。
参照图10(B)~10(D)说明介由连接部25电连接所述第一导电箔42和所述第二导电箔43的工序。
首先,参照图10(B),在第二导电箔43中,蚀刻形成通孔27的部分。由于第二导电箔43是以Cu为主材料的导电箔,故蚀刻液使用氯化铁或氯化铜,进行化学蚀刻。另外,在进行该蚀刻时,第一导电箔42利用粘接性的片等覆盖,以保护其不受蚀刻液侵蚀。但是,第一导电箔42本身非常厚,只要是在蚀刻后也可维持平坦性的膜厚,则少量被蚀刻也没关系。
参照图10(C),以第二导电箔43为掩模,利用激光除去通孔27正下方的绝缘树脂41,在通孔27的底部露出第一导电箔42的背面。在利用激光蒸发绝缘树脂后在开口部的底部存在残渣的情况下,利用过锰酸钠或过硫酸铵等进行湿式蚀刻,去除该残渣。
参照图10(D),在含有通孔27的第二导电箔43的整个面上形成进行第一导电箔42和第二导电箔43的电连接的连接部25即镀膜。该镀膜通过无电解镀敷或电解镀敷及将无电解镀敷和电解镀敷组合来形成。利用该镀膜形成连接部25。
其次,参照图10(E),通过对第一导电箔42及第二导电箔43构图,形成第一导电图案45及第二导电图案46。利用本工序,由第一导电图案45、第二导电图案46及绝缘树脂41形成配线片44。
参照图11(A)及图11(B),将配线片44压装在形成于电路衬底16表面的第一绝缘层17A上。在第一绝缘层17A中,考虑导热性,混入填充物。在此,在第一绝缘层17A中混入比绝缘树脂41中含有的填充物多量的填充物。另外,也可以混入平均粒径比绝缘树脂41中含有的填充物大的直径的填充物。而且,第一导电图案45埋入第一绝缘层17A中。在该密封利用真空加压进行时,可防止第一导电图案45和第一绝缘层17A之间的空气产生的空隙。另外,利用各向同性蚀刻形成的第一导电图案45的侧面构成圆滑的曲面。因此,在将第一导电图案45压入第一绝缘层17A时,使树脂沿该曲面浸入,会消除未填充部。另外,通过将第一导电图案45埋入第一绝缘层17A中,可提高第一导电图案45和第一绝缘层17A的粘附强度。
参照图12(A),介由焊锡或导电膏等将电路元件14固定在第二导电图案46(岛)上。在此,构成一个电路装置的单元24形成在一张电路衬底16上,可一并进行装片及引线接合。在此,利用面朝下接合法安装有源元件,但也可以根据需要安装。
参照图12(B),介由金属细线15进行半导体元件14和第二导电图案46的电连接。
在上述工序结束后,进行各单元24的分离。各单元的分离可通过使用冲压机的冲切、切割等进行。然后,将引线11固定在各单元的电路衬底16上。
参照图13,进行各电路衬底16的树脂密封。在此,通过使用热硬性树脂的传递膜模制进行密封。即,在由上模型30A及下模型30B构成的模型30中收纳电路衬底16,然后,通过将两模型咬合,进行引线11的固定。然后,通过向模腔31中封入树脂,进行树脂密封的工序。利用以上的工序制造电路装置。
Claims (10)
1.一种电路装置,其特征在于,包括:电路衬底;第一绝缘层,其形成于所述电路衬底表面;第一导电图案,其形成于所述第一绝缘层表面;第二绝缘层,其覆盖所述第一导电图案;第二导电图案,其介由所述第二绝缘层层积在所述第一导电图案上,在所述各绝缘层中填充填充物,在所述第一绝缘层中比所述第二绝缘层混入更多的所述填充物,并且,所述第一绝缘层包含的所述填充物的粒径分布比所述第二绝缘层包含的所述填充物的粒径分布宽。
2.一种电路装置,其特征在于,包括:电路衬底;第一绝缘层,其形成于所述电路衬底表面;第一导电图案,其形成于所述第一绝缘层表面;第二绝缘层,其覆盖所述第一导电图案;第二导电图案,其介由所述第二绝缘层层积在所述第一导电图案上,在所述各绝缘层中混入填充物,所述第一绝缘层中含有的所述填充物的平均粒径比所述第二绝缘层中含有的所述填充物的平均粒径大,并且,所述第一绝缘层包含的所述填充物的粒径分布比所述第二绝缘层包含的所述填充物的粒径分布宽。
3.如权利要求1或权利要求2所述的电路装置,其特征在于,设有贯通所述第二绝缘层的所希望的位置将所述第一导电图案和所述第二导电图案连接的连接部。
4.如权利要求1或权利要求2所述的电路装置,其特征在于,所述第一导电图案和所述第二导电图案平面交叉。
5.如权利要求1或权利要求2所述的电路装置,其特征在于,所述电路衬底由金属构成。
6.如权利要求1或权利要求2所述的电路装置,其特征在于,其具有和所述第二导电图案电连接的电路元件。
7.如权利要求6所述的电路装置,其特征在于,在固定所述电路元件的区域的下方设置将所述第二导电图案和所述第一导电图案热接合的热通路。
8.一种电路装置的制造方法,其特征在于,包括:准备电路衬底的工序;在所述电路衬底表面形成混入有填充物的第一绝缘层的工序;在所述第一绝缘层表面形成第一导电图案的工序;覆盖所述第一导电图案形成比所述第一绝缘层填充物的含有量少的第二绝缘层的工序;形成贯通所述第二绝缘层和所述第一导电图案电连接的第二导电图案的工序,并且,所述第一绝缘层包含的所述填充物的粒径分布比所述第二绝缘层包含的所述填充物的粒径分布宽。
9.一种电路装置的制造方法,其特征在于,包括:准备电路衬底的工序;在所述电路衬底表面形成混入有填充物的第一绝缘层的工序;在所述第一绝缘层表面形成第一导电图案的工序;覆盖所述第一导电图案形成含有的填充物的粒径比所述第一绝缘层的小的第二绝缘层的工序;形成贯通所述第二绝缘层和所述第一导电图案电连接的第二导电图案的工序,并且,所述第一绝缘层包含的所述填充物的粒径分布比所述第二绝缘层包含的所述填充物的粒径分布宽。
10.如权利要求8或权利要求9所述的电路装置的制造方法,其特征在于,通过照射激光,贯通所述第二绝缘层。
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US8643176B2 (en) * | 2011-07-27 | 2014-02-04 | Infineon Technologies Ag | Power semiconductor chip having two metal layers on one face |
US11437304B2 (en) | 2014-11-06 | 2022-09-06 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9408301B2 (en) | 2014-11-06 | 2016-08-02 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
US9397017B2 (en) | 2014-11-06 | 2016-07-19 | Semiconductor Components Industries, Llc | Substrate structures and methods of manufacture |
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JP2005347355A (ja) | 2005-12-15 |
KR20060049443A (ko) | 2006-05-19 |
TW200541125A (en) | 2005-12-16 |
US7221049B2 (en) | 2007-05-22 |
TWI301680B (en) | 2008-10-01 |
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