TWI301680B - Circuit device and manufacturing method thereof - Google Patents

Circuit device and manufacturing method thereof Download PDF

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Publication number
TWI301680B
TWI301680B TW94113212A TW94113212A TWI301680B TW I301680 B TWI301680 B TW I301680B TW 94113212 A TW94113212 A TW 94113212A TW 94113212 A TW94113212 A TW 94113212A TW I301680 B TWI301680 B TW I301680B
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Taiwan
Prior art keywords
insulating layer
conductive pattern
filler
circuit
conductive
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TW94113212A
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English (en)
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TW200541125A (en
Inventor
Yusuke Igarashi
Sadamichi Takakusaki
Hideki Mizuhara
Ryosuke Usui
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Sanyo Electric Co
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Application filed by Sanyo Electric Co filed Critical Sanyo Electric Co
Publication of TW200541125A publication Critical patent/TW200541125A/zh
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Publication of TWI301680B publication Critical patent/TWI301680B/zh

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
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Description

1301680 九、發明說明： 【發明所屬之技術領域】 本發明有關一種電路裝置及其製造方法，尤其是在恭 路基板表面形成多層導電圖案之電路裝置及其製造方法: 【先前技術】 ° 蒼照第14目！兄明習知混合積體電路裝置(例如參照專 利文獻1)。第14圖（A)為混合積體電路裝置之斜視圖 14圖（B)為第14圖（A)之χ-χ，線之剖面圖。 習知之混合積體電路裝置100係具有以下構成。混合 積體電路裝置遍係由以下構件構成：矩形基板⑽；絶' 緣層107 ,設於基板106之表面；導電圖案1〇8，形成於咳 絶緣層107上；電路元件1G4，固著於導電圖案⑽上；/ 金屬細線105,電性連接電路元件1〇4與導電圖案⑽：及 導線101 ’與導電圖案⑽電性連接。再者，混合積體電 路裝置1 00整體由封裝樹脂所封裝。
翅文獻 11 日本特開平6-177295號公報（第4 F 第1圖） ^ 【發明内容】 (發明所欲解決之課題） 么目刖’混合積體電路裝置已内建有高機能且高輸出之 $ 冼 LSI(；Urge scale integrati〇n，大型積體電路）等元 件。=匕，為β建腳端(ριη)極多之元件，需在裝 成更複隸之圖帛’且需確保高散熱性。但是如上述之混合 積妝毛路裝置100巾，因導電圖案1〇8為單層配線構造， 317009 1301680 難以使配線彼此交叉。為使導電圖案1〇8交叉，考慮採用 跨接線（jUmPerwire)之構成，但是，使用跨接線時，在此 跨接線部分有產生寄生電感之慮。再者，在電路基板1〇6 表面形成多層配線時，亦有減低裝置整體之散熱性之問題。 而且，考慮使用具多層配線之印刷基板作為電路基板 106時，會有因印刷基板之散熱性不佳而難以内建發熱較 夕之兀件的問題。此外’採用陶瓷基板時，有配線電阻變 大之問題。 本發明係針對上述問題而研創者。其目的為提供一種 具夕層配線構造且散熱性優異之電路裝置及其製造方法。 (解決課題之手段） …本七明之兒路裝置係具備：電路基板；第工絶緣層， =成方、上14 I路基板之表面；第丨導電圖案，形成於上述 第，色、彖層表面，第2絶緣層，覆蓋上述第」導電圖案； 2 2導電圖案’隔介上述第2絶緣層，疊層於上述第！ V电圖案上。上述各絶緣層均充填填充料，而於上述第1 上㈣緣層混入較上述第2上述絶緣層多量之上述填充 再者’、本發明之電路裂置係具備：電路基板；第η 於二：成於上述電路基板之表面；第1導電圖案，形/ 图安，絶緣層表面；第2絶緣層，覆蓋上述第1導1 .:、：；：弟2導電圖案’隔介上述第2絶緣層，疊層於_ 二:電圖案上。於上述各絶緣層混入填充料，而上i 色‘層所含之上述填充料之平均粒徑，係較上述第： 317009 6 1301680 之填充料。因此，可貫穿此絶緣層電性連 本彼此。再者，即使設有連接部之絶緣層所含之填充:: 平均粒徑，較其他絶緣層所含之填充料為小，; 形成連接部。 谷易地 【貫施方式】 於本形.態中，係以混合積體電路裝置為電 一 :列加以説明。參照第i圖説明本發明 ： io之構成。箆iFirA、盔、曰人士 價版包路裝置 弟1圖（A)為〜合積體電路裝置 弟1圖⑻為第！圖⑷之x_x，剖 ^視圖， 為連接部25附近之剖面的放大圖。°j面圖。弟1圖(〇 較佳電:基=?屬或陶究等所成之基板在散熱上 是了如用A12〇3、A1N。其他口 祕危 及散熱性佳者均可採用為電路基板16之材料 於本形態申，在由鋁所構成之恭 絶緣層Π，在絶緣層17 二:板16的表面形成 本形態中，電路基板16之材料/成¥琶圖案18。又，於 佳。由於銅為熱傳導性 散熱性。又，電料，因而可提高裝置整體之 «]Γ φ 土板6之材料如採用鋁時，亦可在雷路 基板16之表面形成氧化膜。 Τ丨了在电路 第1絶緣層1 7Α係以舜金a 式形成於其表面。第"路基板16之實質全域之方 (仙-)之樹腊。在此埴:⑺係可採用充填有填充料 化合物、鎵化合物、鎂化二料可採用例如鋁化合物、妈 、° ‘、或矽化合物。又，封裝樹 317009 8 1301680 脂12可為熱可塑性樹脂或熱硬化性樹脂均可。再者，第1 絶緣層m為提高裝置整體之散熱性，比其他絶緣層含有 更多量之填充料，其重量充填率例如約6{)%至8㈣左右。 再者，即使將直徑約別㈣以上之大徑之填充料混入於第 1絶緣層17A，亦可提高散熱性。第β緣層m之厚产， 、係按所需之㈣而改變厚度’大致在5一至數百^左 右為佳。 第1導電圖案18A為由銅等金屬所構成，目案 於絶緣層17A之表面。此第1導電圖t18A與上層之第t ‘電圖案18B電性連接，且具佈設圖案之機能。 第2絶緣層⑽以覆蓋第1導電圖案18A之方式形成 於電路基板16表面。而在第2絶緣層17B貫穿形成 25,其係使第1導電圖案⑽與第2導電圖案18β電性連p 接。因此，f 2絶緣層17B為了易於形成連接部25, 1絶緣層ΠΑ相較之下混入較少量之填充料。#者，基於 同樣之理由，帛2絶緣層17B所含之填充料之平均粒ς、， 係較^1絶緣層m所含之填充料之平均粒徑為小。 第2導電圖案18B係形成於第2絶緣層17B之表面。 再者f 2 圖帛18B係形成有裝設電路元件之輝墊 (Pad)、連接該各銲墊之配線部、固著線（1如⑴之 等。U導電圖案⑽與第」導電圖案m可形成為:平 面狀父又。1D此半導體元件14Α具多數個電極時，亦 本發明之多層配線構造自由進行圖案之佈設。 又 連接部25係貫穿第2絶緣層m，且將第ι導電圖宰 317009 9 1301680 1δΑ:第2_導電圖案ΐ8β電性連接之部位。 兒路兀件14係固著於第2導雷 件14與導電圖案18構成預定之電氣V卞路。兩上，由電路元 係採用命B 乂电路 笔路元件1 4 ^ 私日日脸及二極體等主動元件，盥電容哭；千 動元件。又，如功率系之半導雕_心屯合為及電阻等被 可藉由金屬f之料梦署门凡牛寺發熱量較大者，亦 朝上方式裝置：者於電路基板16。在此，以面 圖案⑽電性連接。兀件寺係經由金屬細線15與第2導電 :墊42元Γ:係在其表面具有數十個至數一 ’件UA。Γ 即’亦可採用系統⑶作為半導體元 曾、此’系統LSI係指具有類比運算電路、數位運 丨寺絲系統功旎在-個LSI元件上實現 的凡件。因此，與習知之LSI比軔，紅 之發熱而動作。 糸、，·先LSI會伴隨多量 癱丰者％半‘體兀件14A之背面與接地電位連接時， _版兀件14A背面由銲錫或導電塗漿等固著。此外，半 ㈣元件UA之背面為浮動時，則使用絶緣 半導體:件HA之背面。再者，半導體元件14A為= 下方式文裝呀，藉由銲料等構成之凸塊電極進行安裝。 再者，半導體元件14A可採用控制大電流之功率系泰 晶體，例如功率 MOSCMeta卜0xlde-Semiconductor，金屬' 氧化半導體）、GTBT(Grounded_Trench_M〇s Assisted B1 γ 1 anode FET，接地渠道金屬氧化半導體輔助雙載子 式場效電晶體）、IGBT(Insulated Gate Bip〇lai_ 317009 1301680
Transistor，絕緣閘雙載子電晶體）、閘流體（Thyrist〇r) 等。又，功率系1C亦適用。近年來，晶片尺寸小而薄而且 具南功能，因此所發生之熱會增加。例如用以控制電腦之 CPU等為其一例。 導線11在電路基板16之周邊部固著於第2導電圖案 18B，具有進行例如與外部之輸入/輸出的作用。在此，於
-邊設有多數個導線11。導線u與圖案之黏著係藉由焊 料之銲錫1 9等進行。 封裝樹脂12係藉由使用熱硬化樹脂之轉注模塑 (transfer molding) ’或使用熱可塑性樹脂之射出模塑 (叫灿加molding)所形成。在此，為了封裝電路基板 16及其表面形成之電路而形成封裝樹脂12，電路基板μ 自封裝樹脂12露出。再者，藉由模塑加 士 *抖:方ί亦可適用於本形態之混合積體電路裝置，例 口对脂之灌注（potting)封裝，遮護材之知封 f方法均可適用。參照第i圖⑻，為了使從1:::電之路封基 =表面之電路元件14所發生之熱適當地向外散出，恭 16之背面係從封裝樹脂12露出於外部。又，為； 问、置整體之耐濕性，亦可連同電路 ’'、、 封裝樹脂12整體封裝。 板16之月面’由 茶照第1圖（C)剖面圖，詳細説明連 圖為連接部25及其附近之混合積體二=面 :圖。連接部25為貫穿絕緣層並使所疊層裝之置導 導逋之部位。S，田 < 令兒圖案彼此 又，用以進行導電圖案18彼此之熱結合之熱 317009 11 1301680 通孔(:he:ila)亦可使用連接部25。 25ΒΠΓ態中’形成有由第1連接部25A及第2連接部 25B所構成之連接部 ： 案18A連續向厚产太b F25Ai自弟1導電圖 係向上方突出广。大之部位。在此’第1連接部25Α 係自第2導入於第2絶緣層17δ。第2連接部25Β :”、… 水18B連續向厚度方向突出之部位，在此， 弟2連接部25Β係向下方$屮，& Α 隹此 楚〗、查拉Α 下方大出而埋入於第2絶緣層17Β。 弟1連接。Ρ 25Α係由蝕刻加工朝向；^h办& 成之部位，是由「 朝向；度方向突出而形 …與軋壓所成之鋼落所成。又，第1連 亦可由钕刻加工以外之方法形成。具體而言，藉 二或無電解電鍍膜，在第1導電圖案18Α之 為凸狀，而可形成第1連接部25Α。再者，夢由 將銲料等之銲錫或銀㈣等 錯由 圖案m之表面，亦可形成第丨連接部25α。於本形 使第1連接部25Α與第2連接部挪所接觸之領域，心位於 弟2絶緣層17Β之厚度方向之中間 此 接觸部分之連接可靠性。 了袪同雙方 參照第2圖之斜視圖’説明形成於電路基板16表面之 第2導電圖請之具體形狀之-例。圖示為二ί 體之樹脂部分。 了衣 爹知、第2圖’第2導電圖案j 8β係構成安裝有電路元 件14之接合銲墊部分，與固著有導線η之銲墊26等。又， 於半導體元件UA周邊部，形成有多數個線接合金属細線 is之輝墊。當載置具有多數個接合銲墊之半導體元件ΐ4Α 317009 ]2 1301680 時’僅由第2導電圖案18B所構成之單層圖案，因配線穷 度受限而有無法充分佈設之虞。但是，於本形態中，在: 路基板16表面構築多層之配線構造，得以實現複雜圖案I 佈設。 ’' 、夢照第3圖説明其他方式之混合積體電路裝置1〇之 ^。第3圖⑴及第3圖⑴為其他形態之混合積體 裝置之剖面圖。 蝰思參？第3圖(A):在此，形成熱通孔27以貫穿第2絶 '’曰Π。熱通孔27為在貫穿第2絶緣層17β之孔充填金 屬之部位’是具有將熱向外部傳導之，路徑功能的部位二、因 此，熱通孔27無需導通。具體而言，熱通孔27係以接觸 固著有半導體元件14A之島狀之第2導電圖帛18β下面之 方式形成。因此，當半導體元件14A發生大量的埶時，也 能經過複數個熱通孔27,將其熱傳導至電路基板16。此日士 熱之路徑為半導體元件14^第2導電圖案ΐ8β 一埶通孔’ 27-第1絶緣層17A—電路基板16—外部。 參照第3圖（B)，在此，在第丨絶緣層m及第2绝 緣層17B之雙方設置熱通孔27。如上·，含大量填充料 弟1、’色緣層17A的散熱性佳。因此，如該圖所示，藉由 第1，’色4：層17A s又置熱通孔2 7，而使散熱性更力σ提高。 。又於乐1絶緣層17Α之熱通孔27,最好設置在對應伴隨發 熱之半導體元件14Α下方的區域。 ^
接著，參照第4圖詳細説明充填於如上所述之絶緣層 之填充料。第4圖(Α)為包含於絶緣層之填充料量之曲線S 317009 13 1301680 第2絶緣層17B所含之填充料之粒經分佈曲線，盘上 述第1絶緣層17A所含之填充料之分佈曲線，均向粒經較 」、者移位。亦即，包含於第2絶緣層ΠΒ之填充料粒經俜 較包含於第丨絶緣層ΠΑ之填充料粒徑為小。詳十之，勺、 含於第2絶緣層17B之填充料之平均粒徑及最大粒徑，： 較包含於第"色緣層17A之填充料粒徑為小。由之 填充料量少且其粒徑小，因而極為容易利用雷射等在第2 絶緣層17B形成貫穿孔時。容後詳述。 第5=第另一形態之混合積體電路裝置構造。 :)與第5圖⑻為混合積體電路裝置之剖面圖。 安參照第5圖（A)’在此，係隔介絶緣層17疊層導電圖 案二，而構成4層之配線構造。具體而言，在第」絶緣層 上面形成第1導電圖案18A。接著，自第2導電圖荦 權至第4導電圖請，係從第，絶緣請隔介第！ :色緣層m而疊層。如此藉由增加導電圖案ΐδ之層數，可 17B^f 17Dj ^ 成=以連接各層彼此間之導電圖案的連接部 比第2絶緣層17B更上層之絶 ^ 在 17A ^ ^ ^ ^ , 豕層17’混入較第1絶緣層 广之真充料。由此形成連接部25較為容易。 广照f 5圖⑻，在&，在裝設有銲墊較多之半導體元 ^ 域之電路基板16表面形成多層之配線構造，而 在固者有龟路元件14β之區域 之配線構造。 -路基板16表面形成單層 半導體元件…為如上述具數十至數百個電極之元 3]7009 】5 1301680 件1因此，為了佈設與半導體元件14A之電極連接之圖氕， =半導體元件14A周邊部形成多層之配線構造^具體:’ 言，形成有由第丄導電圖案1δΑ及第2導電圖案^ 之多層配線。 m珉 =’形成為多層之部分之第2導電圖案18B，與形成 部分之第1導電圖案18A，係經由金屬細線15電 量發例如為功率系半導體元件，且為伴隨大 :之開關凡件。形成有由第！導電圖案i8a所 線構造之部分的電路基板16,與其他區域相較之下 -則散熱效果較大。因此 W目#乂之下’ 離式⑻SCrete)電^ ==14B般發熱量較大之分 •第1導電圖案181。曰曰肢 接固著於構成單層配線之 方法接f ’參照第6圖説明上述混合積體電路裝置之製造 • 首先參照第6圖（A)，隔介第】綠綠 16表面壓接第2 弟〗、.，色、，，彖版17A在電路基板
塗布於電路& ^ 驟可在將第1絶緣層17A 於第1絶緣層m來進行。再:由㈣1導電膜2δΑ貼合 面設有第1絶緣層m之第i導電亦可進行將在背 板16之表面。電路基板16 =、 &貼合於電路基 採用Fe-Ni或紹 心、以銅為主材料，亦可 圖案，電路基板支擇在表面所形成之 擇。如採用鋼為電路基板又 16之材:_左右之範'内選 料I ’因銅為熱傳導性極 317009 16 1301680 佳之材料，故可提高散熱效果。 接著，參照第6圖⑻將第」導電膜m圖案化 到弟1導電圖案】8A。此圖案化步赞，茲 于 之濕式㈣來進行。 可精由使用钱刻劑 接著，參照第6圖⑹，塗布第2絶緣層n 弟二電圖請。於此第2絶緣層17B·^ 、:=較少量的填充料。由此可形成抑制間隙發生㈣^ :薄：第2絶緣層17B之形成，可藉由真空沖壓貼 形成第2絶緣層谓。 外精由塗布液状樹脂亦可 1 =照第6_’在第2絶緣層17β上面貼合第 於上述説明中’係分別形成第」絶緣層ΐ7β 電膜則。但是，亦能夠以覆蓋第丨導電圖案ΐ8Α 咖。“著將第2絶緣層17Β附著於背面之第2導電膜 =，參照第7圖⑴至第7圖(C)，形成用以電性連 ▲ V電圖案18Α與第2導電膜28β之連接部巧。 2導電膜：7，Α)，將形成有連接部25之預定區域之第 可夢由祐局部去除而形成貫穿孔27。形成此貫穿孔27 』糟由使用蝕刻遮罩之濕蝕刻來進行。 27/中照第7圖⑻’以雷射等去除方法，去除自貫穿孔 出:八之部分的第2絶緣層17Β。絲第2絶緣層m露 1 a3、’可照射二氧化碳雷射或激生分子雷射（exc 1 mer 1進行。藉由本步驟，在貫穿孔27之最下部露出第！ 3]7009 ]7 13〇168〇 導電圖案18A之表面。 大時，利用:射去=除。含有填充料量多且填充料粒經 在第9 田射去除树脂層愈加困難。因此於本形能中， 在弟2絶緣層17B合右龄 4〜心中， 於本形能中1 ”！粒徑較小之填充料。因此， ▲、 可以利用雷射去除第2絶緣層πβ。 之表：=，，包含貫穿孔27而在第2導電勒 採用二此形成連接部25。此連接部25可 鑛之方法=成:，f或組合無電解電鑛及電解電 無電解電㈣tV；的連接部25之形成方法為，首先以 包含貫穿孔二二=:列_^^ 鐘，對約20_度之全;=之二面。繼之進行電解電 金屬版進仃電鑛。由此，貫穿利97 ^用金“以，㈣錢接部25。⑽；;孔2 财可選擇性地僅埋人貫？孔27。又，電賴亦可= U :Ag ' Pdj Q亦可使用遮罩進行部分電鑛。再者，於本 A t ’如第3圖所示’以相同方法同時形成熱通孔亦可。 參照第7圖⑻’圖案化第2導電膜 第2導電圖案18B。由上述步驟，形成與下層之第i導電于 圖案18A電性連接之第2導電圖案18B。 以下詳細説明形成導電圖案後之步驟。 蒼/、第8圖（A) ’藉由銲料及導電塗漿等將電路元件 14固著於第2導電圖牵〗只。六& 4妓jl 卞18在此，構成一個混合積體電路 裝且之早兀24，複數個形成於一片電路基板16。於是，各 317009 18 1301680 ^兀24可總括進行晶粒接合（die b〇nding)及引線接合 (二。在此，將半導體元件UA以面朝上方式 m是視需要亦可面朝下。半導體元件i4a之背面如 人外部w時，可利料電性黏著_著半導 14An#體元件14A之背面與外部不導通時^ 絶緣性黏著劑固著半導體元件14a。 、】和用 1參照第8圖⑻藉由金屬細線15電性 14A與導電圖案μ。 干V奴兀件 、在結束上述步驟後，進行各單元24之分離。各單元之 - 在各早兀之電路基板16固著導線1〗。 參照第9圖進行久雷说|4 Ί •获也 基板16之樹脂封裝。在此，俜 猎由使用熱硬化性樹脂之轉注行 " 混合積體電路裳置。 ^錢弟1圖所不之 此等：二:之：者電子機器及家庭電氣製品之高性能化， 此寻所知用之半導體元丰 電力增大之對增大，極需謀求消耗 、 再者，由於此等機器之小型化，所穸恭 +導體元件及電子零件，亦極需小型化、薄型化。 電路I:之::諸多大_LSi以高密度安農於混合積體 體電路基板之：形=:有更多有關發熱之問題。混合積 ^寸愚小，則有關發熱之問題愈大。 317009 19 1301680 人積為解決此等問題之手段。以往之想法係將混 。、版包路基板，例如視金屬基板為提 ::=)。但是，本發明則包含在其 但是，將大量填充料混人絶緣層時，會發生種種問題。 ^慮職傳導性時，填域之充填率愈高騎佳。但是將 .护錢ί料As/昆人樹脂時’其表面積會擴大，而在 袭層日寸之液狀樹脂會有黏度增大之問豸。亦即，將 料之液編滴下在基板上而擴散時，作業性會 作聿：入:粒,大之填充料時’樹脂之黏性會降低而可確保 :=。但疋此等較大填充料，會形成很多間隙，而難以 徑熱傳導。因此’於本發明中，係使填充料之粒 在大粒徑之填充料彼此間形成之間隙，埴 齡小粒徑之填充料。 八 另一方面，在混合積體電路基板上形成多層配線時， ^員要有貫穿孔’在此即為連接部25。但是混入填充料 恰，孔之加工性會成為問題。 /此係因填充料為由氧化銘、石夕氧化膜等之金屬及半導 脰之氧化物所成者之故’難以用雷射加以去除。且，露出 於貫穿孔側面之填充料剝離’貫穿孔内側面會形成凹凸。 因此，於本形態中，在最下層無需貫穿孔之絶緣層， 混入較大填充料與充填在其間之小徑填充料，而實現高熱 317009 20 1301680 傳導率。但是，上層之絶緣層需要填充較最下層之絶緣層 較小尺寸之填充料。由此，在樹脂層形成貫穿孔時所需之 雷射能量可較小，且使貫穿孔側面之凹凸較小。貫穿二側 面之凹隨小時’形成於貫穿孔内部之電鑛膜之成膜性亦 會提高。 又，雷射亦需要使用較二氧化碳雷射更短波長之雷射 ㈣成開Π。例如採用YAG雷射之第2高頻（532_、第3 南頻（3 5 5 run)寺’則加工性更佳。 如上所述，在混合積體電路基板上進行多層配線時， 因最下層之樹脂層未設貫穿孔，故可採用充填有大 填充料與充填在其間之粒徑小之填充料的絕緣^ 4 層之絶緣層及形成至少貫穿孔之絶緣層，係混 於最下層之絶緣層之平均粒徑更小尺寸之填充料乂此可 一次解決散熱性與貫穿孔加工之問題。 " •、蒼照第10圖至第13圖，説明其他形態之步夕 製造方法。於上述説明中係在電路基 ,广 導電圖宰，作在下、f y〜由, 、面开> 成多層之 α木仁在下述形怨中，係另形成多声 將此薄片疊層於電路基板16表面^二 '後’ 绝绫二二 明準備絶緣樹脂薄片40之步驟。 名細曰湾片40係將絶緣樹脂4 … 由導電络覆蓋所形紅絶緣樹脂 :表面及月面 脂或環氧樹脂等高分子樹脂所構成之=由聚酿亞胺樹 ^电伯42及第2導電结43最好 弟1 之導線架材料。導電膜之厚 =為主材料’或公知 y " m至數百// m左右即可。 3]7009 21 13〇1680 、冷將=樹脂41為聚嶋樹脂或環氧樹脂等為佳。涂上 !〇〇 r/i#ii(CaSting)^8' 5 10 卜入谊/ 又考慮熱傳導性時，在絶緣樹脂 此入填充料。絕緣樹脂41中所混入 電路基板16表面之W絶緣層m更少旦充;^較形成於 ?混入較第1絶緣層之平均粒徑小之填充料亦可在絶緣 立，易於形成後續步驟之貫穿孔。 /、 V /、° 。由 多"月?、弟 1 〇 圖（i 1 n g γ n、 電性連接上述W導電ί:，藉由連接部25 首先參述第2導電落43之步驟。 …、、、弟1 0圖（Β)，於第2導 貫穿孔27之部分。第2 =中，钱刻形成 .㈣液為使用氯化鐵或氯化銅進行主材料，因此 刻時，第1導電落42係由勘著性薄片j。又’在此钱 液影響。但是如第】導電荡42 设盍以免受到蝕刻 —亦能維持平坦性之 电:身有充分厚度，在蝕刻後 =，27正下方之絶緣樹二在 出弟1導電箔42之背面。 朴在貝牙孔27底部露 部之底部有殘渣時，則以古田射瘵發絶緣樹脂後，在開口 刻，以去除此殘渣。 ㊁·久鈉或過硫酸銨等進行濕蝕 參照第10圖⑻，在包含 之全面，形成用以電性連，、牙27之第2導電箔43 43之連接部25之電鍍膜。導電箔42與第2導電落 免鍍，及無電解電鍍鍍膜為無電解電鍍或電解 …電鍍組合所形成。藉由此電鍍 317009 22 1301680 膜形成連接部2 5。 斤接著，麥照第10圖（E)，藉由圖案化第}導電窄 與第2導電箔43， 形 J ‘ 安 士 ㈣成乐1 ^圖案45與第2導電圖 " 、、本步驟中，由第1導電圖案45、第2導恭圖安 46與絶緣樹脂41形成配線薄片44。、 包1"木 蒼照第11圖（A)及第11圖（β)，蔣蜱鵁 形成在恭敗υ , 口…）將配線潯片44壓接於 办成在包路基板16表面之笫 層心难、.. 緣層17Α。對於第1絶緣 绝緣朽“ 混入有填充料。在此，將較 絶緣樹脂41所含之埴奋斗斗# θ 層17A。又：枓更大！的填充料混入於第1絶緣 亦可混入較絶緣樹脂41所含之填充料平均： 仏大之填充料。於是，第1導命罔垒Κ〆 17Α。此宓芸士古 电圖案45係埋入第1絶緣層 此山者如以真空沖壓進行，則 45與第1絶緣層17Α之間的而# 弟1 V电圖案 蝕刻所形成之第！導電圖案45之 隙而由寺向性 ^ I m ^ AC Γ 1面係為平滑之曲面。因 盯牙V i ¥包圖案45壓入第Γ >面浸入，而π八士 4 弟丄、，，色、、袭層ΡΑ時，樹脂沿此曲 埋入第= 部分。再者，因第1導電圖案45 弟1、、色緣層17Α，故可提高第！導带安 緣層17Α之密著強度。 电圖木45與弟1絶 麥照第12圖（a )，藉由銲料及導+ 一 14固著於第2導電圖案46(島部’ ‘二，電路元件 個電路裝置之單元24係形成 ：)二此，構成！ ;隹t s 1 t θ兒路基板16 ’可細i壬 進仃晶粒接合及引線接合。在 >括 安Fθ、目兩π 、主動元件以面朝上方式 疋視而要以面朝下方式安裝亦可。 +照第12圖（Β)，藉由金屬細崎 、淥3 5電性連接半導體元 317009 23 1301680 件14與第2導電圖案46。 結束上述步驟後，進行各單元24之分離。各單元之分 雜可藉由使用沖壓機之沖切、切割等進行。隨後在各單元 之電路基板16固著導線u。 —參照第μ圖，進行各電路基板16之樹脂封裝。在此， 稭由使用熱硬化樹脂之轉注塑模進行封裝。亦即，在上模 具30A與下模具3〇B所成之模具3〇收容電路基板a後， 具：固定導線丨1。於是將樹脂封入腔3卜而完成 ，封裝之步驟。藉由以上步驟完成電路裳置之製造。 【圖式簡單説明】 第1圖係本發明之混合積體雷 面圖⑻、剖面圖(c)。積一破置之斜視圖(A)、剖 第2圖係本發明之混合積體電 第3圖係本發明之、、θ入并一 t斜視圖 面圖⑻。Λ月之一體電路裝置之剖面圖⑴、剖 弟4圖係適用於本發明、e人 特性之特性Pim杜 此5積粗電路裝置之填充料 了丨王惑％胜圖（A)、待性圖（β)。 第5圖係本發明之混合積體 面圖（β)。 、電路裝置之剖面圖（Α)、剖 第6圖係説明本發明之混人 之剖面圖（Α)至（D)。 口貝肢黾路裝置之裳造方法 第7圖係説明本發明之混合 之剖面圖（Α)至（D)。 口貝肢电路裝置之製造方法 明之混合積體 弟8圖係説明本發 電路裝置之製造方法 317009 24 1301680 之剖面圖（A)、剖面圖（B)。 製造方法 第9圖係説明本發明之混合積體電路裝置之 之剖面圖。 、 弟10圖係説明本發明之混仓^ ^ 知體電路裝置之製造方 法之剖面圖（A)至（E) 〇 第11圖係制本發明之混合㈣電料置 方 法之剖面圖（A)、剖面圖（B)。 "
積體電路裝置之製造方 積體電路裝置之製造方 弟12圖係説明本發明之混合 法之剖面圖（A)、剖面圖（β)。 弟13圖係説明本發明之現人 法之剖面圖。 第14圖係習知混合積體 ® ( Β) 〇 電路裝置之斜視圖（A)、剎面 10
主要元件符號說明】 混合積體電路裝置 封裝樹脂 11 導線 14A 16 半導體元件 電路基板 17B 第2絶緣層 17D 第4絶緣層 第2導電圖案 18D 第4導電圖案 24 單元 14 15 17A 17C 18A 18C 19 電路元件 金屬細線 第1絶緣層 第3絶緣層 第1導電圖案 第3導電圖案 銲锡 ΜΑ 第1連接部
25 25B 連接部 第2連接部 317009 25 1301680 26 銲墊 27 貫穿孔（熱通孔） 27A 熱通道 27B 熱通道 28A 第1導電膜 28B 第2導電膜 30 模具 30A 上模具 30B 下模具 31 腔 40 絶緣樹脂薄片 41 絶緣樹脂 42 第1導電箔 43 第2導電箔 44 配線薄片 45 第1導電圖案 46 第2導電圖案 100 混合積體電路裝置 101 導線 102 封裝樹脂 104 電路元件 105 金屬細線 106 基板 107 絶緣層 108 導電圖案 26 317009

Claims (1)

  1. i1301680十、申請專利範圍：
    %修(更)正替换頁 第941132辺號專利申請案 (97年4月29曰） .一種電路裝置，係具備：由金屬構成的電路基板；第1 絶緣層，形成於上述電路基板之表面；第丨導電圖案， 形成於上述第！絶緣層之表面；第2絶緣層，m 述第1導電圖案；及第2導電圖案，隔介上述絶 緣層，疊層於上述第1導電圖案之上， 於上述各絶緣層充填填充料， 而於上述第1絶緣層混入較上述第2絶緣層更大量 之上述填充料， 2. ^上述第1絕緣層所含之上述填充料的平均粒徑， 係較上述第2絕緣層所含之上述填充料的平均粒徑大。 -種電路裝置，係具# :由金屬構成的電路基板；第] 絶緣層，形成於上述電路基板之表面；第i導電圖案， 形^於上述第1絶緣層之表面；第2絶緣層，覆蓋上 述第1導電圖案’'及第2導電圖案’隔介上述第2絶 緣層，疊層於上述第〗導電圖案之上， 於上述各絶緣層混入填充料， 而上述第1絶緣層所含之上述填充料之平均粒 徑’係較上述第2絶緣層所含之上述填充料之平均 徑為大， /上述第1絕緣層所含之上述填充料的粒徑分布， 係比上述第2絕緣層所含之上述填充料的粒徑分布廣。 3.如申請專利範㈣！或2項之電路裝置，其中，裝二 有貫穿上述第2絶緣層之所希望部位，而連接上述第1 (修正本）317009 k 1301680 第94113212號專利申請案 導電圖案與上述第2導電圖案的連接部。（年$ 29曰） ,4.如申請專利範圍第2或2項之電路裝置，里中， .第1導電圖案與上述第2導電圖案為平㈣叉。 5. 如申請專利範圍第1或2項之 電路基板為由金屬所成。 衣，八，上述 6. 如申請專利範圍第1或2項之電路襄置，其中，且備 與上述第2導電圖案電性連接之電路元件。 7. Μ請專利範㈣6項之電路裝置，其中，其係在固 者有上述電路元件之領域下方褒置用以將上述第2導 電圖案與上述第1導電圖案作熱結合之熱通孔。 8. —種電路裝置之製造方法，係包括： 準備電路基板之步驟； 在上述電路基板之表面形成混入有填充料之们 絶緣層之步驟； 在上述第1絶緣層之表面形成第丨導電圖宰之 • 驟； ^覆蓋上述第1導電圖案之方、式形成填充料之含 有1較上述第1絶緣層少之第2絶緣層之步驟；及 形成貫穿上述第2絶緣層而與上述第丨導電圖案電 性連接之第2導電圖案之步驟。 9· 一種電路裝置之製造方法，係包括、 準備電路基板之步驟； 在上述電路基板表面，形成混入有填充料之第工 絶緣層之步驟； (修正本）317009 28 1301680 第94113212號專利申讀 在上述第1絶緣層之表面形成第年4月29曰 驟； /成罘】導電圖案之步 以覆蓋上述第1導雷R安4 ‘丄、 料之粒徑較上述第1絶緣層為小之;之填充 驟，·及 罘2、、'色緣層之步 10. 案電而與上 逆摆之弟2導電圖案之步驟。 ί中m圍第8或9項之_置之製造方法， 猎由照射雷射來貫穿上述第2絶緣層。 (修正本）317009 29
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