JP4383258B2 - 回路装置の製造方法 - Google Patents
回路装置の製造方法 Download PDFInfo
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- JP4383258B2 JP4383258B2 JP2004162656A JP2004162656A JP4383258B2 JP 4383258 B2 JP4383258 B2 JP 4383258B2 JP 2004162656 A JP2004162656 A JP 2004162656A JP 2004162656 A JP2004162656 A JP 2004162656A JP 4383258 B2 JP4383258 B2 JP 4383258B2
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- Prior art keywords
- hole
- film
- wiring layer
- conductive film
- circuit device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本形態では、回路装置の一例として図1等に示すような混成集積回路装置を例に説明を行う。しかしながら下記する本形態は、他の種類の回路装置にも適用可能である。
本形態では、回路装置の一例として混成集積回路装置を例に製造方法の説明を行う。しかしながら、下記する本形態の製造方法は、他の種類の回路装置の製造方法にも適用可能である。
11 リード
12 封止樹脂
14 回路素子
15 金属細線
16 回路基板
17A〜17D 絶縁層
17B1 第1の樹脂膜
17B2 第2の樹脂膜
18A〜18D 配線層
19 ロウ材
24 ユニット
25A、25B 接続部
26 パッド
27 サーマルビア
28A、28B 導電膜
29A〜29E レジスト
30 貫通孔
31 キャビティ
32 貫通孔
33 レーザー
34 メッキ膜
Claims (9)
- 回路基板の表面に、第1の配線層の厚みと第1の接続部の高さとを加算した厚さ以上の第1の導電膜を形成する工程と、
前記第1の導電膜をエッチングすることにより、前記第1の配線層と、前記第1の配線層の厚み方向に突出し、前記第1の配線層と同じ材料で前記第1の配線層と連続した前記第1の接続部とを形成する工程と、
フィラーを含む絶縁層を介して前記第1の配線層に第2の導電膜を積層させる工程と、
前記第1の接続部が形成された領域に対応する前記第2の導電膜を部分的に除去する工程と、
前記第1の接続部が埋め込まれることで薄く形成された領域の前記絶縁層を除去して貫通孔を形成し、前記貫通孔の下面に前記第1の接続部の上面を露出させる工程と、
前記貫通孔に第2の接続部を形成することで、前記第2の導電膜と前記第1の配線層とを導通させる工程と、
前記第2の導電膜をパターニングすることにより、第2の配線層を形成する工程とを具備することを特徴とする回路装置の製造方法。 - 前記絶縁層は、フィラーを含む第1の樹脂膜と、前記第1の樹脂層の上面を被覆して前記第1の樹脂膜よりも前記フィラーの含有量が少ない第2の樹脂膜とから成り、
前記第1の接続部の上方に位置する前記第2の樹脂膜を除去することにより前記貫通孔を形成することを特徴とする請求項1記載の回路装置の製造方法。 - 前記第2の樹脂膜には、前記フィラーが含まれないことを特徴とする請求項2記載の回路装置の製造方法。
- 前記貫通孔の形成は、部分的に前記第2の導電膜を除去して前記絶縁層を露出させ、露出した前記絶縁層にレーザーを照射して除去することにより行うことを特徴とする請求項1記載の回路装置の製造方法。
- 無電解メッキ処理により前記貫通孔の側壁にメッキ膜を形成した後に、電解メッキ処理を行い、新たなメッキ膜を前記貫通孔に形成することで、前記第1の配線層と前記第2の導電膜とを導通させることを特徴とする請求項1記載の回路装置の製造方法。
- 前記第2の導電膜を電極として用いた電解メッキ処理を行うことで、前記貫通孔の周辺部に位置する前記第2の導電膜から前記貫通孔の内側に向けてメッキ膜を形成し、前記メッキ膜により前記第1の配線層と前記第2の導電膜とを導通させることを特徴とする請求項1記載の回路装置の製造方法。
- 前記第2の導電膜から成るひさしを前記貫通孔の周辺部に形成し、
前記ひさしから前記貫通孔の内側に向けてメッキ膜を形成することを特徴とする請求項6記載の回路装置の製造方法。 - 前記第1の配線層を電極として用いた電解メッキ処理を行うことで、前記貫通孔の下部に露出する前記第1の配線層から前記貫通孔の内側に向けてメッキ膜を形成し、前記メッキ膜により前記第1の配線層と前記第2の導電膜とを導通させることを特徴とする請求項1記載の回路装置の製造方法。
- 前記メッキ膜を形成する前に、前記貫通孔の側壁に前記メッキ膜とは異なる金属を付着させることを特徴とする請求項5から請求項8のいずれかに記載の回路装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004162656A JP4383258B2 (ja) | 2004-05-31 | 2004-05-31 | 回路装置の製造方法 |
US11/138,932 US7565738B2 (en) | 2004-05-31 | 2005-05-25 | Method for manufacturing circuit device |
US12/352,372 US7854062B2 (en) | 2004-05-31 | 2009-01-12 | Method for manufacturing circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004162656A JP4383258B2 (ja) | 2004-05-31 | 2004-05-31 | 回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005347357A JP2005347357A (ja) | 2005-12-15 |
JP4383258B2 true JP4383258B2 (ja) | 2009-12-16 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004162656A Expired - Fee Related JP4383258B2 (ja) | 2004-05-31 | 2004-05-31 | 回路装置の製造方法 |
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JP (1) | JP4383258B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2014143276A (ja) * | 2013-01-23 | 2014-08-07 | Sumitomo Electric Ind Ltd | 半導体装置 |
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2004
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