CN100576462C - 减小厚绝缘体层的粗糙度的方法 - Google Patents
减小厚绝缘体层的粗糙度的方法 Download PDFInfo
- Publication number
- CN100576462C CN100576462C CN200680030390A CN200680030390A CN100576462C CN 100576462 C CN100576462 C CN 100576462C CN 200680030390 A CN200680030390 A CN 200680030390A CN 200680030390 A CN200680030390 A CN 200680030390A CN 100576462 C CN100576462 C CN 100576462C
- Authority
- CN
- China
- Prior art keywords
- insulator layer
- plasma
- substrate
- layer
- roughness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/06—Planarisation of inorganic insulating materials
- H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
- H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Formation Of Insulating Films (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Magnetic Heads (AREA)
- Element Separation (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0507573A FR2888663B1 (fr) | 2005-07-13 | 2005-07-13 | Procede de diminution de la rugosite d'une couche epaisse d'isolant |
| FR05/07573 | 2005-07-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101243545A CN101243545A (zh) | 2008-08-13 |
| CN100576462C true CN100576462C (zh) | 2009-12-30 |
Family
ID=36090950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200680030390A Active CN100576462C (zh) | 2005-07-13 | 2006-07-12 | 减小厚绝缘体层的粗糙度的方法 |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US7446019B2 (https=) |
| EP (1) | EP1902463B1 (https=) |
| JP (1) | JP4927080B2 (https=) |
| KR (1) | KR100958467B1 (https=) |
| CN (1) | CN100576462C (https=) |
| AT (1) | ATE524828T1 (https=) |
| FR (1) | FR2888663B1 (https=) |
| SG (1) | SG151287A1 (https=) |
| WO (1) | WO2007006803A1 (https=) |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7115530B2 (en) * | 2003-12-03 | 2006-10-03 | Texas Instruments Incorporated | Top surface roughness reduction of high-k dielectric materials using plasma based processes |
| WO2006029651A1 (en) * | 2004-09-16 | 2006-03-23 | S.O.I.Tec Silicon On Insulator Technologies | Method of manufacturing a silicon dioxide layer |
| FR2911598B1 (fr) * | 2007-01-22 | 2009-04-17 | Soitec Silicon On Insulator | Procede de rugosification de surface. |
| FR2911597B1 (fr) * | 2007-01-22 | 2009-05-01 | Soitec Silicon On Insulator | Procede de formation et de controle d'interfaces rugueuses. |
| FR2912839B1 (fr) * | 2007-02-16 | 2009-05-15 | Soitec Silicon On Insulator | Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud |
| WO2008123116A1 (en) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| WO2008123117A1 (en) * | 2007-03-26 | 2008-10-16 | Semiconductor Energy Laboratory Co., Ltd. | Soi substrate and method for manufacturing soi substrate |
| CN101281912B (zh) * | 2007-04-03 | 2013-01-23 | 株式会社半导体能源研究所 | Soi衬底及其制造方法以及半导体装置 |
| CN102623400B (zh) | 2007-04-13 | 2015-05-20 | 株式会社半导体能源研究所 | 显示器件、用于制造显示器件的方法、以及soi衬底 |
| KR101440930B1 (ko) * | 2007-04-20 | 2014-09-15 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Soi 기판의 제작방법 |
| EP1993128A3 (en) * | 2007-05-17 | 2010-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
| US8513678B2 (en) | 2007-05-18 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Light-emitting device |
| US7763502B2 (en) * | 2007-06-22 | 2010-07-27 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device |
| FR2923079B1 (fr) * | 2007-10-26 | 2017-10-27 | S O I Tec Silicon On Insulator Tech | Substrats soi avec couche fine isolante enterree |
| WO2009057669A1 (en) * | 2007-11-01 | 2009-05-07 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing photoelectric conversion device |
| JP5354900B2 (ja) * | 2007-12-28 | 2013-11-27 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
| US8093136B2 (en) * | 2007-12-28 | 2012-01-10 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| FR2926674B1 (fr) * | 2008-01-21 | 2010-03-26 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable |
| JP5503876B2 (ja) * | 2008-01-24 | 2014-05-28 | 株式会社半導体エネルギー研究所 | 半導体基板の製造方法 |
| US8119490B2 (en) * | 2008-02-04 | 2012-02-21 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| US7858495B2 (en) * | 2008-02-04 | 2010-12-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| JP4577382B2 (ja) * | 2008-03-06 | 2010-11-10 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
| KR101541940B1 (ko) * | 2008-04-01 | 2015-08-04 | 신에쓰 가가꾸 고교 가부시끼가이샤 | Soi 기판의 제조 방법 |
| FR2931585B1 (fr) * | 2008-05-26 | 2010-09-03 | Commissariat Energie Atomique | Traitement de surface par plasma d'azote dans un procede de collage direct |
| JP5548395B2 (ja) | 2008-06-25 | 2014-07-16 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| JP5663150B2 (ja) * | 2008-07-22 | 2015-02-04 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| US20100022070A1 (en) * | 2008-07-22 | 2010-01-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
| SG160295A1 (en) * | 2008-09-29 | 2010-04-29 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
| US8741740B2 (en) * | 2008-10-02 | 2014-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
| JP5496598B2 (ja) * | 2008-10-31 | 2014-05-21 | 信越化学工業株式会社 | シリコン薄膜転写絶縁性ウェーハの製造方法 |
| FR2942911B1 (fr) * | 2009-03-09 | 2011-05-13 | Soitec Silicon On Insulator | Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique |
| FR2951026B1 (fr) | 2009-10-01 | 2011-12-02 | St Microelectronics Sa | Procede de fabrication de resonateurs baw sur une tranche semiconductrice |
| FR2951024B1 (fr) | 2009-10-01 | 2012-03-23 | St Microelectronics Sa | Procede de fabrication de resonateur baw a facteur de qualite eleve |
| FR2951023B1 (fr) | 2009-10-01 | 2012-03-09 | St Microelectronics Sa | Procede de fabrication d'oscillateurs monolithiques a resonateurs baw |
| JP5917036B2 (ja) | 2010-08-05 | 2016-05-11 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
| JP2012156495A (ja) | 2011-01-07 | 2012-08-16 | Semiconductor Energy Lab Co Ltd | Soi基板の作製方法 |
| EP3447789B1 (de) | 2011-01-25 | 2021-04-14 | EV Group E. Thallner GmbH | Verfahren zum permanenten bonden von wafern |
| EP2695183A1 (de) | 2011-04-08 | 2014-02-12 | Ev Group E. Thallner GmbH | Verfahren zum permanenten bonden von wafern |
| US8802534B2 (en) | 2011-06-14 | 2014-08-12 | Semiconductor Energy Laboratory Co., Ltd. | Method for forming SOI substrate and apparatus for forming the same |
| KR102148336B1 (ko) * | 2013-11-26 | 2020-08-27 | 삼성전자주식회사 | 표면 처리 방법, 반도체 제조 방법 및 이에 의해 제조된 반도체 장치 |
| CN106170834B (zh) * | 2014-01-29 | 2018-09-11 | 帕尔文纳纳桑·加内森 | 具有自冷式外壳结构和紧急热交换系统的浮动式核反应堆 |
| US10049947B2 (en) | 2014-07-08 | 2018-08-14 | Massachusetts Institute Of Technology | Method of manufacturing a substrate |
| FR3036200B1 (fr) * | 2015-05-13 | 2017-05-05 | Soitec Silicon On Insulator | Methode de calibration pour equipements de traitement thermique |
| WO2017102383A1 (en) * | 2015-12-18 | 2017-06-22 | Asml Netherlands B.V. | A method of manufacturing a membrane assembly for euv lithography, a membrane assembly, a lithographic apparatus, and a device manufacturing method |
| FR3045939B1 (fr) | 2015-12-22 | 2018-03-30 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de collage direct entre deux structures |
| KR102509390B1 (ko) * | 2017-07-24 | 2023-03-14 | 어플라이드 머티어리얼스, 인코포레이티드 | 산화규소 상의 초박형 비정질 규소 막의 연속성을 개선하기 위한 전처리 접근법 |
| FR3079345B1 (fr) | 2018-03-26 | 2020-02-21 | Soitec | Procede de fabrication d'un substrat pour dispositif radiofrequence |
| CN114203546B (zh) * | 2020-09-18 | 2026-04-03 | 中芯集成电路(宁波)有限公司 | 半导体器件及其制造方法 |
| JP7487659B2 (ja) * | 2020-12-25 | 2024-05-21 | 株式会社Sumco | Soiウェーハの製造方法 |
| CN114688950B (zh) * | 2022-05-31 | 2022-08-23 | 陕西建工第一建设集团有限公司 | 一种建筑施工用铝合金板平整检测装置 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271101B1 (en) * | 1998-07-29 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Process for production of SOI substrate and process for production of semiconductor device |
| US20040124416A1 (en) * | 2002-12-30 | 2004-07-01 | Knipp Dietmar P. | Method for producing organic electronic devices on deposited dielectric materials |
| WO2005014895A1 (en) * | 2003-07-24 | 2005-02-17 | S.O.I.Tec Silicon On Insulator Technologies | A method of fabricating an epitaxially grown layer |
| US20050079712A1 (en) * | 2000-02-16 | 2005-04-14 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6489255B1 (en) * | 1995-06-05 | 2002-12-03 | International Business Machines Corporation | Low temperature/low dopant oxide glass film |
| US6051478A (en) * | 1997-12-18 | 2000-04-18 | Advanced Micro Devices, Inc. | Method of enhancing trench edge oxide quality |
| US6489241B1 (en) * | 1999-09-17 | 2002-12-03 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
| FR2827078B1 (fr) * | 2001-07-04 | 2005-02-04 | Soitec Silicon On Insulator | Procede de diminution de rugosite de surface |
| US7749910B2 (en) * | 2001-07-04 | 2010-07-06 | S.O.I.Tec Silicon On Insulator Technologies | Method of reducing the surface roughness of a semiconductor wafer |
| JP4086272B2 (ja) * | 2001-07-26 | 2008-05-14 | 株式会社東芝 | 半導体装置 |
| FR2835095B1 (fr) * | 2002-01-22 | 2005-03-18 | Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique | |
| WO2004061944A1 (en) * | 2003-01-07 | 2004-07-22 | S.O.I.Tec Silicon On Insulator Technologies | Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer |
| JP2004259970A (ja) * | 2003-02-26 | 2004-09-16 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
| US6723666B1 (en) * | 2003-03-06 | 2004-04-20 | Advanced Micro Devices, Inc. | Method for reducing gate oxide surface irregularities |
| US6982210B2 (en) * | 2003-07-10 | 2006-01-03 | S.O.I.Tec Silicon On Insulator Technologies S.A. | Method for manufacturing a multilayer semiconductor structure that includes an irregular layer |
| FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
| JP2005150686A (ja) * | 2003-10-22 | 2005-06-09 | Sharp Corp | 半導体装置およびその製造方法 |
| US20050250346A1 (en) * | 2004-05-06 | 2005-11-10 | Applied Materials, Inc. | Process and apparatus for post deposition treatment of low k dielectric materials |
| US7349140B2 (en) * | 2005-05-31 | 2008-03-25 | Miradia Inc. | Triple alignment substrate method and structure for packaging devices |
-
2005
- 2005-07-13 FR FR0507573A patent/FR2888663B1/fr not_active Expired - Fee Related
-
2006
- 2006-07-05 US US11/481,701 patent/US7446019B2/en active Active
- 2006-07-12 SG SG200901884-7A patent/SG151287A1/en unknown
- 2006-07-12 WO PCT/EP2006/064169 patent/WO2007006803A1/fr not_active Ceased
- 2006-07-12 AT AT06777736T patent/ATE524828T1/de not_active IP Right Cessation
- 2006-07-12 EP EP06777736A patent/EP1902463B1/fr active Active
- 2006-07-12 JP JP2008520879A patent/JP4927080B2/ja active Active
- 2006-07-12 CN CN200680030390A patent/CN100576462C/zh active Active
- 2006-07-12 KR KR1020087001701A patent/KR100958467B1/ko active Active
-
2008
- 2008-09-19 US US12/234,280 patent/US8183128B2/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6271101B1 (en) * | 1998-07-29 | 2001-08-07 | Semiconductor Energy Laboratory Co., Ltd. | Process for production of SOI substrate and process for production of semiconductor device |
| US20050079712A1 (en) * | 2000-02-16 | 2005-04-14 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
| US20040124416A1 (en) * | 2002-12-30 | 2004-07-01 | Knipp Dietmar P. | Method for producing organic electronic devices on deposited dielectric materials |
| WO2005014895A1 (en) * | 2003-07-24 | 2005-02-17 | S.O.I.Tec Silicon On Insulator Technologies | A method of fabricating an epitaxially grown layer |
Non-Patent Citations (2)
| Title |
|---|
| Engineering strained silicon on insulator wafers with theSmart Cut(TM) technology. B. Ghyselen et al.Solid-State Electronics,Vol.48 . 2004 * |
| Low-pressure deposition of high-quality SiO2 films bypyrolysisof tetraethylorthosilicate. F. S. Becker et al.J. Vac. Sci. Technol. B,Vol.5 No.6. 1987 * |
Also Published As
| Publication number | Publication date |
|---|---|
| SG151287A1 (en) | 2009-04-30 |
| US8183128B2 (en) | 2012-05-22 |
| KR100958467B1 (ko) | 2010-05-17 |
| JP4927080B2 (ja) | 2012-05-09 |
| CN101243545A (zh) | 2008-08-13 |
| EP1902463B1 (fr) | 2011-09-14 |
| US20090023267A1 (en) | 2009-01-22 |
| WO2007006803A1 (fr) | 2007-01-18 |
| FR2888663A1 (fr) | 2007-01-19 |
| KR20080031747A (ko) | 2008-04-10 |
| US7446019B2 (en) | 2008-11-04 |
| US20070020947A1 (en) | 2007-01-25 |
| FR2888663B1 (fr) | 2008-04-18 |
| EP1902463A1 (fr) | 2008-03-26 |
| JP2009501440A (ja) | 2009-01-15 |
| ATE524828T1 (de) | 2011-09-15 |
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| Date | Code | Title | Description |
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| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SUTAIKE INC. Free format text: FORMER NAME: SOITEC SILICON ON INSULATOR |
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| CP01 | Change in the name or title of a patent holder |
Address after: Benin, France Patentee after: SOITEC Address before: Benin, France Patentee before: Soitec Silicon On Insulator |