CN100576462C - 减小厚绝缘体层的粗糙度的方法 - Google Patents

减小厚绝缘体层的粗糙度的方法 Download PDF

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Publication number
CN100576462C
CN100576462C CN200680030390A CN200680030390A CN100576462C CN 100576462 C CN100576462 C CN 100576462C CN 200680030390 A CN200680030390 A CN 200680030390A CN 200680030390 A CN200680030390 A CN 200680030390A CN 100576462 C CN100576462 C CN 100576462C
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insulator layer
plasma
substrate
layer
roughness
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CN101243545A (zh
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尼古拉斯·达瓦尔
塞巴斯蒂安·凯尔迪勒
塞西尔·奥尔耐特
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Soitec SA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Formation Of Insulating Films (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Magnetic Heads (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Element Separation (AREA)
CN200680030390A 2005-07-13 2006-07-12 减小厚绝缘体层的粗糙度的方法 Active CN100576462C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0507573A FR2888663B1 (fr) 2005-07-13 2005-07-13 Procede de diminution de la rugosite d'une couche epaisse d'isolant
FR05/07573 2005-07-13

Publications (2)

Publication Number Publication Date
CN101243545A CN101243545A (zh) 2008-08-13
CN100576462C true CN100576462C (zh) 2009-12-30

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US (2) US7446019B2 (enExample)
EP (1) EP1902463B1 (enExample)
JP (1) JP4927080B2 (enExample)
KR (1) KR100958467B1 (enExample)
CN (1) CN100576462C (enExample)
AT (1) ATE524828T1 (enExample)
FR (1) FR2888663B1 (enExample)
SG (1) SG151287A1 (enExample)
WO (1) WO2007006803A1 (enExample)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes
EP1789999B1 (en) * 2004-09-16 2017-06-07 Soitec Method of manufacturing a silicon dioxide layer
FR2911597B1 (fr) * 2007-01-22 2009-05-01 Soitec Silicon On Insulator Procede de formation et de controle d'interfaces rugueuses.
FR2911598B1 (fr) * 2007-01-22 2009-04-17 Soitec Silicon On Insulator Procede de rugosification de surface.
FR2912839B1 (fr) * 2007-02-16 2009-05-15 Soitec Silicon On Insulator Amelioration de la qualite de l'interface de collage par nettoyage froid et collage a chaud
WO2008123116A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
WO2008123117A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
CN101657882B (zh) 2007-04-13 2012-05-30 株式会社半导体能源研究所 显示器件、用于制造显示器件的方法、以及soi衬底
KR101440930B1 (ko) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Ｓｏｉ 기판의 제작방법
EP1993128A3 (en) * 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US8513678B2 (en) 2007-05-18 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
US7763502B2 (en) * 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
FR2923079B1 (fr) * 2007-10-26 2017-10-27 S O I Tec Silicon On Insulator Tech Substrats soi avec couche fine isolante enterree
CN101842910B (zh) * 2007-11-01 2013-03-27 株式会社半导体能源研究所 用于制造光电转换器件的方法
JP5354900B2 (ja) * 2007-12-28 2013-11-27 株式会社半導体エネルギー研究所 半導体基板の作製方法
US8093136B2 (en) * 2007-12-28 2012-01-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
FR2926674B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication d'une structure composite avec couche d'oxyde de collage stable
JP5503876B2 (ja) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 半導体基板の製造方法
US8119490B2 (en) * 2008-02-04 2012-02-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US7858495B2 (en) * 2008-02-04 2010-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP4577382B2 (ja) * 2008-03-06 2010-11-10 信越半導体株式会社 貼り合わせウェーハの製造方法
US8420503B2 (en) 2008-04-01 2013-04-16 Shin—Etsu Chemical Co., Ltd. Method for producing SOI substrate
FR2931585B1 (fr) * 2008-05-26 2010-09-03 Commissariat Energie Atomique Traitement de surface par plasma d'azote dans un procede de collage direct
JP5548395B2 (ja) 2008-06-25 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
JP5663150B2 (ja) * 2008-07-22 2015-02-04 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
SG160295A1 (en) * 2008-09-29 2010-04-29 Semiconductor Energy Lab Method for manufacturing semiconductor device
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP5496598B2 (ja) * 2008-10-31 2014-05-21 信越化学工業株式会社 シリコン薄膜転写絶縁性ウェーハの製造方法
FR2942911B1 (fr) * 2009-03-09 2011-05-13 Soitec Silicon On Insulator Procede de realisation d'une heterostructure avec adaptation locale de coefficient de dilatation thermique
FR2951026B1 (fr) * 2009-10-01 2011-12-02 St Microelectronics Sa Procede de fabrication de resonateurs baw sur une tranche semiconductrice
FR2951023B1 (fr) 2009-10-01 2012-03-09 St Microelectronics Sa Procede de fabrication d'oscillateurs monolithiques a resonateurs baw
FR2951024B1 (fr) 2009-10-01 2012-03-23 St Microelectronics Sa Procede de fabrication de resonateur baw a facteur de qualite eleve
JP5917036B2 (ja) 2010-08-05 2016-05-11 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
JP2012156495A (ja) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法
KR101705937B1 (ko) 2011-01-25 2017-02-10 에베 그룹 에. 탈너 게엠베하 웨이퍼들의 영구적 결합을 위한 방법
JP2014516470A (ja) 2011-04-08 2014-07-10 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウェハを恒久的にボンディングするための方法
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
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EP3100275B1 (en) * 2014-01-29 2018-08-22 Palvannanathan Ganesan Floating nuclear power reactor with a self-cooling containment structure and an emergency heat exchange system
JP6751385B2 (ja) * 2014-07-08 2020-09-02 マサチューセッツ インスティテュート オブ テクノロジー 基板の製造方法
FR3036200B1 (fr) * 2015-05-13 2017-05-05 Soitec Silicon On Insulator Methode de calibration pour equipements de traitement thermique
WO2017102383A1 (en) * 2015-12-18 2017-06-22 Asml Netherlands B.V. A method of manufacturing a membrane assembly for euv lithography, a membrane assembly, a lithographic apparatus, and a device manufacturing method
FR3045939B1 (fr) * 2015-12-22 2018-03-30 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct entre deux structures
CN110709967B (zh) * 2017-07-24 2023-09-01 应用材料公司 改善在氧化硅上的超薄非晶硅膜的连续性的预处理方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US20040124416A1 (en) * 2002-12-30 2004-07-01 Knipp Dietmar P. Method for producing organic electronic devices on deposited dielectric materials
WO2005014895A1 (en) * 2003-07-24 2005-02-17 S.O.I.Tec Silicon On Insulator Technologies A method of fabricating an epitaxially grown layer
US20050079712A1 (en) * 2000-02-16 2005-04-14 Ziptronix, Inc. Method for low temperature bonding and bonded structure

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489255B1 (en) * 1995-06-05 2002-12-03 International Business Machines Corporation Low temperature/low dopant oxide glass film
US6051478A (en) * 1997-12-18 2000-04-18 Advanced Micro Devices, Inc. Method of enhancing trench edge oxide quality
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film
FR2827078B1 (fr) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator Procede de diminution de rugosite de surface
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
JP4086272B2 (ja) * 2001-07-26 2008-05-14 株式会社東芝 半導体装置
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
CN100483666C (zh) * 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 施主晶片以及重复利用晶片的方法和剥离有用层的方法
JP2004259970A (ja) * 2003-02-26 2004-09-16 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
US6723666B1 (en) * 2003-03-06 2004-04-20 Advanced Micro Devices, Inc. Method for reducing gate oxide surface irregularities
US6982210B2 (en) * 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
FR2857983B1 (fr) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiee
JP2005150686A (ja) * 2003-10-22 2005-06-09 Sharp Corp 半導体装置およびその製造方法
US20050250346A1 (en) * 2004-05-06 2005-11-10 Applied Materials, Inc. Process and apparatus for post deposition treatment of low k dielectric materials
US7349140B2 (en) * 2005-05-31 2008-03-25 Miradia Inc. Triple alignment substrate method and structure for packaging devices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US20050079712A1 (en) * 2000-02-16 2005-04-14 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US20040124416A1 (en) * 2002-12-30 2004-07-01 Knipp Dietmar P. Method for producing organic electronic devices on deposited dielectric materials
WO2005014895A1 (en) * 2003-07-24 2005-02-17 S.O.I.Tec Silicon On Insulator Technologies A method of fabricating an epitaxially grown layer

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Engineering strained silicon on insulator wafers with theSmart Cut(TM) technology. B. Ghyselen et al.Solid-State Electronics,Vol.48 . 2004 *
Low-pressure deposition of high-quality SiO2 films bypyrolysisof tetraethylorthosilicate. F. S. Becker et al.J. Vac. Sci. Technol. B,Vol.5 No.6. 1987 *

Also Published As

Publication number Publication date
KR20080031747A (ko) 2008-04-10
US20070020947A1 (en) 2007-01-25
WO2007006803A1 (fr) 2007-01-18
SG151287A1 (en) 2009-04-30
CN101243545A (zh) 2008-08-13
JP4927080B2 (ja) 2012-05-09
US7446019B2 (en) 2008-11-04
EP1902463A1 (fr) 2008-03-26
JP2009501440A (ja) 2009-01-15
KR100958467B1 (ko) 2010-05-17
ATE524828T1 (de) 2011-09-15
FR2888663B1 (fr) 2008-04-18
US20090023267A1 (en) 2009-01-22
FR2888663A1 (fr) 2007-01-19
US8183128B2 (en) 2012-05-22
EP1902463B1 (fr) 2011-09-14

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