CN100561907C - 位同步电路 - Google Patents

位同步电路 Download PDF

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Publication number
CN100561907C
CN100561907C CNB200610005821XA CN200610005821A CN100561907C CN 100561907 C CN100561907 C CN 100561907C CN B200610005821X A CNB200610005821X A CN B200610005821XA CN 200610005821 A CN200610005821 A CN 200610005821A CN 100561907 C CN100561907 C CN 100561907C
Authority
CN
China
Prior art keywords
phase
clock
data
mentioned
initial stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB200610005821XA
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English (en)
Chinese (zh)
Other versions
CN1909442A (zh
Inventor
矢岛祐辅
加泽彻
芦贤浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Communication Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Communication Technologies Ltd filed Critical Hitachi Communication Technologies Ltd
Publication of CN1909442A publication Critical patent/CN1909442A/zh
Application granted granted Critical
Publication of CN100561907C publication Critical patent/CN100561907C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0004—Initialisation of the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Small-Scale Networks (AREA)
CNB200610005821XA 2005-08-03 2006-01-10 位同步电路 Expired - Fee Related CN100561907C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP225053/2005 2005-08-03
JP2005225053A JP3950899B2 (ja) 2005-08-03 2005-08-03 ビット同期回路

Publications (2)

Publication Number Publication Date
CN1909442A CN1909442A (zh) 2007-02-07
CN100561907C true CN100561907C (zh) 2009-11-18

Family

ID=37700441

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB200610005821XA Expired - Fee Related CN100561907C (zh) 2005-08-03 2006-01-10 位同步电路

Country Status (3)

Country Link
US (2) US7483506B2 (ja)
JP (1) JP3950899B2 (ja)
CN (1) CN100561907C (ja)

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JP4148951B2 (ja) * 2005-01-12 2008-09-10 株式会社東芝 磁気記録再生装置
KR100819308B1 (ko) * 2005-09-02 2008-04-03 삼성전자주식회사 안정적인 ｔｄｄ 방식의 무선 서비스가 가능하도록 하는ｒｏｆ 링크 장치
US9014561B2 (en) * 2006-02-03 2015-04-21 At&T Intellectual Property Ii, L.P. Wavelength upgrade for passive optical networks
WO2008012928A1 (fr) * 2006-07-28 2008-01-31 Panasonic Corporation Comparateur de phase, dispositif de comparaison de phase, et système de récupération de données d'horloge
WO2008035428A1 (fr) * 2006-09-21 2008-03-27 Fujitsu Limited Terminal de communication, et procédé de réception du signal
US8243869B2 (en) * 2006-11-28 2012-08-14 Broadlight Ltd. Burst mode clock and data recovery circuit and method
US7889815B2 (en) * 2007-02-13 2011-02-15 Optical Communication Products, Inc. Burst mode receiver for passive optical network
US7724049B2 (en) * 2007-02-28 2010-05-25 Micron Technology, Inc. Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal
JP4359786B2 (ja) * 2007-03-22 2009-11-04 日本電気株式会社 データ伝送装置及びクロック切替回路
US20090010643A1 (en) * 2007-07-06 2009-01-08 Delew David A Method and apparatus for identifying faults in a passive optical network
WO2009010891A1 (en) * 2007-07-17 2009-01-22 Nxp B.V. A method and a device for data sample clock reconstruction
JP2009081662A (ja) * 2007-09-26 2009-04-16 Oki Electric Ind Co Ltd ポイントｔｏマルチポイント光通信システム
CN101874379B (zh) 2007-11-28 2013-03-27 三菱电机株式会社 比特识别电路
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
JP5135009B2 (ja) * 2008-03-13 2013-01-30 株式会社日立製作所 クロックデータリカバリ回路
JP5243877B2 (ja) * 2008-08-04 2013-07-24 ルネサスエレクトロニクス株式会社 通信装置
JP5188287B2 (ja) * 2008-06-25 2013-04-24 ルネサスエレクトロニクス株式会社 通信装置
TWI358906B (en) * 2008-08-15 2012-02-21 Ind Tech Res Inst Burst-mode clock and data recovery circuit using p
US8942561B2 (en) * 2008-10-21 2015-01-27 Broadcom Corporation Synchronization transport over passive optical networks
JP4924630B2 (ja) * 2009-02-06 2012-04-25 富士通株式会社 クロック生成回路
SI23045A (sl) * 2009-04-29 2010-10-29 Instrumentation Technologies D.D. Optični sistem za prenos signala časovne reference
JP5478950B2 (ja) * 2009-06-15 2014-04-23 ルネサスエレクトロニクス株式会社 半導体装置及びデータ処理システム
US20110001530A1 (en) * 2009-07-01 2011-01-06 Kawasaki Microelectronics Inc. Method and apparatus for receiving burst data without using external detection signal
US8582418B2 (en) * 2009-10-26 2013-11-12 Electronics And Telecommunications Research Institute Packet mode auto-detection in multi-mode wireless communication system, signal field transmission for the packet mode auto-detection, and gain control based on the packet mode
US20110289593A1 (en) * 2010-05-24 2011-11-24 Alexander Roger Deas Means to enhance the security of data in a communications channel
JP5617405B2 (ja) * 2010-07-16 2014-11-05 三菱電機株式会社 データ再生回路、局側光送受信装置及びデータ再生方法
JP5728249B2 (ja) 2011-02-25 2015-06-03 任天堂株式会社 情報処理システム、情報処理装置、情報処理プログラム、および、情報処理方法
JP5707171B2 (ja) 2011-02-25 2015-04-22 任天堂株式会社 通信制御装置、通信制御プログラム、通信制御方法、および、情報処理システム
JP6092727B2 (ja) 2012-08-30 2017-03-08 株式会社メガチップス 受信装置
US9203351B2 (en) 2013-03-15 2015-12-01 Megachips Corporation Offset cancellation with minimum noise impact and gain-bandwidth degradation
TW201445887A (zh) * 2013-05-23 2014-12-01 Raydium Semiconductor Corp 時脈嵌入式序列資料傳輸系統及時脈還原方法
JP6580346B2 (ja) * 2015-03-04 2019-09-25 ザインエレクトロニクス株式会社 送信装置、受信装置および送受信システム
US9893877B2 (en) * 2016-01-15 2018-02-13 Analog Devices Global Circuits, systems, and methods for synchronization of sampling and sample rate setting
CN109831191B (zh) * 2016-09-13 2021-10-26 华为技术有限公司 一种多路时钟分发电路及电子设备
TWI640901B (zh) * 2018-02-21 2018-11-11 友達光電股份有限公司 資料擷取方法及裝置
US11212072B1 (en) * 2020-12-22 2021-12-28 Xilinx, Inc. Circuit for and method of processing a data stream

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07307764A (ja) * 1994-03-18 1995-11-21 Fujitsu Ltd 光並列受信装置に用いられるデータ識別回路、光並列受信装置、光並列伝送装置及び光伝送ファイバの端末構造
JP3355261B2 (ja) 1995-07-20 2002-12-09 株式会社日立製作所 ビット同期回路及びビット同期方法
JP3294566B2 (ja) * 1999-05-28 2002-06-24 沖電気工業株式会社 ビット位相同期装置
WO2001059982A1 (fr) * 2000-02-14 2001-08-16 Fujitsu Limited Recepteur optique
JP4279611B2 (ja) 2003-06-17 2009-06-17 株式会社日立コミュニケーションテクノロジー ビット同期回路および光伝送システム局側装置

Also Published As

Publication number Publication date
JP3950899B2 (ja) 2007-08-01
CN1909442A (zh) 2007-02-07
US8204168B2 (en) 2012-06-19
US20070030937A1 (en) 2007-02-08
JP2007043460A (ja) 2007-02-15
US7483506B2 (en) 2009-01-27
US20090123160A1 (en) 2009-05-14

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Effective date: 20100318

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Granted publication date: 20091118

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CF01 Termination of patent right due to non-payment of annual fee