CN100552930C - 高速集成电路封装 - Google Patents

高速集成电路封装 Download PDF

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Publication number
CN100552930C
CN100552930C CNB2006100988331A CN200610098833A CN100552930C CN 100552930 C CN100552930 C CN 100552930C CN B2006100988331 A CNB2006100988331 A CN B2006100988331A CN 200610098833 A CN200610098833 A CN 200610098833A CN 100552930 C CN100552930 C CN 100552930C
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pin
integrated circuit
pad
polarity
encapsulation
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CN1933135A (zh
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塞哈特·苏塔迪嘉
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Abstract

本发明提供一种包含集成电路管芯的集成电路封装，所述集成电路管芯包含第一焊盘、与第一焊盘相邻的第二焊盘、与第二焊盘相邻的第三焊盘以及与第三焊盘相邻的第四焊盘。引脚框架包含第一引脚、与第一引脚相邻的第二引脚、与第二引脚相邻的第三引脚以及与第三引脚相邻的第四引脚，其中第四引脚的第一末端延伸超过第一、第二和第三引脚中的至少一个并且沿朝向由第三引脚定义的路径的方向延伸。第一、第二、第三和第四键合丝将第一、第二、第四和第三引脚分别连接到第一、第二、第三和第四焊盘。

Description

高速集成电路封装
技术领域
本发明涉及集成电路(IC)封装，更具体而言涉及IC高速封装。
背景技术
现代的集成电路(IC)通常使用差分信令。在差分信令中，信号在两个独立的有源导体之间传送而不是在一个有源的导体和地之间传送。差分信号的大小是两个信号之间的差别而不是两个单独的信号和地之间的电压。
为了发送差分信号到IC或者从IC接收差分信号，差分信号在引脚框架的一对导体上传输。现在参照图1-图2，示例性的封装10和10’被示为包括具有焊盘14的集成电路管芯(die)12，焊盘14通过键合丝(bondwire)16连接到引脚框架24的引脚20。封装10和10’通常包裹在合适的保护材料24中。
现在参照图3，差分信号对50-1、50-2和50-3分别通过引脚20-1A和20-1B、20-2A和20-2B、及20-3A和20-3B以及键合丝16-1A和16-1B、16-2A和16-2B、及16-3A和16-3B分别连接到集成电路管芯12的焊盘14-1A和14-1B、14-2A和14-2B、及14-3A和14-3B。在图3中的每个差分对中，分别地，符号A代表第一极性导体，符号B代表第二极性导体。
相邻的差分对彼此之间通常位置很近。在一些情况下，差分对的位置可能是如下情况，其中一个差分对的第一极性导体的一侧紧邻的是同一差分对的第二极性导体，而另一侧是另一差分对的第二极性导体。对耦合(pair coupling)在相邻的高速差分信号之间可能发生。例如，对耦合在图3中的60和62处可能发生。在相邻对上承载的信号之间差别的大小可能引起数据误差以及/或者将设计余度降低到不可接受的水平，尤其对于高速信号例如吉比特(Gigabit)每秒以及更高的数据率更是如此。与具有接地平面保护的球栅面阵列(BGA)封装相比，对耦合问题对于低成本的塑料引脚框架甚至可能更严重。
发明内容
本发明的一个技术方案提供了一种集成电路封装，其包含：集成电路管芯，包含第一焊盘、与第一焊盘相邻的第二焊盘、与第二焊盘相邻的第三焊盘以及与第三焊盘相邻的第四焊盘，其中第一、第二、第三和第四焊盘对齐，并且第二焊盘位于第一焊盘和第三焊盘之间；引脚框架，包含第一引脚、与第一引脚相邻的第二引脚、与第二引脚相邻的第三引脚以及与第三引脚相邻的第四引脚，其中第三引脚位于第二引脚和第四引脚之间；以及第一、第二、第三和第四键合丝，将所述第一、第二、第三和第四引脚分别连接到所述第一、第二、第三和第四焊盘，
在其他特征中，所述第一和第二引脚以及所述第三和第四引脚间隔第一距离并且所述第二和第三引脚间隔与所述第一距离不同的第二距离。所述第一引脚承载具有第一极性的信号，所述第二引脚承载具有第二极性的信号，所述第三引脚承载具有第一极性的信号并且所述第四引脚承载具有第二极性的信号，所述第一极性和第二极性是相反的极性。所述引脚框架的第一和第二引脚以及第三和第四引脚承载具有大于或等于1吉比特每秒(Gb/s)的频率的高速差分信号。
在其他特征中，所述引脚框架还包含与第四引脚间隔第三距离的第五引脚，并且其中所述第三距离与所述第一和第二距离不同。还包含与所述第五引脚间隔第四距离的第六引脚，其中所述第四距离与所述第一距离不同，并且其中所述第五和第六引脚承载控制信号。
在其他特征中，所述集成电路封装还包含与所述第一、第二、第三和第四焊盘相连的串行器/并行器(SERDES)模块。所述集成电路管芯的第一和第二焊盘与所述SERDES模块的差分发送信号相关联，并且所述集成电路管芯的第三和第四焊盘与所述SERDES模块的差分接收信号相关联。
本发明的另一技术方案提供了一种网络接口，其包含如权利要求1所述的集成电路封装，其中所述网络接口是遵从以太网的并且以大于1Gb/s的速度进行操作。
在其他特征中，所述集成电路封装还包含位于所述第二和第三引脚之间并且与参考电压相连，但是不与所述集成电路管芯相连的第五引脚。
在其他特征中，所述集成电路封装还包含附接于所述引脚框架的第一、第二、第三和第四引脚的导电带，所述导电带包含导电层和与所述第一、第二、第三和第四引脚接触的绝缘粘合层。所述导电带包含多个隔开的穿孔。
在其他特征中，所述集成电路封装还包含与所述集成电路管芯、所述导电带、所述引脚框架和所述键合丝接触的封装材料。
本发明的另一技术方案提供了一种集成电路封装，其包含：集成电路管芯，包含N个焊盘，其中N是大于一的整数；引脚框架，包含N个相邻的引脚；N个连接装置，独立地将所述N个引脚分别连接到所述N个焊盘；以及第一材料，包含绝缘层和导电层，其中所述绝缘层被粘合地设置在所述引脚框架的所述N个引脚上。其中所述N个相邻的引脚中的第一引脚承载具有第一极性的信号，第二引脚承载具有第二极性的信号，所述第一引脚与第二引脚相邻，并且所述第一极性和第二极性是相反的极性。
在其他特征中，所述N个连接装置包含N根键合丝。所述第一材料包含多个隔开的穿孔。
在其他特征中，所述集成电路封装还包含与所述集成电路管芯、所述第一材料、所述引脚框架和所述N根键合丝接触的封装材料。所述第一材料包含导电带。
本发明可应用于的更广的范围将从下文中提供的详细描述中变得清楚。应该了解虽然详细的描述和具体的示例指示了本发明的优选实施例，但是其只是作为说明的目的而不是要限制本发明的范围。
附图说明
从详细描述和附图中将会更全面地理解本发明，其中：
图1是根据现有技术的第一示例性封装、IC、键合丝和引脚框架的引脚的侧面横截面视图；
图2是根据现有技术的第二示例性封装、IC、键合丝和引脚框架的引脚的侧面横截面视图；
图3是根据现有技术通过引脚框架的引脚和键合丝连接到IC焊盘的差分信号对的局部平面视图；
图4是根据本发明的一个实现方式通过引脚框架的引脚和键合丝连接到IC焊盘的差分信号对的局部平面视图；
图5是根据本发明的另一个实现方式通过引脚框架的引脚和键合丝连接到IC焊盘的差分信号对的局部平面视图；
图6A是根据本发明的另一个实现方式通过引脚框架的引脚和堆叠键合丝连接到IC焊盘的差分信号对的局部平面视图；
图6B是图6A的通过引脚框架的引脚和堆叠键合丝连接到IC焊盘的差分信号对的局部侧面视图；
图7说明了根据本发明的包括串行器/并行器模块的IC的封装，其中串行器/并行器模块在差分收发对上接收信号；
图8说明了根据本发明的使用高速封装的网络接口IC的封装；
图9A说明了设置在硬盘驱动器中的本发明；
图9B说明了设置在数字通用光盘中的本发明；
图9C说明了设置在高清晰度电视中的本发明；
图9D说明了设置在车辆控制系统中的本发明；
图9E说明了设置在便携式电话中的本发明；
图9F说明了设置在机顶盒中的本发明；
图9G说明了设置在媒体播放器中的本发明；
图10A说明了包括具有不规则间隔引脚的引脚框架的封装；
图10B说明了包括具有不规则间隔引脚和在高速引脚之间具有接地引脚的引脚框架的封装；
图11A说明了包括具有不规则间隔引脚和导电带的引脚框架的封装，所述导电带具有连接到引脚的绝缘粘合层；
图11B是图11A的导电带的横截面侧面视图；
图11C是图11A的导电带的示出穿孔的局部平面视图；
图12A-图12D说明了连接引脚的各种方法；
图13A是包括球栅面阵列衬底的封装的侧面视图；
图13B是包括倒装芯片和球栅面阵列衬底的封装的侧面视图；
图13C是一个示例性BGA封装的横截面视图；
图14A是说明用于连接到集成电路管芯的高速迹线的BGA跳线的平面视图；
图14B是说明BGA跳线的简化的横截面视图；
图15A是说明使用其接地平面的可替换的BGA跳线的简化的横截面视图；
图15B是说明使用其电源平面的可替换的BGA跳线的简化的横截面视图；以及
图15C是说明图15B的电源平面和BGA跳线的平面视图。
具体实施方式
优选实施例的下列描述实质上仅是示例性的，并没有想要限制本发明、本发明的应用或者使用。为了清楚的目的，将在图中使用相同的标号来标识相似的元件。
本发明降低了以高速进行操作的差分线的对耦合。现在参照图4，差分信号对根据本发明的一种实现方式通过引脚框架的引脚和键合丝连接到IC的焊盘。引脚框架100包含引脚104的一个或多个组102，引脚104包括第一对引脚104-1A和104-1B以及第二对引脚104-2A和104-2B(共同称为引脚104)。引脚104-1A位于与引脚104-1B相邻处，引脚104-1B位于与引脚104-2A相邻处，并且引脚104-2A位于与引脚104-2B相邻处。
分别地，引脚104-1A承载具有第一极性的信号，引脚104-1B承载具有第二极性的信号，引脚104-2A承载具有第二极性的信号，并且引脚104-2B承载具有第一极性的信号。引脚104的靠近IC 110的部分108一般是相互平行的。引脚104中的至少一个引脚(例如引脚104-2B)的末端109比引脚104的其它引脚延伸得更长。所述的至少一个引脚104-2B还沿着朝向相邻引脚(例如引脚104-2A)的方向延伸。在一些实现方式中，所述的至少一个引脚104-2B延伸成平行的路径110，如图4所示，路径110由相邻的引脚104-2A定义。在一些实现方式中，至少一个引脚104-2B具有大体上是“L”形的构造。
键合丝114-1A、114-1B，114-2A和114-2B分别将引脚104-1A、104-1B、104-2A和104-2B连接到焊盘116-1A、116-1B、116-2B和116-2A。因此，焊盘116-1A、116-1B、116-2A和116-2B现在分别连接到第一极性、第二极性、第一极性和第二极性。换言之，键合丝114-2A和114-2B的方位相对于引脚104-2A和104-2B的方位发生了翻转。由于如图4所示的封装设置的结果，对之间例如在120和122处的耦合由于部分的抵消而降低了。引脚框架可能包括与图4中用虚线表示的那些相似的一组或多组引脚。
现在参照图5，当耦合降低时，由于引脚框架的引脚通常比键合丝长，所以耦合抵消是不完全的。为了提高抵消，根据本发明的一些实现方式的封装使用高速引脚，这些高速引脚比承载更低速信号(例如，但不限于，控制和/或状态信号)的引脚短。引脚框架150可能包括一组或多组高速引脚102-1和102-2以及一组或多组低速引脚152。高速引脚102-1和102-2具有末端156-1和156-2，末端156-1和156-2与IC 110至少间隔距离H，而低速引脚与IC 110间隔距离L，其中H＞L。低速引脚152比高速引脚102-1和102-2延伸得更长。更短的高速引脚102-1和102-2趋于提高耦合抵消。低速引脚152更长并且需要更短的键合丝，这趋于降低键合丝的成本。
现在参照图6A和6B，差分信号对由引脚框架的引脚和两个或更多个堆叠的(stacked)键合丝连接到IC的焊盘。引脚框架200包含一组引脚202，该组引脚202包括第一对引脚204-1A和204-1B以及第二对引脚204-2A和204-2B(共同称为引脚204)。引脚204-1A位于与引脚204-1B相邻处，引脚204-1B位于与引脚204-2A相邻处，并且引脚204-2A位于与引脚204-2B相邻处。
分别地，引脚204-1A承载具有第一极性的信号，引脚204-1B承载具有第二极性的信号，引脚204-2A承载具有第二极性的信号，并且引脚204-2B承载具有第一极性的信号。引脚204的靠近IC 210的末端部分一般是相互平行的。引脚204中的至少一个引脚(例如引脚204-2B)比引脚204的其它引脚延伸得更长。所述的至少一个引脚204也沿着朝向相邻引脚(例如引脚204-2A)的方向延伸。在一些实现方式中，所述的至少一个引脚204延伸成平行的路径，如图6A所示，该路径由相邻的引脚204定义。可以使用另外的高速引脚和/或低速引脚组。
键合丝214-1A1和214-1A2、214-1B1、214-1B2、214-2A1、214-2A2以及214-2B1和214-2B2(共同称为键合丝214)分别将引脚204-1A、204-1B、204-2A和204-2B连接到焊盘216-1A1和216-1A2、216-1B1和216-1B2、216-2A1和216-2A2以及216-2B1和216-2B2。因此，焊盘216-1A1和216-1A2、216-1B1和216-1B2、216-2A1和216-2A2，以及216-2B1和216-2B2(共同称为焊盘216)现在分别连接到第一极性、第二极性、第一极性和第二极性。键合丝214的末端可能以隔开的和/或重叠关系附接到引脚204。焊盘216可由外部和/或内部通孔(via)和/或迹线(trace)230连接在一起。
堆叠的键合丝214的好处包含增加的键合丝电容。堆叠的键合丝214之间的键合丝耦合增加了。每单位长度的键合丝电容与单元长度的引脚框架电容更加接近。堆叠的键合丝214的每键合丝单元长度还具有更低的电感。在正负管脚(pin)之间的信号管脚对还具有更低的净传输线阻抗。由于堆叠的键合丝更高的匹配特性，引脚框架还具有更高的耦合抵消。
现在参照图7，集成电路管芯300包括串行器/并行器(SERDES)模块301，该串行器/并行器模块301根据本发明接收差分收发对上的信号。在一些实现方式中，SERDES模块301的高速差分对以大于或等于1Gb/s的速度进行操作。
现在参照图8，根据本发明网络接口IC 350包括使用高速封装的差分对。在一些实现方式中，网络接口的高速差分对以大于或等于1Gb/s的速度进行操作。在一些实现方式中，网络接口的高速差分对以大于或等于10Gb/s的速度进行操作。在一些实现方式中，网络接口包含物理层设备(PHY)。在其他的实现方式中，网络接口包含媒体访问控制器(MAC)。在其他的实现方式中，网络接口遵从1Gb/s和10Gb/s以太网协议。
现在参照图9A-9G，示出了本发明的各种示例性的实现方式。现在参照图9A，本发明可以在硬盘驱动器400中实现。本发明可实现信号处理电路和控制电路中的任一个或两者，所述信号处理和/或控制电路在图9A中的402处一般性地标识出来。在一些实现方式中，HDD 400中的信号处理和/或控制电路402和/或其他电路(没有示出)可处理数据、执行编码和/或加密、执行计算以及/或者格式化输出到磁性存储介质406并且/或者从磁性存储介质406接收的数据。
HDD 400可能通过一个或多个有线或无线通信链路408与主机设备(没有示出)进行通信，主机设备例如是计算机、移动计算设备(例如个人数字助理、便携式电话、媒体或MP3播放器等等)以及/或者其他设备。HDD 400可能被连接到存储器409例如随机存取存储器(RAM)、低延迟非易失性存储器例如闪存、只读存储器(ROM)和/或其他合适的电子数据存储设备。
现在参照图9B，本发明可以在数字通用光盘(DVD)驱动器410中实现。本发明可实现DVD驱动器410的信号处理电路和控制电路中的任一个或两者以及/或者大容量数据存储设备，所述信号处理和/或控制电路在图9B中的412处一般性地标识出来。DVD 410中的信号处理和/或控制电路412和/或其他电路(没有示出)可能处理数据、执行编码和/或加密、执行计算以及/或者格式化从光存储介质416读取并且/或者写入到光存储介质416的数据。在一些实现方式中，DVD 410中的信号处理和/或控制电路412和/或其他电路(没有示出)还可以执行其他功能，例如编码和/或译码和/或任何其他与DVD驱动器相关联的信号处理功能。
DVD驱动器410可能通过一个或多个有线或无线通信链路417与输出设备(没有示出)进行通信，输出设备例如是计算机、电视机或其他设备。DVD 410可能与以非易失性方式存储数据的大容量数据存储设备418进行通信。大容量数据存储设备418可能包括硬盘驱动器(HDD)。HDD可能具有如图9A所示的配置。HDD可能是包括一个或多个盘片(platter)的小型HDD，这些盘片具有大约比1.8″小的直径。DVD 410可能被连接到存储器419例如RAM、ROM、低延迟非易失性存储器例如闪存和/或其他合适的电子数据存储设备。
现在参照图9C，本发明可以在高清晰度电视(HDTV)420中实现。本发明可实现HDTV 420的信号处理电路和控制电路中的任一个或两者，WLAN接口以及/或者大容量数据存储设备，所述信号处理和/或控制电路在图9C的422处一般性地标识出来。HDTV 420以有线或者无线的格式接收HDTV输入信号并且为显示器426生成HDTV输出信号。在一些实现方式中，HDTV 420的信号处理电路和/或控制电路422和/或其他电路(没有示出)可能处理数据、执行编码和/或加密、执行计算、格式化数据以及/或者执行可能需要的任何其他类型的HDTV处理。
HDTV 420可能与以非易失性方式存储数据的大容量数据存储设备427进行通信，大容量数据存储设备427例如是光和/或磁性存储设备。至少一个HDD可能具有如图9A所示的配置并且/或者至少一个DVD可能具有如图9B所示的配置。HDD可能是包括一个或多个盘片的小型HDD，这些盘片具有大约比1.8″小的直径。HDTV 420可能被连接到存储器428例如RAM、ROM、低延迟非易失性存储器例如闪存和/或其他合适的电子数据存储设备。HDTV 420可能还支持通过WLAN网络接口429与WLAN连接。
现在参照图9D，本发明实现车辆430的控制系统、该车辆控制系统的WLAN接口和/或大容量数据存储设备。在一些实现方式中，本发明实现动力传动(powertrain)控制系统432，动力传动控制系统432从一个或多个传感器接收输入并且/或者生成一个或多个输出控制信号，传感器例如是温度传感器、压力传感器、转动传感器、气流传感器和/或其他合适的传感器，输出控制信号例如是引擎操作参数、传送操作参数和/或其他控制信号。
本发明可能还在车辆430的其他控制系统440中实现。控制系统440可能同样从输入传感器442接收信号并且/或者将控制信号输出到一个或多个输出设备444。在一些实现方式中，控制系统440可能是防锁刹车系统(ABS)、导航系统、信息通讯系统(telematics system)、车辆信息通讯系统、车道偏离系统、适应性巡航控制系统、车辆娱乐系统例如立体声系统、DVD、压缩唱片等等中的部分。还考虑到了其他的实现方式。
动力传动控制系统432可能与以非易失性方式存储数据的大容量数据存储设备446进行通信。大容量数据存储设备446可能包括光和/或磁性存储设备，例如，硬盘驱动器HDD和/或DVD。至少一个HDD可能具有如图9A所示的配置并且/或者至少一个DVD可能具有如图9B所示的配置。HDD可能是包括一个或多个盘片的小型HDD，这些盘片具有大约比1.8″小的直径。动力传动控制系统432可能被连接到存储器447例如RAM、ROM、低延迟非易失性存储器例如闪存和/或其他合适的电子数据存储设备。动力传动控制系统432可能还支持通过WLAN网络接口448与WLAN连接。控制系统440可能还包括大容量数据存储设备，存储器和/或WLAN接口(所有的都没示出)。
现在参照图9E，本发明可以在可包括便携式天线451的便携式电话450中实现。本发明可实现便携式电话450的信号处理电路和控制电路中的任一个或两者，WLAN接口和/或大容量数据存储设备，所述信号处理和/或控制电路在图9E中的452处一般性地标识出来。在一些实现方式中，便携式电话450包括麦克风456、音频输出458例如扬声器和/或音频输出插口、显示器460和/或输入设备462，输入设备462例如是键盘(keypad)、点选设备(pointing device)、声音致动装置(voiceactuation)和/或其他输入设备。便携式电话450中的信号处理和/或控制电路452和/或其他电路(没有示出)可能处理数据、执行编码和/或加密、执行计算、格式化数据以及/或者执行其他便携式电话功能。
便携式电话450可能与以非易失性方式存储数据的大容量数据存储设备464进行通信，大容量数据存储设备464例如是光和/或磁性存储设备，例如硬盘驱动器HDD和/或DVD。至少一个HDD可能具有如图9A所示的配置并且/或者至少一个DVD可能具有如图9B所示的配置。HDD可能是包括一个或多个盘片的小型HDD，这些盘片具有大约比1.8″小的直径。便携式电话450可能被连接到存储器466例如RAM、ROM、低延迟非易失性存储器例如闪存和/或其他合适的电子数据存储设备。便携式电话450还可能支持通过WLAN网络接口468与WLAN连接。
现在参照图9F，本发明可以在机顶盒480中实现。本发明可实现机顶盒480的信号处理电路和控制电路中的任一个或两者，WLAN接口和/或大容量数据存储设备，所述信号处理和/或控制电路在图9F中的484处一般性地标识出来。机顶盒480从源(source)例如宽带源接收信号并且输出适合显示器488的标准和/或高清晰度音频/视频信号，显示器488例如是电视机和/或监视器和/或其他视频和/或音频输出设备。机顶盒480的信号处理和/或控制电路484和/或其他电路(没有示出)可能处理数据、执行编码和/或加密、执行计算、格式化数据以及/或者执行任何其他机顶盒功能。
机顶盒480可能与以非易失性方式存储数据的大容量数据存储设备490进行通信。大容量数据存储设备490可能包括光和/或磁性存储设备例如硬盘驱动器HDD和/或DVD。至少一个HDD可能具有如图9A所示的配置并且/或者至少一个DVD可能具有如图9B所示的配置。HDD可能是包括一个或多个盘片的小型HDD，这些盘片具有大约比1.8″小的直径。机顶盒480可能被连接到存储器494例如RAM、ROM、低延迟非易失性存储器例如闪存和/或其他合适的电子数据存储设备。机顶盒480也可能支持通过WLAN网络接口496与WLAN连接。
现在参照图9G，本发明可以在媒体播放器500中实现。本发明可实现媒体播放器500的信号处理电路和控制电路中的任一个或两者，WLAN接口和/或大容量数据存储设备，所述信号处理和/或控制电路在图9G中的504处一般性地标识出来。在一些实现方式中，媒体播放器500包括显示器507和/或用户输入设备508例如键盘、触摸盘(touchpad)等等。在一些实现方式中，媒体播放器500可能使用图形用户界面(GUI)，图形用户界面通常通过显示器507和/或用户输入设备508来使用菜单、下拉菜单、图标和/或点击(point-and-click)接口。媒体播放器500还包括音频输出设备509例如扬声器和/或音频输出插口。媒体播放器500的信号处理和/或控制电路504和/或其他电路(没有示出)可能处理数据、执行编码和/或加密、执行计算、格式化数据以及/或者执行任何其他媒体播放器功能。
媒体播放器500可能与以非易失性方式存储诸如压缩的音频和/或视频内容之类的数据的大容量数据存储设备510进行通信。在一些实现方式中，压缩的音频文件包括遵从MP3格式或其他合适的压缩音频和/或视频格式的文件。大容量数据存储设备可能包括光和/或磁性存储设备例如硬盘驱动器HDD和/或DVD。至少一个HDD可能具有如图9A所示的配置并且/或者至少一个DVD可能具有如图9B所示的配置。HDD可能是包括一个或多个盘片的小型HDD，这些盘片具有大约比1.8″小的直径。媒体播放器500可能被连接到存储器514例如RAM、ROM、低延迟非易失性存储器例如闪存和/或其他合适的电子数据存储设备。媒体播放器500还可能支持通过WLAN网络接口516与WLAN连接。还考虑到了除上述那些之外的其他实现方式。
现在参照图10A，示出了包括集成电路管芯611和具有不规则间隔引脚的引脚框架612的封装。引脚框架612包含一组或多组引脚，这些引脚包括引脚620-1、620-2、620-3和620-4，以及第一对引脚620-5A和620-5B以及第二对引脚620-6A和620-6B(共同称为引脚620)。
键合丝616-1、616-2、616-3、616-4、616-5A和616-5B以及616-6A和616-6B分别将引脚620-1、620-2、620-3、620-4、620-5A和620-5B以及620-6A和620-6B连接到焊盘614-1、614-2、614-3、614-4、614-5A和614-5B以及614-6A和614-6B。
引脚620-1、620-2、620-3和620-4可能是控制引脚，控制引脚以比高速进行操作的引脚620-5A和620-5B以及620-6A和620-6B低的速度进行操作。引脚620-5A和620-5B以及620-6A和620-6B可能承载差分信号。低速引脚之间的间距可能等于d1。一对高速引脚中引脚之间的间距可能等于d4。低速引脚和高速引脚之间的间距可能是d2。高速引脚对之间的间距可能是d3。间距d1、d2、d3和d4可能是不规则的，以增加或减少耦合。例如，间距d4可能比间距d3小。间距d4可能比间距d1小。
现在参照图10B，示出了包括具有不规则隔开引脚和接地引脚的引脚框架的封装。引脚640位于高速引脚对之间并且被连接到参考电压例如地来减少耦合。引脚640可能或者可能没有被连接到集成电路管芯。可以理解到，图10A和10B中的引脚框架可能包含交叉以及其他上述的属性。
现在参照图11A-11C，用于集成电路管芯611的封装包括引脚框架612。导电带(conductive tape)650被应用于引脚框架612的引脚620的至少一侧。例如，导电带可能被连接到引脚的上侧、引脚的下侧或者引脚的上侧和下侧两者。导电带还可被应用于一些引脚而非其他引脚。导电带650包括内部绝缘粘合层654和外部导电层656。绝缘层654防止将引脚短路。绝缘粘合层654连接到引脚620。在图11C中，导电带650可能包括隔开的穿孔以允许封装材料在生产期间通过穿孔流动，这增加了强度。导电层656提供传导磁通量的接地平面，这样减少了耦合。
现在参照图12A-12D，示出了各种交叉配置。在图12A和图12B中，交叉730包括第一引脚732-A，引脚732-A包括通过键合丝734连接的第一部分732-A1和第二部分732-A2。第二引脚732-B包括第一部分732-B1、中间部分732-B2和第二部分732-B3。第一部分732-B1与第二部分732-A2共线。第二部分732-B3与第一部分732-A1共线。中间部分732-B2相对于第一和第二部分732-B1和732-B3是倾斜的。中间部分732-B2还可能是弯曲的。
在图12C中，交叉750包括第一引脚752-A，引脚752-A包括通过键合丝754连接的第一部分752-A1和第二部分752-A2。第二引脚752-B具有第一部分752-B1、中间部分752-B2和第二部分752-B3。第一部分752-B1与第二部分752-A2共线。第二部分752-B3与第一部分752-A1共线。中间部分752-B2与第一和第二平直部分752-B1和752-B3成直角。中间部分可能还具有其他适合的形状。
在图12D中，一对引脚760包括第一和第二引脚762和764，第一和第二引脚762和764都具有第一(标示-1)部分、中间(标示-2)部分和第二(标示-3)部分。至少一个引脚的中间部分是沿与包含引脚的平面垂直的方向弯曲的，以提供另一引脚从上方或下方通过的空间。中间部分764-2向上弯曲然后向下返回，以为平面的中间部分762-2提供空间。还想到了用于进行交叉的其他变体。
现在参照图13A和图13B，示出了各种封装技术。在图13A中，示出了包括球栅面阵列衬底的集成电路封装800的侧面视图。封装800包括集成电路管芯801。封装材料可以用来保护封装800的一个或多个组件。可以用诸如键合丝、倒装芯片(flip chip)以及/或者卷带自动键合(TapeAutomated Bonding，TAB)之类的互连802将集成电路管芯801连接到球栅面阵列衬底804。球栅面阵列衬底804上的焊锡突起(solder bump)806与印刷电路板812或者其他衬底或安装表面的安装焊盘810对准。在图13B中，集成电路封装815包括附接到衬底804上的倒装芯片或集成电路管芯816。衬底804可能包括与倒装芯片816的焊锡球817对准的安装焊盘818。
现在参照图13C，示出了一种示例性的BGA封装方法830更详细的横截面视图。球栅面阵列衬底834包括铜图案层835，铜图案层835定义衬底核心840的一侧或两侧的迹线、通孔和安装焊盘。键合丝854可被用来将一个或多个迹线或安装焊盘849连接到集成电路管芯848上的安装焊盘850。通孔836提供到BGA衬底834另一侧的连接。BGA衬底的下表面上的安装焊盘853由铜图案层来定义并且接纳焊锡突起844。焊锡掩模板855可能被应用于铜层836。根据本发明交叉或者跳线与BGA衬底结合，这将在下面描述。
现在参照图14A，示出了说明用于高速迹线874、876和878的BGA跳线870的平面视图。迹线874包含第一部分874-1、第二部分874-2和第三部分874-3(共同称为迹线874)。迹线876和878通过通孔880和882被连接到BGA衬底834的另一侧。BGA衬底834对面表面上的交叉迹线883将通孔880和882连接起来。可通过在BGA衬底的底面上加入组合层(buildup layer)而创建交叉迹线883。可以理解到，如上所述，交叉迹线可能具有其他形状和/或构造。
现在参照图14B，示出了说明BGA跳线870的简化横截面视图。通孔880和882在910处共同标识出来。通孔910在迹线876和878(在904处共同标识出来)与迹线或跳线883之间提供连接。
现在参照图15A-15C，示出了说明可替换的BGA衬底930的简化横截面视图。交叉迹线(例如图14A所示的那些)形成于互连和迹线平面934中。在图15A中，BGA衬底930包括I&TP 934、电源平面938和接地平面942。衬底核心材料946和/或其他绝缘层可能位于I&TP 934、电源平面938和接地平面942之间。在图15A中，通孔950提供到交叉跳线或迹线954的连接，交叉跳线或迹线954与接地平面层942共面但是隔离。迹线954与接地平面层942的其余部分隔离。可以理解到，在图15A中示出和描述的结构消除了对图14A中的组合层或迹线883的需求。
在图15B中，通孔960提供到交叉跳线或迹线964的连接，交叉跳线或迹线964与电源平面层938共面但是隔离。迹线964与电源平面层的其余部分隔离。在图15C中，在电源平面938中示出了跳线或迹线964。衬底核心材料或其他绝缘材料可能被用在970处以使跳线或迹线964与电源平面938绝缘。通孔960-1和960-2与跳线或迹线964连接。
上面所示出的任何实施例都可能被如图1和图2所示的保护材料所包裹。本领域的技术人员现在可以从前面的描述中知道本发明的广泛教导可以以多种形式实现。因此，虽然本发明是连同其具体实例进行描述的，但是本发明的真正范围不应该那么有限，因为在研究过附图、说明书和所附权利要求书之后，其他的修改对于本领域技术人员来说就变得清楚了。

Claims (17)

1.一种集成电路封装，包含：
集成电路管芯，包含第一焊盘、与所述第一焊盘相邻的第二焊盘、与所述第二焊盘相邻的第三焊盘以及与所述第三焊盘相邻的第四焊盘，其中所述第一、第二、第三和第四焊盘对齐，并且其中所述第二焊盘位于所述第一焊盘和所述第三焊盘之间；
引脚框架，包含第一引脚、与所述第一引脚相邻的第二引脚、与所述第二引脚相邻的第三引脚以及与所述第三引脚相邻的第四引脚，并且其中所述第三引脚位于所述第二引脚和第四引脚之间；以及
第一、第二、第三和第四键合丝，将所述第一、第二、第三和第四引脚分别连接到所述第一、第二、第三和第四焊盘，
其中所述第一和第二引脚以及所述第三和第四引脚间隔第一距离并且所述第二和第三引脚间隔与所述第一距离不同的第二距离，并且其中所述第一引脚承载具有第一极性的信号，且所述第二引脚承载具有不同于所述第一极性的第二极性的信号。
2.如权利要求1所述的集成电路封装，其中所述第三引脚承载具有所述第一极性的信号并且所述第四引脚承载具有所述第二极性的信号，并且其中所述第一极性和第二极性是相反的极性。
3.如权利要求1所述的集成电路封装，其中所述引脚框架的所述第一和第二引脚以及所述第三和第四引脚承载具有大于或等于1吉比特每秒的频率的高速差分信号。
4.如权利要求1所述的集成电路封装，其中所述引脚框架还包含与所述第四引脚间隔第三距离的第五引脚，并且其中所述第三距离与所述第一和第二距离不同。
5.如权利要求4所述的集成电路封装，还包含与所述第五引脚间隔第四距离的第六引脚，其中所述第四距离与所述第一距离不同，并且其中所述第五和第六引脚承载控制信号。
6.如权利要求1所述的集成电路封装，还包含与所述第一、第二、第三和第四焊盘相连的串行器/并行器模块。
7.如权利要求6所述的集成电路封装，其中所述集成电路管芯的所述第一和第二焊盘与所述串行器/并行器模块的差分发送信号相关联，并且所述集成电路管芯的所述第三和第四焊盘与所述串行器/并行器模块的差分接收信号相关联。
8.如权利要求1所述的集成电路封装，还包含第五引脚，所述第五引脚位于所述第二和第三引脚之间并且与参考电压相连，但是不与所述集成电路管芯相连。
9.如权利要求1所述的集成电路封装，还包含附接于所述引脚框架的所述第一、第二、第三和第四引脚的导电带，其中所述导电带包含导电层和与所述第一、第二、第三和第四引脚接触的绝缘粘合层。
10.如权利要求9所述的集成电路封装，其中所述导电带包含多个隔开的穿孔。
11.如权利要求10所述的集成电路封装，还包含与所述集成电路管芯、所述导电带、所述引脚框架和所述键合丝接触的封装材料。
12.一种网络接口，包含如权利要求1所述的集成电路封装，其中所述网络接口是遵从以太网的并且以大于1吉比特每秒的速度进行操作。
13.一种集成电路封装，包含：
集成电路管芯，包含N个焊盘，其中N是大于一的整数；
引脚框架，包含N个相邻的引脚；
N个连接装置，独立地将所述N个引脚分别连接到所述N个焊盘；以及
第一材料，包含绝缘层和导电层，其中所述绝缘层被粘合地设置在所述引脚框架的所述N个引脚上，
其中所述N个相邻的引脚中的第一引脚承载具有第一极性的信号，并且所述N个相邻的引脚中的第二引脚承载具有第二极性的信号，其中所述第一引脚与所述第二引脚相邻，并且所述第一极性和第二极性是相反的极性。
14.如权利要求13所述的集成电路封装，其中所述N个连接装置包含N根键合丝。
15.如权利要求13所述的集成电路封装，其中所述第一材料包含多个隔开的穿孔。
16.如权利要求14所述的集成电路封装，还包含与所述集成电路管芯、所述第一材料、所述引脚框架和所述N根键合丝接触的封装材料。
17.如权利要求13所述的集成电路封装，其中所述第一材料包含导电带。
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CN1933135A (zh) 2007-03-21
CN100550361C (zh) 2009-10-14
US20070018288A1 (en) 2007-01-25
US7638870B2 (en) 2009-12-29
US20070018305A1 (en) 2007-01-25
US20070018293A1 (en) 2007-01-25
CN1933138A (zh) 2007-03-21
CN100565866C (zh) 2009-12-02
US20070096277A1 (en) 2007-05-03
US20070018292A1 (en) 2007-01-25
US7884451B2 (en) 2011-02-08
US20070018289A1 (en) 2007-01-25
US20070018294A1 (en) 2007-01-25
CN1933134A (zh) 2007-03-21

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