CN100524618C - 制造精细结构的无抗蚀剂光刻方法 - Google Patents

制造精细结构的无抗蚀剂光刻方法 Download PDF

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CN100524618C
CN100524618C CNB028258061A CN02825806A CN100524618C CN 100524618 C CN100524618 C CN 100524618C CN B028258061 A CNB028258061 A CN B028258061A CN 02825806 A CN02825806 A CN 02825806A CN 100524618 C CN100524618 C CN 100524618C
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H·特斯
R·菲哈伯
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Abstract

本发明系相关于一种制造精细结构的无阻光刻方法，一半导体遮幕层(HM)系被形成于一载体材质(TM、HM’)之上，以及一选择性离子植入(I)系加以实现，以对该半导体屏蔽层(HM)的被选择区域进行掺杂，湿化学移除该半导体屏蔽层(HM)的未掺杂区域系会产生一半导体屏蔽，而其系可被用于更进一步的图案化。透过此方法，则可以获得用于形成结构小于100nm之一简单且高精确度的无阻光刻方法。

Description

制造精细结构的无抗蚀剂光刻方法
技术领域
本发明涉及一种用于制造精细结构的无抗蚀剂光刻方法，以及，特别是涉及用于在一载体材质或半导体材质中制造次100nm(sub-100nm)结构的无抗蚀剂光刻方法。
背景技术
于发展可在一次100nm辖域(regime)中制造非常精细结构的适当光刻方法时，有非常大的问题会产生，特别是，由于所谓光刻系统的阻抗化学(resist chemistry)、掩模制造以及复杂度所造成者。
所谓的157nm光刻，其已经在用于在小于100nm的辖域中制造非常精细结构的光学光刻的更进一步的发展中加以达成，在此例子中，这些光刻方法需要新颖的阻抗材质，尽管经过非常密集的努力，迄今仍然没有任何能完全满足如此小的结构的技术需要的阻抗被发现，再者，除了这些新的材质外，新的掩模制造方法亦有所需要，并且，其发展是依次为高度成本密集，因此造成高度成本密集以及难以掌控的光刻系统。
作为此种已知光学光刻方法的另一个选择，举例而言，是一无掩模光刻方法，例如，一电子束直接写入光刻(electron beam direct writelithography，EBDW)，举例而言，因此已被导入，然而，再次地，需要一适合的阻抗。一实质上的有机暴露层，而较佳地是一聚合物。
其它已经揭示的选择是，举例而言，离子投射光刻(ion projectionlithography，IPL)，所谓的印刷模板掩模(stencil mask)，其被用于将结构映像在一特殊的阻抗材质上，然而，一适合的阻抗材质的制造，特别是，会不断地限制变得甚至更精细结构的实现。
文件EP-A-0321 144揭示一用于在一载体材质中制造精细结构的无抗蚀剂光刻方法，在此例子中，在准备完该载体材质后，首先，一半导体掩模层被形成为该载体材质上，并且，执行一选择性离子注入，以对该半导体掩模层的被选择区域进行掺杂，而在这之后紧跟着的是，对该半导体掩模层的该已掺杂或未掺杂区域执行一湿化学移除，以形成一半导体掩模，该载体材质最终利用该已图案化的半导体掩模而进行图案化。
文件JP 63051641揭示一图案化方法，氧可通过离子注入而被导入一多晶硅半导体层中，并且，一激光蚀刻是接续地为了图案化而加以实现，然而，在该次100nm辖域中，结果是，精细结构仅可以不适合地被形成。
再者，文件US 5,918,143揭示一种用于在该次100nm辖域中制造精细结构的无抗蚀剂光刻方法，一特殊的金属/半导体层可通过一聚焦的电子束进行曝光，并且，一图案化接续地加以实现，然而，在此例子中的缺点是，其对标准制造方法的高时间耗损以及低兼容性。
发明内容
因此，本发明是以提供能简单以及具成本效益地实现的用于制造精细结构的无抗蚀剂光刻的方法的目的作为基础。
根据本发明，此目的可以通过本发明所述的方法而加以达成。
特别是由于形成一硬掩模层以作为该载体材质的最上层，而该硬掩模层具有一TOES、SiO2、氮化物、SiC、或BPSG层，举例而言，因此，对位在下方的区域而言的一不需要掺杂可确实地被避免，而此结果，半导体组件的电特质因此实质上维持未受影响。
该半导体掩模层较佳地包含一非晶硅半岛体，而如此的结果是，该精细结构可以被非常准确地加以形成。然而，原则上，其有可能使用多晶质、或结晶质半导体层作为该半导体掩模层。
在结构精准度的更进一步改进，则可以于使用未掺杂或微量掺杂的半导体层作为该半导体掩模层且厚度介于10nm至20nm之间的情况下获得。
在取代阻抗的半导体掩模层的所谓曝光期间，实质上可实行一离子注入，而较佳地是垂直地使用，因而可以获得实现非常精细结构的良好结果，特别是关连于非常薄的层。举例而言，一具有一聚焦离子束的直接光刻写入，一利用一可程序化掩模的离子束光刻，或一利用一投射掩模的离子束光刻可以为了该选择性离子注入而加以实行。在每一个例子中，取决于所需的结构，则可以因此使用最佳化的曝光方法或离子束方法。再者，其有可能在此方法中有效率地制造在一半导体电路中的非常精细结构，以及同时制造所谓的具有迄今梦想不到的精细结构的印刷模板掩模或投射掩模。然而，更多的是，其有可能实现微机械构件或其它在半导体材质上所需的表面效果，在此例子中，用于掺杂半导体区域的该选择性离子注入以及该湿化学移除该已掺杂或未掺杂区域可以直接在一半导体材质或一半导体晶片中加以实现。
附图说明
本发明将利用接下来的示范性实施例并以图式做为参考而更详细地加以叙述。
在图中：
第1A图至第1E图：其显示用于举例依照一第一实施例的无抗蚀剂光刻方法的必要制造步骤的简化剖面图；
第2A图至第2E图：其显示用于举例依照一第二实施例的无抗蚀剂光刻方法的必要制造步骤的简化剖面图；
第3图：其显示用于举例依照一第三实施例的无抗蚀剂光刻方法的必要制造步骤的一简化剖面图。
具体实施方式
第1A图至第1E图显示依照一第一实施例的无抗蚀剂光刻方法的必要制造步骤的简化剖面图，在此例子中，根据第1A图，举例而言，在一可选择的用于平面化一载体材质TM的起伏(topology)的平坦化步骤之后，形成一薄硬掩模层HM’，该载体材质TM，举例而言，构成一Si晶片或Si半导体晶片，而在此例子中，其亦有可能使用所有更进一步的载体材质，以及，特别是，半导体材质，例如，III-V材质，举例而言。
举例而言，一TEOS、SiO2、氮化物、SiC、或BPSG层被形成作为该硬掩模层HM’或是作为该载体材质的最上层，然而，其有可能使用适用于一分别标准方法或一分别载体材质TM的更进一步硬掩模层。
根据第1A图，一半导体掩模层HM接着被形成于该载体材质或该硬掩模层HM’上，以作为该最上层，较佳地是，一薄非晶形半导体层，例如，将具有厚度10nm至20nm的一硅半导体层于温度500至600度C时进行沉积，然而，其亦有可能使用其它的材质，以用于形成该半导体掩模层，可以因此而加以产生。特别地是，该半导体掩模层的具有小的层厚度的该垂直注入与先前所提及的能量间的相互影响使得光刻制造精细结构可以达成迄今无法达成者。
上述的p掺杂较佳地产生在未掺杂或微量p掺杂的半导体掩模层HM中，然而，在相同的方法中，在未掺杂或微量p掺杂的半导体掩模层HM中的n型掺质或用于掺杂该半导体掩模层HM的相反的掺质亦有可能。
不同型态的聚焦离子束方法对上述直接写入到该半导体掩模层HM者而言，为有可能。
举例而言，在所谓的单源-单束(single source-single beam)方法中，单一离子束可以通过单一离子源而加以产生并且被用于写入至该半导体掩模层，再者，所谓的单源-多束(single source-multiple beam)方法亦为可能，然而，在其中，离子束的多重性可以通过单一离子源而加以产生，并且，接着被用于写入至该半导体掩模层。作为此使用一聚焦离子束的局部离子注入方法的更进一步选择，其有可能使用所谓的多源-单束方法，离子源的多重性被用于产生单一离子束，而其接着被用于平行写入至该半导体掩模层。另外，其有可能使用所谓的多源-多束方法，其中，离子源的多重性被用于产生离子束的多重性，而其接着平行写入至该半导体掩模层HM。
根据第2D图，在一接续的步骤中，该氧化掩模或该已氧化的区域1’被移除，并且，一非等向性蚀刻方法，例如，活性离子蚀刻(RIE)，再次地加以实行，以有关于该硬掩模层HM’而对该多晶硅层5进行选择性地蚀刻，而结果是可以获得在第2D图中所图例的该闸极结构。
在此方法中，一半导体电路中，任意的小结构皆可以通过一自由的可选择方式，亦即光刻，而加以制造，在此状况下，该等结构亦可以彼此非常的接近在一起，再者，此无抗蚀剂光刻方法使得一格外快速以及干净的图案化成为可能，特别地是，当使用聚焦离子束时，所谓的曝光时间、以及因此将被形成的具有减少的结构尺寸的该精细结构的制造时间会有所减少。
然而，上述的方法不仅可以被用作为一制造在半导体电路中的精细结构的光刻方法，其亦可以，举例而言，用于制造在投射掩模或所谓的印刷模板掩模中的精细结构。
第3图显示依照一第三实施例的一无抗蚀剂光刻方法的一必要制造步骤的一简化剖面图，一样的，相同的参考符号代表相同或相对应的组件或层，并且，一重复的叙述则于后加以省略。
通常，在一半导体材质中如第3图所举例说明的严重起伏(topology)不同会于，特别是已知的光学光刻方法中，引起相当大的问题，因为在不同平面中鲜明的成像为不可能、或仅在非常大的困难度下有可能。而根据在第1图至第2图中所举例说明的无抗蚀剂光刻方法，被选择的区域1现在可以被非常精确地进行掺杂，即使是在不同的平面中，并且，一格外精确的半导体掩模则因此而可以加以提供。
本发明的叙述是以硅半导体层作为基础，然而，其并受限于此，并且相同的包含其它的材质。同样的，除了闸极结构以外的结构亦可以被制造在半导体电路中，相同的，除了硼或BF2注入以及NH4OH蚀刻之外，另外的离子束、或，同样的，另外的湿化学蚀刻方法亦为可能。
参考符号列表
1   已掺杂区域
2   在硬掩模层中的被注入区域
3   半导体晶片
4   闸极氧化层
5   多晶硅层
HM’硬掩模层
TM  载体材质
HM  半导体掩模层
O   开口

Claims (17)

1.一种用于在一载体材质中制造精细结构的无抗蚀剂光刻方法，其包括下列步骤：
a)准备该载体材质(TM、HM’)，形成一硬掩模层(HM’)以作为该载体材质(TM)的最上层；
b)于该载体材质(TM、HM’)上形成一半导体掩模层(HM)；
c)实行一选择性离子注入(I)，以对该半导体掩模层(HM)的被选择区域进行掺杂；
d)湿化学移除该半导体掩模层(HM)的该已掺杂或未掺杂(HM)区域(1)，以形成一半导体掩模；以及
e)利用该已图案化的半导体掩模，实行该载体材质(TM、HM’)的一图案化。
2.根据权利要求第1项所述的方法，其特征在于，形成一TOES、SiO2、氮化物、SiC、或BPSG层，以作为该硬掩模层(HM’)。
3.根据权利要求第2项所述的方法，其特征在于，在该步骤a)中，对该载体材质(TM、HM’)执行一平坦化。
4.根据权利要求第1项所述的方法，其特征在于，在该步骤a)中，对该载体材质(TM、HM’)执行一平坦化。
5.根据权利要求第1项所述的方法，其特征在于，在该步骤b)中，形成一非晶形、多晶质、或结晶质半导体层。
6.根据权利要求第2项所述的方法，其特征在于，在该步骤b)中，形成一非晶形、多晶质、或结晶质半导体层。
7.根据权利要求第1至第6项中任一项所述的方法，其特征在于，在该步骤b)中，形成一未掺杂或微量p-掺杂的半导体层。
8.根据权利要求第7项所述的方法，其特征在于，在该步骤c)中，实行利用一可程序化掩模的离子束光刻。
9.根据权利要求第1至第6项中任一项所述的方法，其特征在于，在该步骤b)中，该半导体掩模层(HM)被形成为具有厚度10nm至20nm。
10.根据权利要求第9项所述的方法，其特征在于，在该步骤c)中，实行利用一可程序化掩模的离子束光刻。
11.根据权利要求第1项所述的方法，其特征在于，在该步骤c)中，该离子注入(I)实质上垂直于该半导体掩模层(HM)而加以实现。
12.根据权利要求第1项所述的方法，其特征在于，在该步骤c)中，利用一聚焦离子束实行直接光刻写入。
13.根据权利要求第12项所述的方法，其特征在于，
步骤c)中所述聚焦离子束可通过一单源-单束方法、或一单源-多束方法、或一多源-单束方法、或一多源-多束方法来提供。
14.根据权利要求第1至第6项以及第11至12项中任一项所述的方法，其特征在于，在该步骤c)中，实行一利用一可程序化掩模的离子束光刻。
15.根据权利要求第1至第6项以及第11至13项中任一项所述的方法，其特征在于，在该步骤c)中，实行一利用一投射掩模的离子束光刻。
16.根据权利要求第1至第6项中任一项所述的方法，其特征在于，在该步骤b)中，未掺杂的半导体材质被形成做为一半导体掩模层，并且，在该步骤d)中，实行一NH4OH湿蚀刻方法，以利用一大于100的选择性来移除该半导体掩模层(HM)的该未掺杂区域。
17.根据权利要求第1项所述的方法，其特征在于，在该步骤e)中，实行一非等向性蚀刻方法。
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