JPS56116626A - Pattern formation - Google Patents

Pattern formation

Info

Publication number
JPS56116626A
JPS56116626A JP1908380A JP1908380A JPS56116626A JP S56116626 A JPS56116626 A JP S56116626A JP 1908380 A JP1908380 A JP 1908380A JP 1908380 A JP1908380 A JP 1908380A JP S56116626 A JPS56116626 A JP S56116626A
Authority
JP
Japan
Prior art keywords
pattern
si3n4
sio2
etching speed
pattern formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1908380A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Hideo Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP1908380A priority Critical patent/JPS56116626A/en
Publication of JPS56116626A publication Critical patent/JPS56116626A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain a predetermined shaped pattern by diagrammatically irradiating lights or electron beams on the surface of a semiconductor material, a dielectric material or a metallic material wherein etching speed is selectively changed. CONSTITUTION:With an amorphous film 2 such as of Si or SiO2, Si3N4 or the like formed on an Si wafer 1 and with laser lights 3, 4 partially irradiated, parts 5, 6 are monocrystallized by Si and become high density by SiO2 or Si3N4 to reduce etching speed to 1/3 or below. The same effect will be obtained by a metal film such as Al. Then, a desired pattern will be obtained by photoetching. In this composition, a pattern will be formed without a resist and pattern accuracy will be improved.
JP1908380A 1980-02-20 1980-02-20 Pattern formation Pending JPS56116626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1908380A JPS56116626A (en) 1980-02-20 1980-02-20 Pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1908380A JPS56116626A (en) 1980-02-20 1980-02-20 Pattern formation

Publications (1)

Publication Number Publication Date
JPS56116626A true JPS56116626A (en) 1981-09-12

Family

ID=11989546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1908380A Pending JPS56116626A (en) 1980-02-20 1980-02-20 Pattern formation

Country Status (1)

Country Link
JP (1) JPS56116626A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142529A (en) * 1982-02-18 1983-08-24 Mitsubishi Electric Corp Manufacture of semiconductor element
DE10163346A1 (en) * 2001-12-21 2003-07-10 Infineon Technologies Ag Resistless lithography process for the production of fine structures
CN105097537A (en) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 Forming method of fin type field effect transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58142529A (en) * 1982-02-18 1983-08-24 Mitsubishi Electric Corp Manufacture of semiconductor element
DE10163346A1 (en) * 2001-12-21 2003-07-10 Infineon Technologies Ag Resistless lithography process for the production of fine structures
US7318993B2 (en) 2001-12-21 2008-01-15 Infineon Technologies Ag Resistless lithography method for fabricating fine structures
CN105097537A (en) * 2014-05-12 2015-11-25 中芯国际集成电路制造(上海)有限公司 Forming method of fin type field effect transistor
CN105097537B (en) * 2014-05-12 2019-09-27 中芯国际集成电路制造(上海)有限公司 The forming method of fin field effect pipe

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