CN100499068C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN100499068C
CN100499068C CNB2005101063761A CN200510106376A CN100499068C CN 100499068 C CN100499068 C CN 100499068C CN B2005101063761 A CNB2005101063761 A CN B2005101063761A CN 200510106376 A CN200510106376 A CN 200510106376A CN 100499068 C CN100499068 C CN 100499068C
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CN
China
Prior art keywords
film
conductive layer
interlayer insulating
etching
stopper film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005101063761A
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English (en)
Chinese (zh)
Other versions
CN1758425A (zh
Inventor
上杉胜洋
片山克生
酒井克尚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Renesas Electronics Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Publication of CN1758425A publication Critical patent/CN1758425A/zh
Application granted granted Critical
Publication of CN100499068C publication Critical patent/CN100499068C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
CNB2005101063761A 2004-09-22 2005-09-22 半导体装置及其制造方法 Expired - Fee Related CN100499068C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004275565A JP2006093330A (ja) 2004-09-22 2004-09-22 半導体装置およびその製造方法
JP2004275565 2004-09-22

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN200910139117A Division CN101546748A (zh) 2004-09-22 2005-09-22 半导体装置及其制造方法

Publications (2)

Publication Number Publication Date
CN1758425A CN1758425A (zh) 2006-04-12
CN100499068C true CN100499068C (zh) 2009-06-10

Family

ID=36074618

Family Applications (2)

Application Number Title Priority Date Filing Date
CNB2005101063761A Expired - Fee Related CN100499068C (zh) 2004-09-22 2005-09-22 半导体装置及其制造方法
CN200910139117A Pending CN101546748A (zh) 2004-09-22 2005-09-22 半导体装置及其制造方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN200910139117A Pending CN101546748A (zh) 2004-09-22 2005-09-22 半导体装置及其制造方法

Country Status (5)

Country Link
US (3) US7301237B2 (enExample)
JP (1) JP2006093330A (enExample)
KR (1) KR20060051496A (enExample)
CN (2) CN100499068C (enExample)
TW (1) TW200618177A (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070293034A1 (en) * 2006-06-15 2007-12-20 Macronix International Co., Ltd. Unlanded via process without plasma damage
US9391020B2 (en) * 2014-03-31 2016-07-12 Stmicroelectronics, Inc. Interconnect structure having large self-aligned vias

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976984A (en) * 1997-10-29 1999-11-02 United Microelectronics Corp. Process of making unlanded vias
CN1426600A (zh) * 2000-04-28 2003-06-25 东京毅力科创株式会社 具有低介电膜的半导体器件及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953188B2 (ja) 1992-04-24 1999-09-27 日本電気株式会社 半導体装置の製造方法
JP3297220B2 (ja) * 1993-10-29 2002-07-02 株式会社東芝 半導体装置の製造方法および半導体装置
JPH097970A (ja) 1995-06-21 1997-01-10 Sanyo Electric Co Ltd 半導体装置の製造方法
JP2000294631A (ja) 1999-04-05 2000-10-20 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR100303366B1 (ko) * 1999-06-29 2001-11-01 박종섭 반도체 소자의 배선 형성방법
JP2002009152A (ja) * 2000-06-21 2002-01-11 Nec Corp 半導体装置及びその製造方法
US20030148618A1 (en) * 2002-02-07 2003-08-07 Applied Materials, Inc. Selective metal passivated copper interconnect with zero etch stops

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5976984A (en) * 1997-10-29 1999-11-02 United Microelectronics Corp. Process of making unlanded vias
CN1426600A (zh) * 2000-04-28 2003-06-25 东京毅力科创株式会社 具有低介电膜的半导体器件及其制造方法

Also Published As

Publication number Publication date
CN101546748A (zh) 2009-09-30
TW200618177A (en) 2006-06-01
US7465662B2 (en) 2008-12-16
US20080045006A1 (en) 2008-02-21
US7301237B2 (en) 2007-11-27
CN1758425A (zh) 2006-04-12
KR20060051496A (ko) 2006-05-19
US20060063372A1 (en) 2006-03-23
JP2006093330A (ja) 2006-04-06
US20090137114A1 (en) 2009-05-28

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Owner name: NEC CORP.

Free format text: FORMER OWNER: RENESAS TECHNOLOGY CORP.

Effective date: 20100917

C41 Transfer of patent application or patent right or utility model
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Owner name: RENESAS ELECTRONICS

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Free format text: CORRECT: ADDRESS; FROM: TOKYO, JAPAN TO: KANAGAWA, JAPAN

CP01 Change in the name or title of a patent holder

Address after: Kanagawa, Japan

Patentee after: Renesas Electronics Corp.

Address before: Kanagawa, Japan

Patentee before: NEC ELECTRONICS Corp.

TR01 Transfer of patent right

Effective date of registration: 20100917

Address after: Kanagawa, Japan

Patentee after: NEC ELECTRONICS Corp.

Address before: Tokyo, Japan

Patentee before: Renesas Technology Corp.

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090610

Termination date: 20130922