CN100355066C - 无引线型半导体封装及其制作工艺 - Google Patents
无引线型半导体封装及其制作工艺 Download PDFInfo
- Publication number
- CN100355066C CN100355066C CNB2004100749717A CN200410074971A CN100355066C CN 100355066 C CN100355066 C CN 100355066C CN B2004100749717 A CNB2004100749717 A CN B2004100749717A CN 200410074971 A CN200410074971 A CN 200410074971A CN 100355066 C CN100355066 C CN 100355066C
- Authority
- CN
- China
- Prior art keywords
- electrode
- semiconductor chip
- electrode terminal
- resin
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 210
- 238000004519 manufacturing process Methods 0.000 title claims description 66
- 239000011347 resin Substances 0.000 claims abstract description 132
- 229920005989 resin Polymers 0.000 claims abstract description 132
- 229910052751 metal Inorganic materials 0.000 claims description 72
- 239000002184 metal Substances 0.000 claims description 72
- 238000005538 encapsulation Methods 0.000 claims description 70
- 238000000465 moulding Methods 0.000 claims description 29
- 238000005520 cutting process Methods 0.000 claims description 18
- 238000002360 preparation method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 9
- 238000004381 surface treatment Methods 0.000 claims description 8
- 238000009713 electroplating Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 36
- 229910052709 silver Inorganic materials 0.000 description 36
- 239000004332 silver Substances 0.000 description 36
- 238000000034 method Methods 0.000 description 23
- 229910000679 solder Inorganic materials 0.000 description 16
- 230000008569 process Effects 0.000 description 13
- 238000003491 array Methods 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000007769 metal material Substances 0.000 description 8
- 229910001369 Brass Inorganic materials 0.000 description 5
- 239000010951 brass Substances 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000003466 welding Methods 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 230000008719 thickening Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims (19)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP308571/2003 | 2003-09-01 | ||
JP2003308571A JP3789443B2 (ja) | 2003-09-01 | 2003-09-01 | 樹脂封止型半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1591853A CN1591853A (zh) | 2005-03-09 |
CN100355066C true CN100355066C (zh) | 2007-12-12 |
Family
ID=34074794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004100749717A Expired - Fee Related CN100355066C (zh) | 2003-09-01 | 2004-09-01 | 无引线型半导体封装及其制作工艺 |
Country Status (3)
Country | Link |
---|---|
US (2) | US7166919B2 (zh) |
JP (1) | JP3789443B2 (zh) |
CN (1) | CN100355066C (zh) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101073152B (zh) * | 2004-12-20 | 2010-04-28 | 半导体元件工业有限责任公司 | 具有下置引脚的电子封装和方法 |
US7898092B2 (en) * | 2007-11-21 | 2011-03-01 | Alpha & Omega Semiconductor, | Stacked-die package for battery power management |
US20060145312A1 (en) * | 2005-01-05 | 2006-07-06 | Kai Liu | Dual flat non-leaded semiconductor package |
US7884454B2 (en) * | 2005-01-05 | 2011-02-08 | Alpha & Omega Semiconductor, Ltd | Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package |
US8310060B1 (en) | 2006-04-28 | 2012-11-13 | Utac Thai Limited | Lead frame land grid array |
US8492906B2 (en) * | 2006-04-28 | 2013-07-23 | Utac Thai Limited | Lead frame ball grid array with traces under die |
US8487451B2 (en) | 2006-04-28 | 2013-07-16 | Utac Thai Limited | Lead frame land grid array with routing connector trace under unit |
DE102006044690B4 (de) * | 2006-09-22 | 2010-07-29 | Infineon Technologies Ag | Elektronisches Bauteil und Verfahren zum Herstellen |
JP5259978B2 (ja) * | 2006-10-04 | 2013-08-07 | ローム株式会社 | 半導体装置の製造方法 |
JP5702763B2 (ja) * | 2006-10-04 | 2015-04-15 | ローム株式会社 | 半導体装置 |
JP5197953B2 (ja) * | 2006-12-27 | 2013-05-15 | 新光電気工業株式会社 | リードフレーム及びその製造方法、及び半導体装置 |
CN101308831B (zh) * | 2007-05-17 | 2010-06-09 | 南茂科技股份有限公司 | 用于无引线封装的引线框及其封装结构 |
JP4991637B2 (ja) | 2008-06-12 | 2012-08-01 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US8227908B2 (en) | 2008-07-07 | 2012-07-24 | Infineon Technologies Ag | Electronic device having contact elements with a specified cross section and manufacturing thereof |
US8138587B2 (en) * | 2008-09-30 | 2012-03-20 | Infineon Technologies Ag | Device including two mounting surfaces |
US20100149773A1 (en) * | 2008-12-17 | 2010-06-17 | Mohd Hanafi Mohd Said | Integrated circuit packages having shared die-to-die contacts and methods to manufacture the same |
DE102009032253B4 (de) * | 2009-07-08 | 2022-11-17 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Elektronisches Bauteil |
US8164199B2 (en) * | 2009-07-31 | 2012-04-24 | Alpha and Omega Semiconductor Incorporation | Multi-die package |
US9257375B2 (en) | 2009-07-31 | 2016-02-09 | Alpha and Omega Semiconductor Inc. | Multi-die semiconductor package |
US9418919B2 (en) | 2010-07-29 | 2016-08-16 | Nxp B.V. | Leadless chip carrier having improved mountability |
CN103177974B (zh) * | 2011-12-23 | 2014-10-29 | 丽智电子(昆山)有限公司 | 铜片电极的离散式电子组件制造工艺 |
JP5959386B2 (ja) * | 2012-09-24 | 2016-08-02 | エスアイアイ・セミコンダクタ株式会社 | 樹脂封止型半導体装置およびその製造方法 |
US8809119B1 (en) | 2013-05-17 | 2014-08-19 | Stats Chippac Ltd. | Integrated circuit packaging system with plated leads and method of manufacture thereof |
US9048228B2 (en) | 2013-09-26 | 2015-06-02 | Stats Chippac Ltd. | Integrated circuit packaging system with side solderable leads and method of manufacture thereof |
JP6588215B2 (ja) * | 2015-03-24 | 2019-10-09 | 株式会社ディスコ | パッケージ基板の切削方法 |
WO2016188566A1 (en) * | 2015-05-26 | 2016-12-01 | Osram Opto Semiconductors Gmbh | Optoelectronic package device and method for producing the same |
JP6476418B2 (ja) * | 2016-02-04 | 2019-03-06 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法および電子部品実装構造体の製造方法 |
US10892211B2 (en) | 2017-08-09 | 2021-01-12 | Semtech Corporation | Side-solderable leadless package |
TWI641306B (zh) * | 2017-11-07 | 2018-11-11 | 華新科技股份有限公司 | Electronic component packaging device and packaging method thereof |
US20220084912A1 (en) * | 2019-02-15 | 2022-03-17 | Ase Japan Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
CN111987002A (zh) * | 2020-09-04 | 2020-11-24 | 长电科技(滁州)有限公司 | 一种封装体成型方法 |
CN115116978A (zh) | 2021-03-22 | 2022-09-27 | 株式会社东芝 | 半导体装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11150143A (ja) * | 1997-11-17 | 1999-06-02 | Fujitsu Ltd | 半導体装置及びその製造方法及びリードフレーム及びその製造方法 |
US6143981A (en) * | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6191494B1 (en) * | 1998-06-30 | 2001-02-20 | Fujitsu Limited | Semiconductor device and method of producing the same |
US6400004B1 (en) * | 2000-08-17 | 2002-06-04 | Advanced Semiconductor Engineering, Inc. | Leadless semiconductor package |
US6437429B1 (en) * | 2001-05-11 | 2002-08-20 | Walsin Advanced Electronics Ltd | Semiconductor package with metal pads |
US20030006055A1 (en) * | 2001-07-05 | 2003-01-09 | Walsin Advanced Electronics Ltd | Semiconductor package for fixed surface mounting |
US20030062606A1 (en) * | 2000-03-30 | 2003-04-03 | Chun Dosung | Leadless semiconductor product packaging apparatus having a window lid and method for packaging |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56100420A (en) | 1980-01-17 | 1981-08-12 | Toshiba Corp | Plasma etching method for oxidized silicon film |
JP2563683B2 (ja) | 1990-03-08 | 1996-12-11 | 松下電子工業株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
JPH07226396A (ja) | 1994-02-10 | 1995-08-22 | Sony Corp | パターン形成方法 |
US5656550A (en) * | 1994-08-24 | 1997-08-12 | Fujitsu Limited | Method of producing a semicondutor device having a lead portion with outer connecting terminal |
JP3400877B2 (ja) * | 1994-12-14 | 2003-04-28 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US5977613A (en) * | 1996-03-07 | 1999-11-02 | Matsushita Electronics Corporation | Electronic component, method for making the same, and lead frame and mold assembly for use therein |
US6201292B1 (en) * | 1997-04-02 | 2001-03-13 | Dai Nippon Insatsu Kabushiki Kaisha | Resin-sealed semiconductor device, circuit member used therefor |
US6211462B1 (en) * | 1998-11-05 | 2001-04-03 | Texas Instruments Incorporated | Low inductance power package for integrated circuits |
JP2000294719A (ja) * | 1999-04-09 | 2000-10-20 | Hitachi Ltd | リードフレームおよびそれを用いた半導体装置ならびにその製造方法 |
JP2000294715A (ja) * | 1999-04-09 | 2000-10-20 | Hitachi Ltd | 半導体装置及び半導体装置の製造方法 |
JP2001077268A (ja) * | 1999-06-28 | 2001-03-23 | Matsushita Electronics Industry Corp | 樹脂封止型半導体装置およびその製造方法 |
JP3062192B1 (ja) * | 1999-09-01 | 2000-07-10 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置の製造方法 |
JP2001257304A (ja) * | 2000-03-10 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 半導体装置およびその実装方法 |
US6399415B1 (en) * | 2000-03-20 | 2002-06-04 | National Semiconductor Corporation | Electrical isolation in panels of leadless IC packages |
KR100559664B1 (ko) * | 2000-03-25 | 2006-03-10 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
JP2001326295A (ja) * | 2000-05-15 | 2001-11-22 | Rohm Co Ltd | 半導体装置および半導体装置製造用フレーム |
JP4477202B2 (ja) * | 2000-07-12 | 2010-06-09 | ローム株式会社 | 半導体装置およびその製造方法 |
JP4731021B2 (ja) * | 2001-01-25 | 2011-07-20 | ローム株式会社 | 半導体装置の製造方法および半導体装置 |
JP3445255B2 (ja) | 2001-04-04 | 2003-09-08 | 有限会社善徳丸建設 | 法面均し機、および法面均し方法 |
TW543172B (en) * | 2001-04-13 | 2003-07-21 | Yamaha Corp | Semiconductor device and package, and method of manufacture therefor |
JP4068336B2 (ja) * | 2001-11-30 | 2008-03-26 | 株式会社東芝 | 半導体装置 |
US6841854B2 (en) * | 2002-04-01 | 2005-01-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device |
US6608366B1 (en) * | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6872599B1 (en) * | 2002-12-10 | 2005-03-29 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
JP4159348B2 (ja) * | 2002-12-20 | 2008-10-01 | 三洋電機株式会社 | 回路装置の製造方法 |
JP2004279996A (ja) | 2003-03-19 | 2004-10-07 | Hitachi Ltd | リフレクタ、及びそれを用いた投射型表示装置 |
JP3915794B2 (ja) * | 2003-04-02 | 2007-05-16 | ヤマハ株式会社 | 半導体パッケージ、その製造方法、および、これに使用するリードフレーム |
-
2003
- 2003-09-01 JP JP2003308571A patent/JP3789443B2/ja not_active Expired - Fee Related
-
2004
- 2004-08-13 US US10/917,496 patent/US7166919B2/en active Active
- 2004-09-01 CN CNB2004100749717A patent/CN100355066C/zh not_active Expired - Fee Related
-
2007
- 2007-01-05 US US11/620,481 patent/US7655506B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11150143A (ja) * | 1997-11-17 | 1999-06-02 | Fujitsu Ltd | 半導体装置及びその製造方法及びリードフレーム及びその製造方法 |
US6143981A (en) * | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
US6191494B1 (en) * | 1998-06-30 | 2001-02-20 | Fujitsu Limited | Semiconductor device and method of producing the same |
US20030062606A1 (en) * | 2000-03-30 | 2003-04-03 | Chun Dosung | Leadless semiconductor product packaging apparatus having a window lid and method for packaging |
US6400004B1 (en) * | 2000-08-17 | 2002-06-04 | Advanced Semiconductor Engineering, Inc. | Leadless semiconductor package |
US6437429B1 (en) * | 2001-05-11 | 2002-08-20 | Walsin Advanced Electronics Ltd | Semiconductor package with metal pads |
US20030006055A1 (en) * | 2001-07-05 | 2003-01-09 | Walsin Advanced Electronics Ltd | Semiconductor package for fixed surface mounting |
Also Published As
Publication number | Publication date |
---|---|
CN1591853A (zh) | 2005-03-09 |
US20070105281A1 (en) | 2007-05-10 |
JP2005079372A (ja) | 2005-03-24 |
US20050017335A1 (en) | 2005-01-27 |
US7655506B2 (en) | 2010-02-02 |
US7166919B2 (en) | 2007-01-23 |
JP3789443B2 (ja) | 2006-06-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100355066C (zh) | 无引线型半导体封装及其制作工艺 | |
CN100479135C (zh) | 半导体器件及其制造方法 | |
US7405104B2 (en) | Lead frame and method of producing the same, and resin-encapsulated semiconductor device and method of producing the same | |
CN100527411C (zh) | 半导体器件 | |
US20050023677A1 (en) | Method for assembling a ball grid array package with multiple interposers | |
US7800206B2 (en) | Semiconductor device | |
TW200522328A (en) | Semiconductor device and manufacturing method thereof | |
JP4075204B2 (ja) | 積層型半導体装置 | |
JP2000068406A (ja) | 半導体装置の製造方法、半導体装置及び配線基板 | |
CN103887292B (zh) | 堆叠式双芯片封装结构及其制备方法 | |
KR101644913B1 (ko) | 초음파 용접을 이용한 반도체 패키지 및 제조 방법 | |
CN102403236B (zh) | 芯片外露的半导体器件及其生产方法 | |
KR100253376B1 (ko) | 칩 사이즈 반도체 패키지 및 그의 제조 방법 | |
US5606204A (en) | Resin-sealed semiconductor device | |
JP3940298B2 (ja) | 半導体装置及びその半導体装置の製造方法 | |
CN212033002U (zh) | 一种qfn封装导热焊盘及具有其的qfn封装结构 | |
JPH0917910A (ja) | 半導体装置及びその製造方法、検査方法、実装基板 | |
JP3153197B2 (ja) | 半導体装置 | |
CN102832190B (zh) | 一种倒装芯片的半导体器件及制造方法 | |
CN213816121U (zh) | 一种窄脚距msop型专用芯片封装结构 | |
CN212084990U (zh) | 一种半导体封装件及pcb板 | |
CN207896074U (zh) | 半导体装置 | |
JP2003197828A (ja) | 樹脂封止型半導体装置 | |
KR102617704B1 (ko) | 파워 모듈 및 그의 패키징 방법 | |
CN109545697A (zh) | 半导体封装方法及半导体封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
ASS | Succession or assignment of patent right |
Owner name: ACER COMPUTER (CHINA) CO., LTD. Free format text: FORMER OWNER: BEIDA FANGZHENG SCIENCE + TECHNOLOGY COMPUTER SYSTEM CO., LTD., SHANGHAI Effective date: 20101027 |
|
C41 | Transfer of patent application or patent right or utility model | ||
COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 200120 36/F, SHANGHAI INTERNATIONAL BUILDING, NO.360, PUDONG SOUTH ROAD, PUDONG NEW DISTRICT, SHANGHAI TO: 200001 3/F, NO.168, XIZANG MIDDLE ROAD, HUANGPU DISTRICT, SHANGHAI |
|
TR01 | Transfer of patent right |
Effective date of registration: 20101103 Address after: Kanagawa, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: NEC Corp. |
|
CP02 | Change in the address of a patent holder |
Address after: Tokyo, Japan Patentee after: Renesas Electronics Corporation Address before: Kanagawa, Japan Patentee before: Renesas Electronics Corporation |
|
CP02 | Change in the address of a patent holder | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071212 Termination date: 20190901 |
|
CF01 | Termination of patent right due to non-payment of annual fee |