WO2016188566A1 - Optoelectronic package device and method for producing the same - Google Patents
Optoelectronic package device and method for producing the same Download PDFInfo
- Publication number
- WO2016188566A1 WO2016188566A1 PCT/EP2015/061580 EP2015061580W WO2016188566A1 WO 2016188566 A1 WO2016188566 A1 WO 2016188566A1 EP 2015061580 W EP2015061580 W EP 2015061580W WO 2016188566 A1 WO2016188566 A1 WO 2016188566A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- outer lead
- lead portion
- optoelectronic
- package device
- notch
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
Abstract
An optoelectronic package device, which is designed for being mounted on a circuit board,comprises an optoelectronic chip, a lead frame and a package housing. The lead frame comprises at least one outer lead portion electrically connected to the optoelectronic chip and exposed on an outside of the package housing. The outer lead portion comprises a bottom surface provided for being electrically coupled to the circuit board. The outer lead portion comprises at least one notch extending along the bottom surface of the outer lead portion.
Description
Description
Optoelectronic package device and method for producing the same
The present invention relates to an optoelectronic package device according to claim 1 and to a method for producing an optoelectronic package device according to claim 11.
The surface mount technology (SMT) is a soldering technology where surface mount electronic components, also known as sur¬ face mount devices (SMDs) , are mounted or soldered on the surface of a printed circuit board.
SMDs are electronic components having no leads like through- hole components. Rather, these devices are usually package devices comprising tiny metallic legs very close to the sur¬ face of the components, which are soldered on the metal trac- ing of the printed circuit board using solder paste.
It is an object of the present invention to provide an optoe¬ lectronic package device that allows for reliable soldering. This objective is achieved by an optoelectronic package de- vice with the features of claim 1. It is a further object of the present invention to provide a method for producing an optoelectronic package device that allows for reliable sol¬ dering. This objective is achieved by a method with the fea¬ tures of claim 11. Preferred embodiments are disclosed in the dependent claims.
An optoelectronic package device, which is designed for being mounted on a circuit board, comprises an optoelectronic chip, a lead frame and a package housing. The lead frame comprises at least one outer lead portion electrically connected to the optoelectronic chip and exposed on an outside of the package housing. The outer lead portion comprises a bottom surface provided for being electrically coupled to the circuit board.
The outer lead portion comprises at least one notch extending along the bottom surface of the outer lead portion.
In this way, when mounting the optoelectronic package device using SMT, the contact surface and therefore the soldering capacity is strongly increased, especially for small package devices with small solder pads. In fact, when the solder paste is melted during the SMD reflow process, an amount of the melted solder is gripped inside the notch, thereby creat- ing an anchoring feature or locking mechanism to the solder surface. Accordingly, the gripping force to the printed cir¬ cuit board is enhanced and the solder shear strength of the package device increased. Since a certain amount of melted solder is hold inside the notch, the solder contact is en- larged, thereby preventing solder creeping from its position. In addition, even for very short leads, the presence of a notch extending along the bottom surface of the outer lead portion allows the solder to wet and form a fillet around the outer leads. Besides an increased shear strength, this pre- vents an excess solder.
In an embodiment, the optoelectronic package device comprises a plurality of outer lead portions arranged in a symmetric fashion. Since the outer lead portions comprise at least a notch, the notches are arranged in a symmetric fashion as well. In particular, the notches are arranged symmetrically with respect to a centre of the package device. In this con¬ test, the centre of the package device is intended as a cen¬ tre of symmetry of said device. Advantageously, the symmetric design of the notches in the package acts as a self-alignment feature during the soldering process. In this way, the risk of tilting or misalignment of the devices during the reflow process is strongly reduced. In an embodiment of the optoelectronic package device, the package housing comprises a mounting surface facing the cir¬ cuit board and a side surface, wherein the outer lead portion is arranged at an edge between the mounting surface and the
side surface of the package housing. This may facilitate the mounting of the package device on the circuit board.
In an embodiment of the optoelectronic package device, the outer lead portion comprises a lateral surface protruding from the side surface of the package housing. This helps in correctly positioning the package device on the circuit board . In an embodiment of the optoelectronic package device, the bottom surface of the outer lead portion is flush with the mounting surface of the package housing. This may help to avoid tilting movements during the mounting process. In an embodiment of the optoelectronic package device, the notch is a rectangular notch. In other words, the notch represents a rectangular cavity extending along a part of the bottom surface of the outer lead portion having a rectangular aperture on the lateral side of said lead portion. The par- ticular rectangular notch shape allows a wider contact surface represented by the internal walls of the cavity, i.e. a horizontal surface, parallel to the circuit board on which the package device is to be mounted, and three vertical sur¬ faces orthogonal to said horizontal surface.
In an alternative embodiment of the optoelectronic package device, the notch is a V-shaped notch. In other words, the notch represents a triangular cavity extending along a part of the bottom surface of the outer lead portion. In this case, the increased contact surface in the cavity comprises at least two surfaces intersecting along a line defining a vertex .
In particular, in one embodiment of the optoelectronic pack- age device, the V-shaped notch comprises a vertex extending parallel to the bottom surface of the outer lead portion and has a triangular aperture on the lateral side of said outer lead portion. This particular shape of the notch can increase
the anchoring feature to solder surface by the fact that the notch aperture can be formed very narrow and the notch can penetrate deeply in the outer lead portion. Alternatively, the V-shaped notch comprises a vertex forming an angle between 0° and 90° with the bottom surface of the outer lead portion. The angle may for example be about 45°. In a particular embodiment, the notch is formed along one edge of the outer lead portion and specifically along the edge created by the bottom and the lateral surface of said lead portion. In this way, there is an improvement by the solder in forming a fillet around the outer lead portion and excess solder is prevented. According to different embodiments, the notch can be a square notch, a J-notch, a Ω-notch, a Y-notch or any notch having a shape or a contour suitable for the improvement of the sol¬ dering function as mentioned above. In an embodiment of the optoelectronic package device, the optoelectronic chip is a light emitting diode (LED) or a la¬ ser diode. In particular, the chip can be a blue LED combined with converter particles of phosphor dispensed in casting or moulding material in order to generate white light.
A method for producing an optoelectronic package device com¬ prises the steps of providing an optoelectronic chip and of providing a lead frame comprising at least an outer lead portion, the outer lead portion comprising a bottom surface adapted for being electrically coupled to the circuit board. The method also comprises the steps of electrically connect¬ ing the outer lead portion to the optoelectronic chip and of forming a notch in the outer lead portion extending along the bottom surface. Advantageously, the solder contact surface is enhanced and therefore the solder capability and the shear strength of package devices with small solder pad is im¬ proved .
In an embodiment of the method, the notch is formed by stamp¬ ing or by a coining process for a stamp lead frame. Alterna¬ tively, the notch can be fabricated by an etching process for etched lead frames. In this way, the final structure of the outer lead portions comprising the notches can easily be ob¬ tained in a relative short time using well-established pro¬ cesses.
In an embodiment of the method, the method further comprises the step of encapsulating the lead frame in a package body made of an insulating material, such as epoxy resin. In this way, the compactness of the entire package device is im¬ proved . The accompanying drawings are included in order to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they will be better understood by reference to the following detailed description. The ele¬ ments of the drawings are not to scale with regard to each other.
Figs, la, lb and lc show a schematic cross section view (a), a perspective view (b) and a detail of an outer lead frame portion (c) of a package device according to one embodiment;
Figs. 2a, 2b and 2c show a schematic cross section view (a), a perspective view (b) and a detail of the outer lead frame portion (c) of a package device according to another embodi¬ ment; and
Figs. 3a, 3b and 3c show a schematic cross section view (a), a perspective view (b) and a bottom view (c) of a package de¬ vice according to a further embodiment.
Fig. la shows a schematic sectional view of an optoelectronic package device 100. In the depiction of Fig. la, the package device 100 is mounted on a circuit board 10. Fig. lb shows a schematic perspective view of the optoelectronic package de¬ vice 100.
The package device 100 comprises a package housing 102 with a cavity 106. An optoelectronic chip 104 is arranged in the cavity 106. The optoelectronic chip 104 may for example be a light emitting diode chip (LED chip) designed for emitting blue light. Phosphor particles may be dispersed in a trans¬ parent molding material in the cavity 106 in order to convert light emitted by the chip 104 into light comprising another wavelength.
The package housing 102 comprises a mounting surface 110 and side surfaces 112. The mounting surface 110 is arranged oppo¬ site to the cavity 106 and faces the circuit board 10 when the package device 100 is mounted on the circuit board 10.
The package device 100 comprises a lead frame 114 which is partially embedded in the package housing 102. The optoelec¬ tronic chip 104 is electrically connected to the lead frame 114, for example via bond wires 108.
The lead frame 114 comprises a plurality of outer lead por¬ tions 116 which are exposed at the outside of the package housing 102. The outer lead portions 116 are exposed at edges between the mounting surface 110 and the side surfaces 112 of the package housing 102. In the example shown in Figs, la and lb, the lead frame 114 of the package device 100 comprises four outer lead portions 116. The outer lead portions 116 are arranged symmetrically with respect to a centre of the pack- age device 100. Two of the outer lead portions 116 are ar¬ ranged on one edge of the package housing 102. Two other outer lead portions 116 are arranged on an opposed edge. In
other embodiments, the package device 100 may, however, com¬ prise another number of outer lead portions 116. The outer lead portions 116 may be arranged at other positions of the package housing 102.
Each outer lead portion 116 comprises a bottom surface 118. The bottom surfaces 118 are parallel to the mounting surface 110 of the package housing 102 and may be flush with the mounting surface 110 or may protrude from the mounting sur- face 110. Furthermore, each outer lead portion 116 comprises a lateral surface 120. Each lateral surface 120 is approxi¬ mately parallel to one of the side surfaces 112 of the pack¬ age housing 102 may be flush with said side surface 112 or may protrude from said side surface 112.
Each outer lead portion 116 comprises a notch 122 arranged at an edge between the bottom surface 118 and the lateral sur¬ face 120 of the respective outer lead portion 116. The notch 122 extends in part along the bottom surface 118 and in part along the lateral surface 120 of the respective outer lead portion 116.
Fig. lc shows the notch 122 of one outer lead portion 116 in detail. The notch 122 is a rectangular notch and forms rec- tangular apertures 124, 126 in the bottom surface 118 and in the lateral surface 120, respectively. The rectangular aper¬ tures 124, 126 may for example both have approximatively the same area and may for example each cover about a quarter of the entire bottom surface 118 and lateral surface 120, re- spectively.
The notches 122 may for example be formed by stamping, by coining, or by etching. The notches 122 may for example al¬ ready be formed in the outer lead portions 116 of the lead frame 114 before embedding the lead frame 114 into the pack¬ age housing 102.
The optoelectronic package device 100 is designed for being mounted on the circuit board 10 by a soldering process, for example by reflow soldering. In the soldering process, the bottom surfaces 118 of the outer lead portions 116 are elec- trically connected to contact pads of the circuit board 10 by a solder 20.
The notches 122 of the outer lead portions 116 define hollows between the bottom surface 118 of the respective outer lead portion 116 and the circuit board 10. During the soldering process, the solder 20 fills these hollows at least partially and adheres to internal surfaces 128 of the notches 122. This increased the contact surface between the solder 20 and the respective outer lead portion 116. This may reduce shear stress exerted on the package device 100. Furthermore, the increased contact surfaces between the solder 20 and the outer lead portions 116 may help to prevent a tilting or a misalignment of the package device 100. Furthermore, the notches 122 may reduce a risk that solder 20 creeps on the package housing 102 during the soldering process.
Fig. 2a shows a schematic sectional view of an optoelectronic package device 200. In the depiction of Fig. 2a, the package device 200 is mounted on a circuit board 10. Fig. 2b shows a schematic perspective view of the optoelectronic package de¬ vice 200.
The package device 200 comprises a package housing 202 with a cavity 206. An optoelectronic chip 204 is arranged in the cavity 206. The optoelectronic chip 204 may for example be a light emitting diode chip (LED chip) designed for emitting blue light. Phosphor particles may be dispersed in a trans¬ parent molding material in the cavity 206 in order to convert light emitted by the chip 204 into light comprising another wavelength.
The package housing 202 comprises a mounting surface 210 and side surfaces 212. The mounting surface 210 is arranged oppo¬ site to the cavity 206 and faces the circuit board 10 when the package device 200 is mounted on the circuit board 10.
The package device 200 comprises a lead frame 214 which is partially embedded in the package housing 202. The optoelec¬ tronic chip 204 is electrically connected to the lead frame 214, for example via bond wires 208.
The lead frame 214 comprises a plurality of outer lead por¬ tions 216 which are exposed at the outside of the package housing 202. The outer lead portions 216 are exposed at edges between the mounting surface 210 and the side surfaces 212 of the package housing 202. In the example shown in Figs. 2a and 2b, the lead frame 214 of the package device 200 comprises four outer lead portions 216. The outer lead portions 216 are arranged symmetrically with respect to a centre of the mount¬ ing surface 210 of the package device 200. Two of the outer lead portions 216 are arranged on one edge of the package housing 202. Two other outer lead portions 216 are arranged on an opposed edge. In other embodiments, the package device 200 may, however, comprise another number of outer lead portions 216. The outer lead portions 216 may be arranged at other positions of the package housing 202.
Each outer lead portion 216 comprises a bottom surface 218. The bottom surfaces 218 are parallel to the mounting surface 210 of the package housing 202 and may be flush with the mounting surface 210 or may protrude from the mounting sur¬ face 210. Furthermore, each outer lead portion 216 comprises a lateral surface 220. Each lateral surface 220 is approxi¬ mately parallel to one of the side surfaces 212 of the pack¬ age housing 202 may be flush with said side surface 212 or may protrude from said side surface 212.
Each outer lead portion 216 comprises a notch 222 arranged at an edge between the bottom surface 218 and the lateral sur¬ face 220 of the respective outer lead portion 216. The notch 222 extends in part along the bottom surface 218 and in part along the lateral surface 220 of the respective outer lead portion 216.
Fig. 2c shows the notch 222 of one outer lead portion 216 in detail. The notch 222 is a V-shaped notch and forms a rectan- gular aperture 224 in the bottom surface 218 and a triangular aperture 226 in the lateral surface 220. The notch 222 com¬ prises a vertex 30 extending parallel to the bottom surface 218 of the outer lead portion 216. The rectangular aperture 224 may for example cover about an eighth of the entire bot- torn surface 218.
The notches 222 may for example be formed by stamping, by coining, or by etching. The notches 222 may for example al¬ ready be formed in the outer lead portions 216 of the lead frame 214 before embedding the lead frame 214 into the pack¬ age housing 202.
The optoelectronic package device 200 is designed for being mounted on the circuit board 10 by a soldering process, for example by reflow soldering. In the soldering process, the bottom surfaces 218 of the outer lead portions 216 are elec¬ trically connected to contact pads of the circuit board 10 by a solder 20. The notches 222 of the outer lead portions 216 define hollows between the bottom surface 218 of the respective outer lead portion 216 and the circuit board 10. During the soldering process, the solder 20 fills these hollows at least partially and adheres to internal surfaces 228 of the notches 222. This increased the contact surface between the solder 20 and the respective outer lead portion 216. This may reduce shear stress exerted on the package device 200. Furthermore, the increased contact surfaces between the solder 20 and the
outer lead portions 216 may help to prevent a tilting or a misalignment of the package device 200. Furthermore, the notches 222 may reduce a risk that solder 20 creeps on the package housing 202 during the soldering process.
Fig. 3a shows a schematic sectional view of an optoelectronic package device 300. In the depiction of Fig. 3a, the package device 300 is mounted on a circuit board 10. Fig. 3b shows a schematic perspective view of the optoelectronic package de- vice 300.
The package device 300 comprises a package housing 302 with a cavity 306. An optoelectronic chip 304 is arranged in the cavity 306. The optoelectronic chip 304 may for example be a light emitting diode chip (LED chip) designed for emitting blue light. Phosphor particles may be dispersed in a trans¬ parent molding material in the cavity 306 in order to convert light emitted by the chip 304 into light comprising another wavelength .
The package housing 302 comprises a mounting surface 310 and side surfaces 312. The mounting surface 310 is arranged oppo¬ site to the cavity 306 and faces the circuit board 10 when the package device 300 is mounted on the circuit board 10.
The package device 300 comprises a lead frame 314 which is partially embedded in the package housing 302. The optoelec¬ tronic chip 304 is electrically connected to the lead frame 314, for example via bond wires 308.
The lead frame 314 comprises a plurality of outer lead por¬ tions 316 which are exposed at the outside of the package housing 302. The outer lead portions 316 are exposed at edges between the mounting surface 310 and the side surfaces 312 of the package housing 302. In the example shown in Figs. 3a and 3b, the lead frame 314 of the package device 300 comprises four outer lead portions 316. The outer lead portions 316 are
arranged symmetrically with respect to a centre of the mount¬ ing surface 310 of the package device 300. Two of the outer lead portions 316 are arranged on one edge of the package housing 302. Two other outer lead portions 316 are arranged on an opposed edge. In other embodiments, the package device 300 may, however, comprise another number of outer lead portions 316. The outer lead portions 316 may be arranged at other positions of the package housing 302. Each outer lead portion 316 comprises a bottom surface 318. The bottom surfaces 318 are parallel to the mounting surface 310 of the package housing 302 and may be flush with the mounting surface 310 or may protrude from the mounting surface 310. Furthermore, each outer lead portion 316 comprises a lateral surface 320. Each lateral surface 320 is approxi¬ mately parallel to one of the side surfaces 312 of the pack¬ age housing 302 may be flush with said side surface 312 or may protrude from said side surface 312. Each outer lead portion 316 comprises a notch 322 arranged at an edge between the bottom surface 318 and the lateral sur¬ face 320 of the respective outer lead portion 316. The notch 322 extends in part along the bottom surface 318 and in part along the lateral surface 320 of the respective outer lead portion 316.
Fig. 3c shows the notch 322 of one outer lead portion 316 in detail. The notch 322 is a V-shaped notch and forms a trian¬ gular aperture 324 in the bottom surface 318 and a triangular aperture 326 in the lateral surface 320. The notch 322 com¬ prises a vertex 40 forming an angle 50 with the bottom sur¬ face 318 of the outer lead portion 316. The angle 50 may for example comprise 45°. The triangular apertures 324, 326 may both have approximatively the same area and may for example each cover about a fifth of the entire bottom surface 318 and the lateral surface 320, respectively..
The notches 322 may for example be formed by stamping, by coining, or by etching. The notches 322 may for example al¬ ready be formed in the outer lead portions 316 of the lead frame 314 before embedding the lead frame 314 into the pack- age housing 302.
The optoelectronic package device 300 is designed for being mounted on the circuit board 10 by a soldering process, for example by reflow soldering. In the soldering process, the bottom surfaces 318 of the outer lead portions 316 are elec¬ trically connected to contact pads of the circuit board 10 by a solder 20.
The notches 322 of the outer lead portions 316 define hollows between the bottom surface 318 of the respective outer lead portion 316 and the circuit board 10. During the soldering process, the solder 20 fills these hollows at least partially and adheres to internal surfaces 328 of the notches 322. This increased the contact surface between the solder 20 and the respective outer lead portion 316. This may reduce shear stress exerted on the package device 300. Furthermore, the increased contact surfaces between the solder 20 and the outer lead portions 316 may help to prevent a tilting or a misalignment of the package device 300. Furthermore, the notches 322 may reduce a risk that solder 20 creeps on the package housing 302 during the soldering process.
While the invention has been described in detail with refer¬ ence to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes in mod¬ ification can be made therein without departing from the spirit and scope thereof. Accordingly it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the ap- pended claims and their equivalents.
Reference numbers
10 circuit board
20 solder
30 vertex
40 vertex
50 angle
100 package device
102 package housing
104 optoelectronic chip
106 cavity
108 bond wires
110 mounting surface of package housing
112 side surfaces of package housing
114 lead frame
116 outer lead portion
118 bottom surface of the outer lead portion
120 lateral surface of the outer lead portion 122 rectangular notch
124 rectangular aperture (bottom)
126 rectangular aperture (lateral)
128 internal surfaces 200 package device
202 package housing
204 optoelectronic chip
206 cavity
208 bond wires
210 mounting surface of package housing
212 side surfaces of package housing
214 lead frame
216 outer lead portion
218 bottom surface of the outer lead portion 220 lateral surface of the outer lead portion
222 V-shaped notch
224 rectangular aperture (bottom)
226 triangular aperture (lateral)
internal surfaces package device
package housing
optoelectronic chip
cavity
bond wires
mounting surface of package housing side surfaces of package housing
lead frame
outer lead portion
bottom surface of the outer lead portion lateral surface of the outer lead portion V-shaped notch
triangular aperture (bottom)
triangular aperture (lateral)
internal surfaces
Claims
1. An optoelectronic package device (100; 200; 300)
designed for being mounted on a circuit board (10), the optoelectronic package device (100; 200; 300) com¬ prising an optoelectronic chip (104; 204; 304),
a lead frame (114; 214; 314) and a package housing (102; 202; 302),
the lead frame (114; 214; 314) comprising at least one outer lead portion (116; 216; 316) electrically connected to the optoelectronic chip (104; 204; 304) and exposed on an outside of the package housing (102; 202; 302), wherein the outer lead portion (116; 216; 316) comprises a bottom surface (118; 218; 318) provided for being elec¬ trically coupled to the circuit board (10),
wherein the outer lead portion (116; 216; 316) comprises at least one notch (122; 222; 322) extending along the bottom surface (118; 218; 318) of the outer lead portion (116; 216; 316) .
2. The optoelectronic package device (100; 200; 300) accord¬ ing to claim 1,
comprising a plurality of outer lead portions (116; 216; 316) arranged in a symmetric fashion.
3. The optoelectronic package device (100; 200; 300) accord¬ ing to any one of the previous claims,
wherein the package housing (102; 202; 302) comprises a mounting surface (110; 210; 310) facing the circuit board (10) and a side surface (112; 212; 312) and wherein the outer lead portion (116, 216, 316) is arranged at an edge between the mounting surface (110; 210; 310) and the side surface (112; 212; 312) of the package housing (102; 202; 302) .
4. The optoelectronic package device (100; 200; 300) accord¬ ing to claim 3,
wherein the bottom surface (118; 218; 318) of the outer
lead portion (116; 216; 316) is flush with the mounting surface (110; 210; 310) of the package housing (102; 202; 302) .
The optoelectronic package device (100; 200; 300) accord¬ ing to any one of claims 3 or 4,
wherein the outer lead portion (116; 216; 316) comprises a lateral surface (120; 220; 320) protruding from the side surface (112; 212; 312) of the package housing (102; 202; 302) .
The optoelectronic package device (100) according to any one of the previous claims,
wherein the notch is a rectangular notch (122) .
The optoelectronic package device (200; 300) according to any one of claims 1 to 5,
wherein the notch is a V-shaped notch (222; 322) .
The optoelectronic package device (200) according to claim 7,
wherein the V-shaped notch (222) comprises a vertex (30) extending parallel to the bottom surface (218) of the outer lead portion (216) .
The optoelectronic package device (300) according to claim 7,
wherein the V-shaped notch (322) comprises a vertex (40) forming an angle (50) between 0° and 90° with the bottom surface (318) of the outer lead portion (316) .
10. The optoelectronic package device (100; 200; 300) accord ing to any one of the previous claims,
wherein the optoelectronic chip (104; 204; 304) is a light emitting diode or a laser diode.
11. A method for producing an optoelectronic package device (100; 200; 300),
the method comprising:
- providing an optoelectronic chip (104; 204; 304);
- providing a lead frame (114; 214; 314) comprising at least an outer lead portion (116; 216; 316), the outer lead portion (116; 216; 316) comprising a bottom surface
(118; 218; 318) adapted for being electrically coupled to the circuit board (10);
- electrically connecting the outer lead portion (116; 216; 316) to the optoelectronic chip (104; 204; 304); and - forming a notch (122; 222; 322) in the outer lead portion (116; 216; 316) extending along the bottom surface (118; 218; 318) .
The method according to claim 11,
wherein the notch (122; 222; 322) is formed by stamping or by coining, or by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP2015/061580 WO2016188566A1 (en) | 2015-05-26 | 2015-05-26 | Optoelectronic package device and method for producing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/EP2015/061580 WO2016188566A1 (en) | 2015-05-26 | 2015-05-26 | Optoelectronic package device and method for producing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2016188566A1 true WO2016188566A1 (en) | 2016-12-01 |
Family
ID=53276106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2015/061580 WO2016188566A1 (en) | 2015-05-26 | 2015-05-26 | Optoelectronic package device and method for producing the same |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2016188566A1 (en) |
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| JP2019047088A (en) * | 2017-09-07 | 2019-03-22 | 日亜化学工業株式会社 | Light-emitting device |
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