CN111987002A - 一种封装体成型方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 claims abstract description 47
- 238000005530 etching Methods 0.000 claims abstract description 36
- 238000007747 plating Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005520 cutting process Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 7
- 238000000576 coating method Methods 0.000 claims abstract description 7
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 19
- 238000000465 moulding Methods 0.000 claims description 5
- 239000005022 packaging material Substances 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 31
- 230000009194 climbing Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 239000008393 encapsulating agent Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- LIMFPAAAIVQRRD-BCGVJQADSA-N N-[2-[(3S,4R)-3-fluoro-4-methoxypiperidin-1-yl]pyrimidin-4-yl]-8-[(2R,3S)-2-methyl-3-(methylsulfonylmethyl)azetidin-1-yl]-5-propan-2-ylisoquinolin-3-amine Chemical compound F[C@H]1CN(CC[C@H]1OC)C1=NC=CC(=N1)NC=1N=CC2=C(C=CC(=C2C=1)C(C)C)N1[C@@H]([C@H](C1)CS(=O)(=O)C)C LIMFPAAAIVQRRD-BCGVJQADSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010137 moulding (plastic) Methods 0.000 description 1
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- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
本发明公开了一种封装体成型方法,属于半导体封装领域。本发明的方法为:对基材进行蚀刻得到若干个封装单元,每个封装单元包括基岛和引脚,封装单元之间通过连接筋连接;再对蚀刻后的基材上表面进行电镀得到第一镀层;安装芯片并进行塑封,再对基岛和引脚的下表面进行电镀得到第二镀层;之后切割连接筋,使得连接筋两侧的引脚的侧面露出,且连接筋未切断;再对未切断的连接筋进行蚀刻,使得第一镀层露出且使得露出的引脚侧面呈凹弧状;之后对露出的引脚侧面进行镀锡。本发明克服了现有技术中,无法实现密间距、高厚度基材产品的侧面镀锡的不足,本发明可以实现密间距、高厚度基材产品的侧面镀锡,可以满足密间距、厚基材的产品侧面镀锡需求。
Description
技术领域
本发明属于半导体封装技术领域,更具体地说,涉及一种封装体成型方法。
背景技术
现有技术中,四侧无引脚扁平封装和双侧无引脚扁平封装为无引脚封装,其中央位置有一个散热焊盘,在散热焊盘的封装外围导电焊盘。通常散热焊盘与导电焊盘一起贴装在电路板上。但在现有技术中存在了塑封体切割后金属引脚的侧面无法披覆电镀锡层,直接造成PCB板上的锡膏无法爬上塑封体侧面的金属区域,从而造成金属引脚侧面虚焊或是冷焊的问题,因此塑封体侧面金属引脚的爬锡尤为关键。
针对引脚侧面镀锡的问题,现有技术也提出了一些解决方案,例如发明创造名称为:一种无外引脚半导体封装构造及其制造方法与导线架条(申请日:2012年12月28日;申请号:201210580957.9),该方案公开的制造方法包含步骤:提供一导线架条,包含数条连接支架、数个导线架单元及一抗蚀预镀金属层;每一导线架单元具有数个接点,且抗蚀预镀金属层覆盖接点及连接支架的一内表面;提供一芯片,并将芯片固定在导线架单元的区域内;利用数个电性连接元件来电性连接芯片与接点上的抗蚀预镀金属层;利用一封装胶材来包覆芯片、电性连接元件及抗蚀预镀金属层;在接点的一外表面设置一抗蚀刻掩膜,裸露出连接支架;蚀刻抗蚀刻掩膜裸露出的连接支架,以形成一蚀刻槽裸露出抗蚀预镀金属层:移除抗蚀刻掩膜;及切割位在切割槽的抗蚀预镀金属层及封装胶材,以分离成数个封装构造。
但是,现有通过预镀抗蚀刻金属层结合全蚀刻的侧面镀锡的方式,对金属基材厚度或引脚的间距有一定要求,针对密间距产品无法满足;首先密间距和厚金属基材产品,引脚之间距离较近,金属基材达到一定厚度,在限定的蚀刻速度下,仅通过单面蚀刻,引脚间金属支架无法被完全蚀刻,限制了爬锡的高度;第二,即使通过增大蚀刻压力或蚀刻时间将金属基材侧面镀锡位置支架全部蚀刻,但会造成严重侧面蚀刻和过蚀刻,导致外引脚尺寸变小。蚀刻前使用感光膜/金属镀层保护外引脚,发生过蚀刻后,凹槽的弧度向内延伸较多,反应在产品外引脚正面可能会呈现为波浪线状,而且产品背面管脚尺寸小于保护层,而正常蚀刻凹槽相对弧度小很多,且实际尺寸与设计尺寸相同。
综上所述,如何实现密间距、高厚度基材产品的侧面镀锡,是现有技术亟需解决的问题。
发明内容
1.要解决的问题
本发明克服了现有技术中,无法实现密间距、高厚度基材产品的侧面镀锡的不足,提供了一种封装体成型方法,可以实现密间距、高厚度基材产品的侧面镀锡,有效解决密间距、厚基材产品蚀刻过程中带来的过蚀刻、侧蚀严重的问题,保证了产品的正常尺寸,可以满足密间距、厚基材的产品侧面镀锡需求。
2.技术方案
为了解决上述问题,本发明所采用的技术方案如下:
本发明的一种封装体成型方法,包括以下步骤:
(1)对基材进行蚀刻得到若干个封装单元,每个封装单元包括基岛和引脚,且封装单元之间通过连接筋连接;
(2)对基岛、引脚和连接筋的上表面进行电镀得到第一镀层;
(3)将芯片安装至基岛上;
(4)对安装有芯片的封装单元进行塑封;
(5)对基岛和引脚的下表面进行电镀得到第二镀层;
(6)切割连接筋,使得连接筋两侧的引脚的侧面露出,且连接筋未切断;
(7)对未切断的连接筋进行蚀刻,使得第一镀层露出且使得露出的引脚侧面呈凹弧状;
(8)对露出的引脚侧面进行镀锡;
(9)对塑封后的封装单元进行切割得到单个引脚侧面镀锡封装件。
更进一步地,步骤(6)中利用刀片对连接筋进行切割,该刀片的厚度大于或者等于封装单元之间的距离。
更进一步地,步骤(8)之前还包括:去除引脚下表面的第二镀层。
更进一步地,步骤(4)中对安装有芯片的封装单元进行塑封的具体过程为:利用塑封料对安装有芯片的封装单元进行塑封,使得塑封料包裹芯片、引脚和基岛;其中,引脚和基岛的下表面未被塑封料包裹。
更进一步地,步骤(3)中采用倒装或者正装的方式安装芯片。
更进一步地,第一镀层的材料为金属,优选地,第一镀层的材料为银。
更进一步地,第二镀层的材料为金属,优选地,第二镀层的材料为锡。
3.有益效果
相比于现有技术,本发明的有益效果为:
本发明的一种封装体成型方法,通过采用对连接筋先切割再蚀刻的方式,可以实现对引脚的侧面镀锡,可以避免密间距且厚度大的基材在蚀刻过程中带来的过蚀刻和侧蚀严重的问题,并且可以满足更高的爬锡高度要求,进一步可以保证引脚的正常尺寸,进而保证了引脚侧面镀锡封装件正常的尺寸及外观。
附图说明
图1为本发明的引脚侧面镀锡的方法流程示意图;
图2为本发明基材时刻后的结构示意图;
图3为实施例1芯片安装后的结构示意图;
图4为实施例1封装单元塑封后的结构示意图;
图5为实施例1刀片切割连接筋后的结构示意图;
图6为实施例1对未切断的连接筋蚀刻后的结构示意图;
图7为实施例1对引脚侧面镀锡后的结构示意图。
标号说明:100、封装单元;101、第一镀层;102、第二镀层;110、基岛;120、引脚;130、连接筋;140、芯片;150、塑封料。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例;而且,各个实施例之间不是相对独立的,根据需要可以相互组合,从而达到更优的效果。因此,以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围,而是仅仅表示本发明的选定实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
为进一步了解本发明的内容,结合附图和实施例对本发明作详细描述。
实施例1
结合图1~图7所示,本发明的一种封装体成型方法,包括以下步骤:
(1)蚀刻基材
结合图2所示,对基材进行蚀刻得到若干个封装单元100,具体地,对金属基材的正反面进行蚀刻,蚀刻后得到若干个封装单元100。每个封装单元100包括基岛110和引脚120;引脚120的数量为多个,且每个封装单元100之间通过连接筋130连接,如图2所示。需要说明的是,单个封装产品是由单个封装单元100制作而成。
(2)形成第一镀层101
结合图3所示,对基岛110、引脚120和连接筋130的上表面进行电镀形成第一镀层101;即对所有的封装单元100和连接筋130的上表面进行电镀。值得说明的是,第一镀层101可以降低半导体芯片的接触电阻,保证半导体芯片接触良好。第一镀层101的材料为金属,本实施例中第一镀层101的材料为银。
(3)安装芯片140并塑封
结合图3所示,将芯片140安装至基岛110上,即每个封装单元100的基岛110对应安装有芯片140;值得说明的是,本发明可以通过正装或者倒装的方式安装芯片140;结合图3所示,本实施例采用正装的方式安装芯片140,如图所示,先将芯片140粘至基岛110的上方,而后利用金属丝进行打线完成芯片140的安装。
(4)对安装有芯片140的封装单元100进行塑封
结合图4所示,对安装有芯片140的封装单元100进行塑封;具体地,利用塑封料150对安装有芯片140的封装单元100进行塑封,使得塑封料150包裹芯片140、引脚120和基岛110,其中,引脚120和基岛110的下表面未被塑封料150包裹。如图4所示,塑封料150包裹了所有的安装有芯片140的封装单元100。
(5)形成第二镀层102
对基岛110和引脚120的下表面进行电镀得到第二镀层102;即对所有的封装单元100的下表面进行电镀;值得说明的是,第二镀层102的材料为金属,本实施例中第二镀层102的材料为锡。
(6)切割连接筋130
结合图5所示,切割连接筋130,使得连接筋130两侧的引脚120的侧面露出;值得说明的是,连接筋130没有被切断,本发明采用刀片对连接筋130进行切割,在切割过程中,通过控制刀片的切割高度,以保证连接筋130未切断。值得说明的是,该刀片的厚度大于或者等于封装单元100之间的距离。
(7)断开连接筋130
结合图6所示,对未切断的连接筋130进行蚀刻,使得连接筋130完全断开,即使得第一镀层101露出。值得说明的是,由于蚀刻的侧面蚀刻特性使得露出的引脚120侧面呈凹弧状。值得说明的是,通过对连接筋130先切割再蚀刻,从而可以将连接筋130完全断开,可以满足侧面爬锡的要求,并且避免了严重侧面蚀刻和过蚀刻的问题。
(8)侧面镀锡
结合图7所示,对漏出的引脚120侧面进行镀锡,使得引脚120的凹弧状侧面形成锡层,即实现了引脚120的侧面镀锡。
(9)切割形成单个引脚侧面镀锡封装件
对塑封后的封装单元100进行切割得到单个引脚侧面镀锡封装件,本实施例中利用刀片对塑封后的封装单元100进行切割,值得说明的是,本步骤中采用的刀片的厚度不大于封装单元100之间的距离,从而可以保证引脚120侧面的镀锡层不会被切除。
本发明的一种封装体成型方法,通过采用对连接筋130先切割再蚀刻的方式,可以实现对引脚120的侧面镀锡,可以避免密间距且厚度大的基材在蚀刻过程中带来的过蚀刻和侧蚀严重的问题,并且可以满足更高的爬锡高度要求,进一步可以保证引脚120的尺寸正常,进而保证了引脚侧面镀锡封装件正常的尺寸及外观。
实施例2
本实施例的内容与实施例1基本相同,不同之处在于,本实施例的一种封装体成型方法,在步骤(7)和步骤(8)之间还包括:对引脚120下表面进行退镀,即去除引脚120下表面的第二镀层102,从而可以避免引脚120下表面的第二镀层102过厚或者可能引起的引脚120下表面的第二镀层102厚度不均匀的问题。
在上文中结合具体的示例性实施例详细描述了本发明。但是,应当理解,可在不脱离由所附权利要求限定的本发明的范围的情况下进行各种修改和变型。详细的描述和附图应仅被认为是说明性的,而不是限制性的,如果存在任何这样的修改和变型,那么它们都将落入在此描述的本发明的范围内。此外,背景技术旨在为了说明本技术的研发现状和意义,并不旨在限制本发明或本申请和本发明的应用领域。
Claims (8)
1.一种封装体成型方法,其特征在于,包括以下步骤:
(1)对基材进行蚀刻得到若干个封装单元,每个封装单元包括基岛和引脚,且封装单元之间通过连接筋连接;
(2)对基岛、引脚和连接筋的上表面进行电镀得到第一镀层;
(3)将芯片安装至基岛上;
(4)对安装有芯片的封装单元进行塑封;
(5)对基岛和引脚的下表面进行电镀得到第二镀层;
(6)切割连接筋,使得连接筋两侧的引脚的侧面露出,且连接筋未切断;
(7)对未切断的连接筋进行蚀刻,使得第一镀层露出且使得露出的引脚侧面呈凹弧状;
(8)对露出的引脚侧面进行镀锡;
(9)对塑封后的封装单元进行切割得到单个引脚侧面镀锡封装件。
2.根据权利要求1所述的一种封装体成型方法,其特征在于,步骤(6)中利用刀片对连接筋进行切割,该刀片的厚度大于或者等于封装单元之间的距离。
3.根据权利要求1所述的一种封装体成型方法,其特征在于,步骤(8)之前还包括:去除引脚下表面的第二镀层。
4.根据权利要求1所述的一种封装体成型方法,其特征在于,步骤(3)中对安装有芯片的封装单元进行塑封的具体过程为:利用塑封料对安装有芯片的封装单元进行塑封,使得塑封料包裹芯片、引脚和基岛;其中,引脚和基岛的下表面未被塑封料包裹。
5.根据权利要求1所述的一种封装体成型方法,其特征在于,步骤(3)中采用倒装或者正装的方式安装芯片。
6.根据权利要求1~5任一项所述的一种封装体成型方法,其特征在于,所述第一镀层和第二镀层的材料为金属。
7.根据权利要求6任一项所述的一种封装体成型方法,其特征在于,所述第一镀层的材料为银。
8.根据权利要求6所述的一种封装体成型方法,其特征在于,所述第二镀层的材料为锡。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI745213B (zh) * | 2021-01-06 | 2021-11-01 | 南茂科技股份有限公司 | 半導體封裝結構及其製造方法 |
CN115719713A (zh) * | 2023-01-09 | 2023-02-28 | 江苏长晶浦联功率半导体有限公司 | 一种扁平无引脚元件及其封装方法 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005079372A (ja) * | 2003-09-01 | 2005-03-24 | Nec Electronics Corp | 樹脂封止型半導体装置とその製造方法 |
US20050287709A1 (en) * | 2004-06-23 | 2005-12-29 | Advanced Semiconductor Engineering Inc. | Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe |
JP2006179760A (ja) * | 2004-12-24 | 2006-07-06 | Yamaha Corp | 半導体パッケージ、および、これに使用するリードフレーム |
US20100149773A1 (en) * | 2008-12-17 | 2010-06-17 | Mohd Hanafi Mohd Said | Integrated circuit packages having shared die-to-die contacts and methods to manufacture the same |
US20100187663A1 (en) * | 2009-01-29 | 2010-07-29 | Phillip Celaya | Method for manufacturing a semiconductor component and structure therefor |
CN103021892A (zh) * | 2012-12-28 | 2013-04-03 | 日月光半导体(昆山)有限公司 | 无外引脚半导体封装构造及其制造方法与导线架条 |
JP2013225595A (ja) * | 2012-04-20 | 2013-10-31 | Shinko Electric Ind Co Ltd | リードフレーム及び半導体パッケージ並びにそれらの製造方法 |
US20140035113A1 (en) * | 2012-08-01 | 2014-02-06 | Analog Devices, Inc. | Packaging and methods for packaging |
CN106158742A (zh) * | 2016-08-30 | 2016-11-23 | 长电科技(滁州)有限公司 | 一种平面凸点式无金属切割封装工艺及其封装结构 |
JP2019047061A (ja) * | 2017-09-06 | 2019-03-22 | 大日本印刷株式会社 | 半導体装置およびその製造方法 |
-
2020
- 2020-09-04 CN CN202010921534.3A patent/CN111987002A/zh active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005079372A (ja) * | 2003-09-01 | 2005-03-24 | Nec Electronics Corp | 樹脂封止型半導体装置とその製造方法 |
US20050287709A1 (en) * | 2004-06-23 | 2005-12-29 | Advanced Semiconductor Engineering Inc. | Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe |
JP2006179760A (ja) * | 2004-12-24 | 2006-07-06 | Yamaha Corp | 半導体パッケージ、および、これに使用するリードフレーム |
US20100149773A1 (en) * | 2008-12-17 | 2010-06-17 | Mohd Hanafi Mohd Said | Integrated circuit packages having shared die-to-die contacts and methods to manufacture the same |
US20100187663A1 (en) * | 2009-01-29 | 2010-07-29 | Phillip Celaya | Method for manufacturing a semiconductor component and structure therefor |
JP2013225595A (ja) * | 2012-04-20 | 2013-10-31 | Shinko Electric Ind Co Ltd | リードフレーム及び半導体パッケージ並びにそれらの製造方法 |
US20140035113A1 (en) * | 2012-08-01 | 2014-02-06 | Analog Devices, Inc. | Packaging and methods for packaging |
CN103021892A (zh) * | 2012-12-28 | 2013-04-03 | 日月光半导体(昆山)有限公司 | 无外引脚半导体封装构造及其制造方法与导线架条 |
CN106158742A (zh) * | 2016-08-30 | 2016-11-23 | 长电科技(滁州)有限公司 | 一种平面凸点式无金属切割封装工艺及其封装结构 |
JP2019047061A (ja) * | 2017-09-06 | 2019-03-22 | 大日本印刷株式会社 | 半導体装置およびその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI745213B (zh) * | 2021-01-06 | 2021-11-01 | 南茂科技股份有限公司 | 半導體封裝結構及其製造方法 |
CN115719713A (zh) * | 2023-01-09 | 2023-02-28 | 江苏长晶浦联功率半导体有限公司 | 一种扁平无引脚元件及其封装方法 |
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