BR112018005532B1 - Suporte de esfera de pacote em nível de wafer (wlp) com o uso de estrutura de cavidade - Google Patents

Suporte de esfera de pacote em nível de wafer (wlp) com o uso de estrutura de cavidade Download PDF

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Publication number
BR112018005532B1
BR112018005532B1 BR112018005532-8A BR112018005532A BR112018005532B1 BR 112018005532 B1 BR112018005532 B1 BR 112018005532B1 BR 112018005532 A BR112018005532 A BR 112018005532A BR 112018005532 B1 BR112018005532 B1 BR 112018005532B1
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BR
Brazil
Prior art keywords
dielectric layer
cavities
blocks
conductors
conductor
Prior art date
Application number
BR112018005532-8A
Other languages
English (en)
Portuguese (pt)
Other versions
BR112018005532A2 (enExample
Inventor
Mario Francisco Velez
David Francis Berdy
Changhan Hobie Yun
Jonghae Kim
Chengjie Zuo
Daeik Daniel Kim
Je-Hsiung Jeffrey Lan
Niranjan Sunil Mudakatte
Robert Paul Mikulka
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Publication of BR112018005532A2 publication Critical patent/BR112018005532A2/pt
Publication of BR112018005532B1 publication Critical patent/BR112018005532B1/pt

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/0905—Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
BR112018005532-8A 2015-09-20 2016-09-20 Suporte de esfera de pacote em nível de wafer (wlp) com o uso de estrutura de cavidade BR112018005532B1 (pt)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/859,323 2015-09-20
US14/859,323 US10074625B2 (en) 2015-09-20 2015-09-20 Wafer level package (WLP) ball support using cavity structure
PCT/US2016/052631 WO2017049324A1 (en) 2015-09-20 2016-09-20 Wafer level package (wlp) ball support using cavity structure

Publications (2)

Publication Number Publication Date
BR112018005532A2 BR112018005532A2 (enExample) 2018-10-02
BR112018005532B1 true BR112018005532B1 (pt) 2023-03-07

Family

ID=57018210

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112018005532-8A BR112018005532B1 (pt) 2015-09-20 2016-09-20 Suporte de esfera de pacote em nível de wafer (wlp) com o uso de estrutura de cavidade

Country Status (8)

Country Link
US (1) US10074625B2 (enExample)
EP (1) EP3350831A1 (enExample)
JP (1) JP6549790B2 (enExample)
KR (1) KR102006115B1 (enExample)
CN (1) CN108028243B (enExample)
BR (1) BR112018005532B1 (enExample)
CA (1) CA2995621A1 (enExample)
WO (1) WO2017049324A1 (enExample)

Family Cites Families (27)

* Cited by examiner, † Cited by third party
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JP3070514B2 (ja) * 1997-04-28 2000-07-31 日本電気株式会社 突起電極を有する半導体装置、半導体装置の実装方法およびその実装構造
GB2389460A (en) 1998-12-22 2003-12-10 Nec Corp Mounting semiconductor packages on substrates
JP3019851B1 (ja) * 1998-12-22 2000-03-13 日本電気株式会社 半導体装置実装構造
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
JP2002050716A (ja) * 2000-08-02 2002-02-15 Dainippon Printing Co Ltd 半導体装置及びその作製方法
JP3842548B2 (ja) * 2000-12-12 2006-11-08 富士通株式会社 半導体装置の製造方法及び半導体装置
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP2003198068A (ja) 2001-12-27 2003-07-11 Nec Corp プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
JP2004103928A (ja) * 2002-09-11 2004-04-02 Fujitsu Ltd 基板及びハンダボールの形成方法及びその実装構造
US7043830B2 (en) 2003-02-20 2006-05-16 Micron Technology, Inc. Method of forming conductive bumps
US8193092B2 (en) * 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
US20100319974A1 (en) * 2008-02-19 2010-12-23 Naomi Ishizuka Printed wiring board, electronic device, and method for manufacturing electronic device
JP2012221998A (ja) * 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
JP5682496B2 (ja) * 2011-07-28 2015-03-11 富士通セミコンダクター株式会社 半導体装置、マルチチップ半導体装置、デバイス、及び半導体装置の製造方法
KR101840447B1 (ko) * 2011-08-09 2018-03-20 에스케이하이닉스 주식회사 반도체 패키지 및 이를 갖는 적층 반도체 패키지
JP2013074054A (ja) * 2011-09-27 2013-04-22 Renesas Electronics Corp 電子装置、配線基板、及び、電子装置の製造方法
JP2013080805A (ja) * 2011-10-03 2013-05-02 Sumitomo Bakelite Co Ltd 補強部材の製造方法
US9129973B2 (en) * 2011-12-07 2015-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit probing structures and methods for probing the same
EP2605273A3 (en) * 2011-12-16 2017-08-09 Imec Method for forming isolation trenches in micro-bump interconnect structures and devices obtained thereof
US8963336B2 (en) * 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US8963335B2 (en) 2012-09-13 2015-02-24 Invensas Corporation Tunable composite interposer
US9343419B2 (en) * 2012-12-14 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for semiconductor package
EP2747132B1 (en) * 2012-12-18 2018-11-21 IMEC vzw A method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US9484318B2 (en) * 2014-02-17 2016-11-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US20150237732A1 (en) 2014-02-18 2015-08-20 Qualcomm Incorporated Low-profile package with passive device

Also Published As

Publication number Publication date
US10074625B2 (en) 2018-09-11
JP6549790B2 (ja) 2019-07-24
EP3350831A1 (en) 2018-07-25
JP2018527754A (ja) 2018-09-20
BR112018005532A2 (enExample) 2018-10-02
CN108028243A (zh) 2018-05-11
US20170084565A1 (en) 2017-03-23
KR102006115B1 (ko) 2019-07-31
CN108028243B (zh) 2021-05-14
WO2017049324A1 (en) 2017-03-23
CA2995621A1 (en) 2017-03-23
KR20180056686A (ko) 2018-05-29

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Legal Events

Date Code Title Description
B06U Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09A Decision: intention to grant [chapter 9.1 patent gazette]
B16A Patent or certificate of addition of invention granted [chapter 16.1 patent gazette]

Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 20/09/2016, OBSERVADAS AS CONDICOES LEGAIS