CN114759003A - 封装结构及其制作方法 - Google Patents

封装结构及其制作方法 Download PDF

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Publication number
CN114759003A
CN114759003A CN202111079211.5A CN202111079211A CN114759003A CN 114759003 A CN114759003 A CN 114759003A CN 202111079211 A CN202111079211 A CN 202111079211A CN 114759003 A CN114759003 A CN 114759003A
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China
Prior art keywords
bump
region
sub
disposed
circuit substrate
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CN202111079211.5A
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English (en)
Inventor
林昱圣
黄汉祥
陈建声
叶书伸
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN114759003A publication Critical patent/CN114759003A/zh
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Abstract

一种封装结构包括电路衬底、半导体封装、第一凸块结构及第二凸块结构。所述半导体封装设置在所述电路衬底上，其中所述半导体封装包括中心区及环绕所述中心区的侧边区。所述第一凸块结构设置在所述半导体封装的所述中心区上，且将所述半导体封装电连接到所述电路衬底。所述第二凸块结构设置在所述半导体封装的所述侧边区上，且将所述半导体封装电连接到所述电路衬底，其中所述第一凸块结构与所述第二凸块结构具有不同的高度及不同的形状。

Description

封装结构及其制作方法
技术领域
本公开实施例是有关一种封装结构及制作所述封装结构的方法。
背景技术
在各种电子应用(例如，手机及其他移动电子设备)中使用的半导体器件及集成电路通常制造在单个半导体晶片上。晶片的管芯可与其他半导体器件或管芯一起以晶片层级进行处理及封装，且已经开发出用于晶片层级封装的各种技术。
发明内容
本公开实施例提供一种封装结构包括电路衬底、半导体封装、第一凸块结构以及第二凸块结构。所述半导体封装设置在所述电路衬底上，其中所述半导体封装包括中心区及环绕所述中心区的侧边区。所述第一凸块结构设置在所述半导体封装的所述中心区上，且将所述半导体封装电连接到所述电路衬底。所述第二凸块结构设置在所述半导体封装的所述侧边区上，且将所述半导体封装电连接到所述电路衬底，其中所述第一凸块结构与所述第二凸块结构具有不同的高度及不同的形状。
本公开实施例提供一种封装结构包括电路衬底、中介层结构、多个凸块结构、多个半导体管芯以及绝缘包封体。所述中介层结构设置在所述电路衬底上且电连接到所述电路衬底。所述多个凸块结构设置在所述电路衬底与所述中介层结构之间，且将所述中介层结构电连接到所述电路衬底，其中设置在所述中介层结构的第一区上的所述多个凸块结构彼此间隔开第一间距，且设置在所述中介层结构的第二区上的所述多个凸块结构彼此间隔开第二间距，其中所述第二间距不同于所述第一间距，且其中设置在所述第一区及所述第二区上的所述多个凸块结构具有不同的大小。所述半导体管芯设置在所述中介层结构的背侧表面上且电连接到所述中介层结构。所述绝缘包封体设置在所述中介层结构的所述背侧表面上，且环绕所述多个半导体管芯。
本公开实施例提供一种封装结构包括电路衬底、内连线结构、第一凸块结构、第二凸块结构以及底部填充结构。所述内连线结构设置在所述电路衬底上且电连接到所述电路衬底。所述第一凸块结构设置在所述电路衬底与所述内连线结构之间。所述第二凸块结构设置在所述电路衬底与所述内连线结构之间，其中所述第二凸块结构具有比所述第一凸块结构大的高度，且所述第一凸块结构在所述内连线结构上的布置比所述第二凸块结构在所述内连线结构上的布置更稠密。所述底部填充结构覆盖所述第一凸块结构及所述第二凸块结构。
附图说明
参照附图阅读以下详细说明，会最好地理解本公开的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为使论述清晰起见，可任意增大或减小各种特征的临界尺寸。
图1A到图1L是根据本公开一些示例性实施例的制作半导体封装的方法中的各种阶段的示意性俯视图及剖视图。
图2是根据本公开一些其他示例性实施例的半导体封装的示意性剖视图。
图3A到图3C是根据本公开一些示例性实施例的制作封装结构的方法中的各种阶段的示意性剖视图。
图4A及图4B是根据本公开一些其他实施例的半导体封装的示意性剖视图及俯视图。
图5A及图5B是根据本公开一些其他实施例的半导体封装的示意性剖视图及俯视图。
图6A及图6B是根据本公开一些其他实施例的半导体封装的示意性剖视图及俯视图。
图7A至图7C是根据本公开一些其他示例性实施例的制作封装结构的方法中的各种阶段的示意性剖视图。
图8是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。
[符号的说明]
21：半导体管芯
21S、22S、114b：背侧表面
22：管芯/半导体管芯
100、100’：中介层结构
101A、116a：介电层
101B：导电层
101C1、101C2、106：导电焊盘
102：核心部分
102a：第一表面
102b：第二表面
104：穿孔
110：电连接件
112、350：底部填充结构
114：绝缘包封体
114a：顶表面
116：重布线结构
116b、116c、116c-1、116c-2、116c-3：金属化图案
116s：顶表面
118：凸块结构
118A：第一凸块结构
118B：第二凸块结构
118B-1：第一部分凸块
118B-2：第二部分凸块
118B-3：第三部分凸块
210、220：本体
211、221：有源表面
212、222：连接焊盘
300：衬底/电路衬底
310、320：接触焊盘
330：金属化层
340：导电球
510：环结构
AR1：中心区
Ax：粘合剂
BR1：侧边区
BR1A：第一侧边区
BR1A-1：第一子区
BR1A-2：第二子区
BR1A-3：第三子区
BR1B：第二侧边区
BR1B-4：第四子区
BR1B-5：第五子区
BR1B-6：第六子区
BR1C：第三侧边区
Cx：载体
DL：切割道
FR：框架
H1、H2、H3、HT：高度
MP1、MP2：金属柱
RDL：重布线层
PDX：无源器件
PKG1、PKG2、PKG3：封装结构
PKR：封装区
SD1：第一外围侧
SD2：第二外围侧
SLD1、SLD2：焊料
SM、SM2、SM3、SM4、SM5：半导体封装
Sp1：间距/第一间距
Sp2：间距/第二间距
Sp2A、Sp2B、Sp2C：间距
TP：胶带
Tx、Ty：厚度
W1、W2：最大宽度
W2A、W2B、W2C：宽度
WP1：高度差/最大高度差
WP2：高度差
Y1：第一平均高度
Y2：第二平均高度
Y3：最大高度
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。下文阐述组件及布置的具体实例以简化本公开。当然，这些仅是实例且不旨在进行限制。举例来说，在以下说明中，在第一特征之上或在第一特征上形成第二特征可包括其中第二特征与第一特征被形成为直接接触的实施例，且还可包括其中在第二特征与第一特征之间可形成附加特征、进而使得所述第二特征与所述第一特征可能不直接接触的实施例。另外，本公开可在各种实例中重复使用参考编号和/或字母。此种重复使用是出于简单及清晰的目的，且自身并不指示所论述的各种实施例和/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“在……下面(beneath)”、“在……下方(below)”、“下部的(lower)”、“上(on)”、“之上(over)”、“上覆在……之上(overlying)”、“在……上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示出的一个元件或特征与另一(其他)元件或特征的关系。除图中所绘示的取向以外，所述空间相对性用语还旨在囊括器件在使用或操作中的不同取向。装置可具有其他取向(旋转90度或处于其他取向)，且本文中所使用的空间相对性阐述语可同样相应地进行解释。
在目前的应用中，在将半导体封装结合到衬底上期间，由于半导体封装的高翘曲，封装结构有时遭受桥接(bridging)或冷接头(cold joint)问题。翘曲问题在例如晶片上芯片(chip-on-wafer，CoW)封装等大的封装中更为常见。在本公开的一些实施例中，由于复杂的材料构成导致一般难以控制半导体封装的翘曲，因此调整半导体封装上的凸块结构的设计以避免或减少冷接头问题以及改善封装结构的可靠性。
图1A到图1L是根据本公开一些示例性实施例的制作半导体封装的方法中的各种阶段的示意性俯视图及剖视图。参照图1A，提供中介层结构100。在一些实施例中，中介层结构100包括核心部分102以及形成在其中的多个穿孔104及导电焊盘106。在一些实施例中，核心部分102是例如体半导体衬底、绝缘体上硅(silicon on insulator，SOI)衬底或多层式半导体材料衬底等衬底。衬底(核心部分102)的半导体材料可为硅、锗、硅锗、碳化硅、镓砷、磷化镓、磷化铟、砷化铟、锑化铟、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或其组合。在一些实施例中，核心部分102是经掺杂的或未经掺杂的。
在一些实施例中，在核心部分102的第一表面102a(中介层结构100的第一表面102a)上形成导电焊盘106。在一些实施例中，在核心部分102中形成穿孔104，且将穿孔104与导电焊盘106连接。在一些实施例中，穿孔104以特定深度延伸到核心部分102中。在一些实施例中，穿孔104是衬底穿孔。在一些实施例中，当核心部分102是硅衬底时，穿孔104是硅穿孔。在一些实施例中，通过在核心部分102中形成孔或凹陷且然后利用导电材料填充凹陷来形成穿孔104。在一些实施例中，通过例如刻蚀、铣削、激光钻孔或类似工艺来形成凹陷。在一些实施例中，通过电化学镀覆工艺、化学气相沉积(chemical vapor deposition，CVD)、原子层沉积(atomic layer deposition，ALD)或物理气相沉积(physical vapordeposition，PVD)来形成导电材料，且导电材料可包括铜、钨、铝、银、金或其组合。在一些实施例中，将与穿孔104连接的导电焊盘106形成为在中介层结构100上形成的重布线层的导电部。在一些实施例中，导电焊盘106包括凸块下金属(under bump metallurgy，UBM)。在某些实施例中，中介层结构100可进一步包括有源器件或无源器件，例如形成在核心部分102中的晶体管、电容器、电阻器或二极管。
如图1A中所示，核心部分102具有多个封装区PKR及将所述多个封装区PKR中的每一者分开的切割道(dicing lane)DL。在封装区PKR内的核心部分102中形成穿孔104及导电焊盘106。在一些实施例中，在中介层结构100上或在封装区PKR内的核心部分102上设置多个半导体管芯21(第一半导体管芯)及多个半导体管芯22(第二半导体管芯)。半导体管芯21及半导体管芯22是从晶片单体化而成的各别管芯。在一些实施例中，半导体管芯21包含相同的电路系统(例如器件及金属化图案)，或者半导体管芯21是相同类型的管芯。在一些实施例中，半导体管芯22包含相同的电路系统，或者半导体管芯22是相同类型的管芯。在某些实施例中，半导体管芯21及半导体管芯22具有不同的电路系统或者是不同类型的管芯。在一些实施例中，半导体管芯21与半导体管芯22可具有相同的电路系统。
在一些实施例中，半导体管芯21可为主管芯，而半导体管芯22是分支管芯。在一些实施例中，在位于每一封装区PKR的中心位置的核心部分102上布置主管芯，同时与主管芯并排且间隔开地布置分支管芯。在一些实施例中，在主管芯旁边且围绕或环绕主管芯布置分支管芯。在一个实施例中，每一个封装区PKR围绕一个主管芯布置四个或六个分支管芯。本公开不限于此。
在某些实施例中，半导体管芯21具有较半导体管芯22的表面积大的表面积。此外，在一些实施例中，半导体管芯21与半导体管芯22可具有不同的大小，包括不同的表面积和/或不同的厚度。在一些实施例中，半导体管芯21可为包括中央处理器(central processingunit，CPU)管芯、图形处理单元(graphics processing unit，GPU)管芯、系统芯片(system-on-a-chip，SoC)管芯、微控制器或类似物在内的逻辑管芯。在一些实施例中，半导体管芯21是例如电源管理集成电路(power management integrated circuit，PMIC)管芯等电源管理管芯。在一些实施例中，半导体管芯22可为包括动态随机存取存储器(dynamic randomaccess memory，DRAM)管芯、静态随机存取存储器(static random access memory，SRAM)管芯或高带宽存储器(high bandwidth memory，HBM)管芯在内的存储器管芯。本公开不限于此，且设置在核心部分102上的半导体管芯的数目、大小及类型可基于产品要求适当地调整。
如图1A中所示，半导体管芯21包括本体210及形成在本体210的有源表面211上的连接焊盘212。在某些实施例中，连接焊盘212可进一步包括用于将半导体管芯21结合到其他结构的柱结构。在一些实施例中，半导体管芯22包括本体220及形成在本体220的有源表面221上的连接焊盘222。在其他实施例中，连接焊盘222可进一步包括用于将管芯22结合到其他结构的柱结构。
在一些实施例中，例如借助于电连接件110通过倒装芯片结合(flip-chipbonding)将半导体管芯21及半导体管芯22贴合到核心部分102的第一表面102a。通过回焊工艺(reflow process)，在连接焊盘212、222与导电焊盘106之间形成电连接件110，且电连接件110将半导体管芯21、22物理连接到中介层结构100的核心部分102。在一些实施例中，电连接件110位于半导体管芯21、22与中介层结构100之间。在某些实施例中，通过电连接件110将半导体管芯21、22电连接到穿孔104及导电焊盘106。在一些替代性实施例中，当半导体管芯22是虚设管芯时，可在不与电连接件110建立电连接的条件下通过物理连接将半导体管芯22贴合到电连接件110。换句话说，半导体管芯22的连接焊盘222可为例如虚设焊盘。
在一个实施例中，电连接件110是微凸块，例如具有铜金属柱的微凸块。在另一实施例中，电连接件110是焊料凸块、无铅焊料凸块或微凸块，例如受控塌陷芯片连接(controlled collapse chip connection，C4)凸块或包含铜柱的微凸块。在一些实施例中，半导体管芯21、22与核心部分102之间的结合是焊料结合。在一些实施例中，半导体管芯21、22与核心部分102之间的结合是例如铜对铜结合(copper-to-copper bonding)等直接金属对金属结合。
参照图1B，在一些实施例中，可形成底部填充结构112以覆盖所述多个电连接件110，且填充满半导体管芯21、22与中介层结构100之间的空间。在一些实施例中，底部填充结构112进一步覆盖半导体管芯21、22的侧壁，且位于封装区PKR内。此后，可在中介层结构100之上(或在核心部分102之上)形成绝缘包封体114(或模制化合物)以覆盖底部填充结构112并环绕半导体管芯21及22。
在一些实施例中，在封装区PKR中的核心部分102的第一表面102a上及在切割道DL之上形成绝缘包封体114。在一些实施例中，通过例如压缩模制工艺(compression moldingprocess)或转移模制(transfer molding)来形成绝缘包封体114。在一个实施例中，执行固化工艺以固化绝缘包封体114。在一些实施例中，通过绝缘包封体114来包封半导体管芯21、22及电连接件110。在一些实施例中，执行平坦化工艺(包括研磨或抛光)以局部地移除绝缘包封体114，从而暴露出半导体管芯21、22的背侧表面21S、22S。因此，半导体管芯21、22的背侧表面21S、22S与绝缘包封体114的顶表面114a齐平。顶表面114a与绝缘包封体114的背侧表面114b相对，其中背侧表面114b与核心部分102接触。在一些替代性实施例中，半导体管芯21、22的背侧表面21S、22S不从绝缘包封体114暴露出，且由绝缘包封体114很好地保护。
在一些实施例中，绝缘包封体114的材料包括聚合物(例如环氧树脂、酚醛树脂、含硅树脂或其他适合的树脂)、具有低介电系数(Dk)及低损耗角正切(Df)性质的介电材料或其他合适的材料。在替代性实施例中，绝缘包封体114可包含可接受的绝缘包封材料。在一些实施例中，绝缘包封体114可进一步包含可被添加到其中以优化绝缘包封体114的热膨胀系数(coefficient of thermal expansion，CTE)的无机填料或无机化合物(例如，二氧化硅、粘土等等)。本公开不限于此。
参照图1C，将图1B中所示结构上下颠倒或翻转，并放置在载体Cx上，以使得载体Cx直接接触半导体管芯21、22的背侧表面21S、22S及绝缘包封体114的顶表面114a。如图1C中所示，在此处理阶段处，中介层结构100尚未薄化且具有厚度Tx。换句话说，穿孔104不被显露出，且被嵌置在中介层结构100的核心部分102中。
参照图1D，对中介层结构100执行薄化工艺，以局部地移除或薄化中介层结构100的核心部分102，直到穿孔104被暴露出且核心部分102的第二表面102b被形成为止。在一些实施例中，薄化工艺可包括背面研磨工艺、抛光工艺或刻蚀工艺。在一些实施例中，在薄化工艺之后，将中介层结构100薄化至厚度Ty。在一些实施例中，厚度Ty对厚度Tx的比率的范围介于约0.1至约0.5。
参照图1E，在封装区PKR中的核心部分102的第二表面102b上及在切割道DL之上形成重布线结构116。第二表面102b与核心部分102的第一表面102a相对。在一些实施例中，重布线结构116、核心部分102、穿孔104及导电焊盘106构成中介层结构100’(或内连线结构)。在一些实施例中，重布线结构116对穿孔104进行电连接和/或对穿孔104与外部器件进行电连接。在某些实施例中，重布线结构116包括至少一个介电层116a及嵌置在介电层116a中的金属化图案116b、116c。在一些实施例中，金属化图案116b的宽度大于金属化图案116c的宽度。金属化图案116b、116c可包括焊盘、通孔和/或迹线，以对穿孔104进行内连，并进一步将穿孔104连接到一个或多个外部器件。尽管在图1E中示出一层介电层116a及一层金属化图案116b、116c，然而应注意，介电层116a及金属化图案116b、116c的层数不限于此，且此可基于要求来进行调整。
在一些实施例中，介电层116a的材料包括氧化硅、氮化硅、碳化硅、氮氧化硅或低介电常数(low-K)介电材料(例如磷硅酸盐玻璃(phosphosilicate glass，PSG)材料、氟硅酸盐玻璃材料、硼磷硅酸盐玻璃材料、SiOC、旋涂玻璃材料、旋涂聚合物或硅碳材料)。在一些实施例中，通过旋转涂布(spin-coating)或包括化学气相沉积(CVD)、等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)、高密度等离子体化学气相沉积(high density plasma-CVD，HDP-CVD)或类似工艺在内的沉积来形成介电层116a。在一些实施例中，金属化图案116b、116c包括凸块下金属(UBM)。在一些实施例中，金属化图案116b、116c的形成可包括使用光刻技术以及一个或多个刻蚀工艺来图案化介电层以及将金属材料填充到经图案化的介电层的开口中。可例如使用化学机械抛光工艺移除介电层上的任何过量导电材料。在一些实施例中，金属化图案116b、116c的材料包括铜、铝、钨、银及其组合。
如图1E中进一步所示，在金属化图案116b、116c上设置多个凸块结构118，且将所述多个凸块结构118电耦合到穿孔104。举例来说，凸块结构118包括第一凸块结构118A及第二凸块结构118B，第一凸块结构118A及第二凸块结构118B放置在重布线结构116的顶表面116s上，并在封装区PKR内通过金属化图案116b、116c电连接到穿孔104。在某些实施例中，第一凸块结构118A位于金属化图案116b上且物理贴合到金属化图案116b，而第二凸块结构118B位于金属化图案116c上且物理贴合到金属化图案116c。
在一些实施例中，第一凸块结构118A及第二凸块结构118B包括无铅焊球、焊球、球栅阵列(ball grid array，BGA)球、凸块、C4凸块或微凸块。在一些实施例中，第一凸块结构118A及第二凸块结构118B可包含例如焊料、铜、铝、金、镍、银、钯、锡或其组合等导电材料。在一些实施例中，通过透过例如蒸镀、电镀、印刷或焊料转移在重布线结构116上形成焊料膏且然后回焊成所期望凸块形状来形成凸块结构118。在一些实施例中，通过植球(ballplacement)或类似工艺将第一凸块结构118A及第二凸块结构118B放置在重布线结构116上。在其他实施例中，通过透过溅镀、印刷、无电镀覆或电镀或者CVD形成无焊料金属柱(例如铜柱)且然后透过在金属柱上镀覆形成无铅顶盖层来形成第一凸块结构118A及第二凸块结构118B。第一凸块结构118A及第二凸块结构118B可用于结合到外部器件或附加的电组件。在一些实施例中，第一凸块结构118A及第二凸块结构118B用于结合到电路衬底、半导体衬底或封装衬底。
如作为图1E中所示封装区PKR的俯视图的图1F中所示，在中介层结构100’的中心区AR1(或第一区)上设置第一凸块结构118A，而在中介层结构100’的侧边区BR1(或第二区)上设置第二凸块结构118B。在一些实施例中，侧边区BR1包括第一侧边区BR1A及第二侧边区BR1B。举例来说，第一侧边区BR1A从中心区AR1延伸到中介层结构100’的第一外围侧SD1。相似地，第二侧边区BR1B从中心区AR1延伸到中介层结构100’的第二外围侧SD2。第二外围侧SD2与第一外围侧SD1相对。
参照图1E及图1F，第一凸块结构118A与第二凸块结构118B具有不同的高度及不同的形状。举例来说，第一凸块结构118A具有卵圆形形状(或椭圆形)，而第二凸块结构118B具有圆形形状。此外，第一凸块结构118A的最大宽度W1大于第二凸块结构118B的最大宽度W2。在一些实施例中，第一凸块结构118A的高度HT小于第二凸块结构118B的高度H1。在某些实施例中，设置在中心区AR1中的第一凸块结构118A彼此间隔开第一间距Sp1，而设置在侧边区BR1中的第二凸块结构118B彼此间隔开第二间距Sp2。位于中心区AR1中的第一凸块结构118A的间距Sp1小于位于侧边区BR1中的第二凸块结构118B的间距Sp2。换句话说，第一凸块结构118A在中介层结构100’(或内连线结构)上的布置比第二凸块结构118B在中介层结构100’(或内连线结构)上的布置更稠密。
图1G是图1E中所示封装区PKR的俯视图的替代性实施例。在图1F中所示的实施例中，侧边区BR1位于中心区AR1的两个相对侧上。然而，本公开不限于此。如图1G中所示，在一些替代性实施例中，侧边区BR1环绕中心区AR1。换句话说，设置在侧边区BR1中的第二凸块结构118B环绕且包围设置在中心区AR1中的第一凸块结构118A。
图1H及图1I是根据不同实施例的第一凸块结构118A及第二凸块结构118B的放大图。参照图1H，在一个实施例中，在金属化图案116b、116c上设置第一凸块结构118A及第二凸块结构118B，以使得第一凸块结构118A及第二凸块结构118B的底表面与重布线结构116的顶表面116s齐平或者与中介层结构100’的顶表面齐平。然而，本公开不限于此。参照图1I，在另一实施例中，第一凸块结构118A及第二凸块结构118B由重布线结构116的介电层116a局部地覆盖或环绕，或者由中介层结构100’局部地环绕。
在图1H及图1I所示实施例中，第一凸块结构118A的高度HT与第二凸块结构118B的高度H1被定义为金属柱(MP1/MP2)与形成在其上的焊料(SLD1/SLD2)的总高度。换句话说，高度HT及高度H1是从贴合到下伏的金属化图案116b、116c的金属柱(MP1/MP2)的底部朝焊料(SLD1/SLD2)的尖端测量。举例来说，第一凸块结构118A的高度HT对第二凸块结构118B的高度H1之间的比率(HT:H1)可在1:1.1到1:1.25的范围内。在某些实施例中，第一凸块结构118A及第二凸块结构118B的焊料(SLD1、SLD2)可在焊接时局部地熔化，同时金属柱(MP1/MP2)的高度维持不变。换句话说，第一凸块结构118A与第二凸块结构118B在焊接之后将仍维持其在高度HT与高度H1之间的高度差。在一些实施例中，当排除焊料(SLD1/SLD2)的高度时，第二凸块结构118B的金属柱MP2的高度大于第一凸块结构118A的金属柱MP1的高度。举例来说，在一个实施例中，第一凸块结构118A的金属柱MP1可具有为70μm到95μm的高度范围，且第二凸块结构118B的金属柱MP2可具有为85μm到110μm的高度范围，而第二凸块结构118B的金属柱MP2具有更大的高度。
参照图1J，在随后的步骤中，在金属化图案116b、116c上设置凸块结构118之后，剥离载体Cx。举例来说，剥离工艺包括将例如激光或紫外(ultra-voilet，UV)光等光投射在贴合到载体Cx(未示出)的剥离层(例如，光热转换释放层(light-to-heat-conversionrelease layer))上，以使得可容易地将载体Cx与剥离层一起移除。在一些实施例中，半导体管芯21、22的背侧表面21S、22S在剥离工艺之后显露出。
参照图1K，在剥离载体Cx之后，将图1J中所示结构贴合到由框架FR支撑的胶带TP(例如，切割胶带(dicing tape))。随后，沿切割道DL对图1J中所示结构进行切割或单体化，以形成多个半导体封装SM。举例来说，执行切割工艺以切削穿过重布线结构116、核心部分102及绝缘包封体114，以沿切割道DL移除重布线结构116、核心部分102及绝缘包封体114的部分。在一些实施例中，切割工艺或单体化工艺通常涉及利用旋转刀片或激光束进行切割。换句话说，切割或单体化工艺是例如激光切削工艺、机械锯切工艺或其他适合的工艺。在剥离载体Cx之后，可获得图1L中所示的经单体化的半导体封装SM。
图2是根据本公开一些其他示例性实施例的半导体封装的示意性剖视图。图2中所示半导体封装SM2相似于图1L中所示半导体封装SM。因此，相同参考编号可用于指代相同或类似的部件，且本文中将省略其详细说明。实施例之间的不同在于，图1L中所示中介层结构100’被图2中所示重布线层RDL(内连线结构)替换。如图2中所示，重布线层RDL设置在绝缘包封体114上，并通过电连接件110电连接到半导体管芯21、22。
在一些实施例中，重布线层RDL是通过交替地依序形成一个或多个介电层101A以及一个或多个导电层101B来形成。在某些实施例中，导电层101B夹在介电层101A之间，且电连接到及物理连接到电连接件110。在示例性实施例中，包括在重布线层RDL中的介电层101A及导电层101B的数目不限于此，且可基于设计要求来指定及选择。举例来说，介电层101A及导电层101B的数目可为一个或多于一个。
在一些实施例中，介电层101A的材料是可使用光刻和/或刻蚀工艺来图案化的聚酰亚胺、聚苯并噁唑(polybenzoxazole，PBO)、苯并环丁烯(benzocyclobutene，BCB)、氮化物(例如氮化硅)、氧化物(例如氧化硅)、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(borosilicateglass，BSG)、掺杂硼的磷硅酸盐玻璃(boron-doped phosphosilicate glass，BPSG)、其组合或类似物。在一些实施例中，介电层101A的材料是通过例如旋转涂布、化学气相沉积(CVD)、等离子体增强型化学气相沉积(PECVD)或类似工艺等适合的制作技术来形成。本公开不限于此。
在一些实施例中，导电层101B的材料由可使用光刻及刻蚀工艺来图案化的例如铝、钛、铜、镍、钨和/或其合金等通过电镀或沉积形成的导电材料制成。在一些实施例中，导电层101B可为经图案化铜层或者其他适合的经图案化金属层。在说明书通篇中，用语“铜”旨在包括实质上纯的元素铜、含有不可避免的杂质的铜以及含有少量元素(例如钽、铟、锡、锌、锰、铬、钛、锗、锶、铂、镁、铝或锆等)的铜合金。
在某些实施例中，重布线层RDL进一步包括设置在导电层101B上用于与凸块结构118电连接的多个导电焊盘101C1、101C2。举例来说，具有较大宽度的导电焊盘101C1连接到第一凸块结构118A，而具有较小宽度的导电焊盘101C2连接到第二凸块结构118B。在一些实施例中，导电焊盘101C1、101C2的材料可包括铜、镍、钛、钨或其合金或者类似物，且可通过例如电镀工艺来形成。导电焊盘101C1、101C2的数目在本公开中不受限制，且可基于设计布局来选择。在一些替代性实施例中，可省略导电焊盘101C1、101C2。换句话说，在后续步骤中形成的凸块结构118可直接设置在重布线层RDL的导电层101B上。
图3A到图3C是根据本公开一些示例性实施例的制作封装结构的方法中的各种阶段的示意性剖视图。参照图3A，在一些实施例中，通过凸块结构118(第一凸块结构118A及第二凸块结构118B)将图1L中获得的半导体封装SM安装或贴合到电路衬底300上。在一些实施例中，电路衬底300包括接触焊盘310、接触焊盘320、金属化层330及通孔(未示出)。在一些实施例中，接触焊盘310与接触焊盘320分别分布在电路衬底300的两个相对的侧上，且被暴露出以与稍后形成的元件/特征电连接。在一些实施例中，金属化层330及通孔嵌置在电路衬底300中，且一起为电路衬底300提供布线功能，其中金属化层330及通孔电连接到接触焊盘310及接触焊盘320。换句话说，接触焊盘310中的至少一些接触焊盘310通过金属化层330及通孔电连接到接触焊盘320中的一些接触焊盘320。在一些实施例中，接触焊盘310及接触焊盘320可包括金属焊盘或金属合金焊盘。在一些实施例中，金属化层330及通孔的材料可与接触焊盘310及接触焊盘320的材料实质上相同或相似。
在示例性实施例中，半导体封装SM(或中介层结构100’)具有微笑状翘曲(smilewarpage)。举例来说，在具有微笑状翘曲的情形中，半导体封装SM的中心区AR1朝电路衬底300突出，而侧边区BR1远离电路衬底300向外弯折。此外，从半导体封装SM的中心区AR1到侧边区BR1的边界测量的重布线结构116的顶表面116s处的最大高度差WP1界定重布线结构116的翘曲水平。
在一些实施例中，当半导体封装SM的高度差WP1或翘曲等于或大于45μm时，则第一凸块结构118A的最大宽度W1与第二凸块结构118B的最大宽度W2满足以下关系：W1>W2≥0.90*W1。此外，当半导体封装SM的高度差WP1或翘曲小于45μm时，则第一凸块结构118A的最大宽度W1与第二凸块结构118B的最大宽度W2满足以下关系：0.90*W1>W2≥0.8*W1。通过设计第一凸块结构118A及第二凸块结构118B的高度及宽度以满足上述关系，当将半导体封装SM结合到电路衬底300时，可补偿翘曲问题且可防止冷接头问题。总体上，可改善封装结构的可靠性。
在示例性实施例中，将第一凸块结构118A与第二凸块结构118B设计成具有不同的高度及宽度，以克服中介层结构100’在贴合到电路衬底300时的翘曲问题。应注意，此概念也可应用于电连接件110。举例来说，当半导体管芯21及22具有一定的翘曲时，也可将电连接件110设计成具有不同的高度。举例来说，在一个实施例中，第一半导体管芯21可具有包括第一电连接件及第二电连接件的电连接件110，由此第二电连接件具有较小的宽度及较大的高度。第一电连接件与第二电连接件之间的高度及宽度差可用于补偿第一半导体管芯21上任何翘曲的存在。
此外，在一些实施例中，通过对凸块结构118与接触焊盘310进行物理连接将半导体封装SM结合到电路衬底300，以形成堆叠结构。在某些实施例中，将半导体封装SM电连接到电路衬底300。在一些实施例中，电路衬底300是例如有机柔性衬底或印刷电路板。在此种实施例中，凸块结构118是例如芯片连接件。在将凸块结构118物理连接到接触焊盘310之后，第一凸块结构118A及第二凸块结构118B的焊料(SLD1/SLD2)可在焊接时局部地熔化，同时金属柱(MP1/MP2)的高度维持不变。然而，第一凸块结构118A与第二凸块结构118B之间的高度差在贴合之后仍然保持在1:1.1到1:1.25的比率范围内。在一些替代性实施例中，电路衬底300可包括位于接触焊盘310上的可选连接凸块(未示出)。在此种实施例中，凸块结构118物理贴合到连接凸块，以电连接到电路衬底300。
在一些实施例中，在衬底300上分别形成多个导电球340。如图3A中所示，举例来说，将导电球340连接到电路衬底300的接触焊盘320。换句话说，通过接触焊盘320将导电球340电连接到电路衬底300。通过接触焊盘310及接触焊盘320，导电球340中的一些导电球340电连接到半导体封装SM(例如，其中所包括的半导体管芯21及22)。在一些实施例中，导电球340是例如焊球或BGA球。在一些实施例中，通过透过衬底上晶片上芯片(chip onwafer on substrate，CoWoS)封装工艺对凸块结构118与电路衬底300的接触焊盘310进行物理连接来将半导体封装SM结合到电路衬底300。另外，如图3A中所示，可在电路衬底300上安装无源器件PDX(集成无源器件或表面安装器件)。举例来说，可通过焊接工艺在电路衬底300的接触焊盘310上安装无源器件PDX。本公开不限于此。在某些实施例中，可在环绕半导体封装SM的电路衬底上安装无源器件PDX。在一些替代性实施例中，省略了无源器件PDX。
参照图3B，在随后的步骤中，形成底部填充结构350以填充满电路衬底300与半导体封装SM之间的空间。在某些实施例中，底部填充结构350填充满相邻凸块结构118之间的空间并覆盖凸块结构118。举例来说，底部填充结构350环绕凸块结构118。在一些实施例中，覆盖中介层结构100’的中心区AR1的底部填充结构350具有第一平均高度Y1，而覆盖侧边区BR1(BR1A、BR1B)的底部填充结构350具有第二平均高度Y2。在某些实施例中，第一平均高度Y1可对应于贴合之后第一凸块结构118A(包括柱及焊料)的高度，而第二平均高度Y2可对应于贴合之后第二凸块结构118B(包括柱及焊料)的高度。在一些其他实施例中，当可选的连接凸块用于连接时，底部填充结构350可进一步覆盖可选的连接凸块。因此，在此种实施例中，第一平均高度Y1可对应于贴合之后第一凸块结构118A及可选连接凸块的高度，而第二平均高度Y2可对应于贴合之后第二凸块结构118B及可选的连接凸块的高度。
此外，覆盖半导体封装SM的侧壁的底部填充结构350具有最大高度Y3。在示例性实施例中，第一平均高度Y1小于第二平均高度Y2，且第二平均高度Y2小于最大高度Y3。在一些实施例中，第一平均高度Y1对第二平均高度Y2的比率在1:1.1到1:1.25的范围内。在一些实施例中，无源器件PDX由底部填充结构350暴露出，且与底部填充结构350保持一定距离。换句话说，底部填充结构350不覆盖无源器件PDX。
参照图3C，在随后的步骤中，通过粘合剂Ax将环结构510贴合到电路衬底300。在一些实施例中，举例来说，环结构510是由金属材料制成的加强环。在某些实施例中，环结构510设置在电路衬底300上以环绕半导体封装SM。在将环结构510贴合到电路衬底300上之后，可实现根据本公开一些实施例的封装结构PKG1。
图4A及图4B是根据本公开一些其他实施例的半导体封装的示意性剖视图及俯视图。图4A及图4B中所示半导体封装SM3相似于图1L中所示半导体封装SM。因此，相同的参考编号用于指代相同或类似的部件，且本文中将省略其详细说明。
参照图4A，且从图4B中所示半导体封装SM3的俯视图来看，侧边区BR1包括第一侧边区BR1A及第二侧边区BR1B。在一些实施例中，第一侧边区BR1A包括第一子区BR1A-1、第二子区BR1A-2及第三子区BR1A-3。第一子区BR1A-1与中心区AR1联结，第三子区BR1A-3位于半导体封装SM3的第一外围侧SD1处，且第二子区BR1A-2位于第一子区BR1A-1与第三子区BR1A-3之间。此外，第二侧边区BR1B包括第四子区BR1B-4、第五子区BR1B-5及第六子区BR1B-6。第四子区BR1B-4与中心区AR1联结，第六子区BR1B-6位于半导体封装SM3的与第一外围侧SD1相对的第二外围侧SD2处，且第五子区BR1B-5位于第四子区BR1B-4与第六子区BR1B-6之间。
在示例性实施例中，第二凸块结构118B进一步包括第一部分凸块118B-1、第二部分凸块118B-2及第三部分凸块118B-3。第一部分凸块118B-1位于第一子区BR1A-1及第四子区BR1B-4中且具有为H1的高度。第二部分凸块118B-2位于第二子区BR1A-2及第五子区BR1B-5中且具有为H2的高度。第三部分凸块118B-3位于第三子区BR1A-3及第六子区BR1B-6中且具有为H3的高度，其中H1<H2<H3。在一些实施例中，第一凸块结构118A设置在金属化图案116b上。此外，第一部分凸块118B-1设置在金属化图案116c-1上，第二部分凸块118B-2设置在金属化图案116c-2上，而第三部分凸块118B-3设置在金属化图案116c-3上。
如图4B中进一步所示，第一凸块结构118A具有卵圆形形状(或椭圆形)，而第二凸块结构118B具有圆形形状。然而，如图4B中所示，第二凸块结构118B的第一部分凸块118B-1、第二部分凸块118B-2及第三部分凸块118B-3具有不同的大小或宽度。举例来说，第一部分凸块118B-1具有为W2A的宽度，第二部分凸块118B-2具有为W2B的宽度，且第三部分凸块118B-3具有为W2C的宽度，其中W2C<W2B<W2A。另外，第二凸块结构118B的宽度W2A～W2C小于第一凸块结构118A的最大宽度W1。在一些实施例中，第一部分凸块118B-1以为Sp2A的间距布置在第一子区BR1A-1及第四子区BR1B-4中。第二部分凸块118B-2以为Sp2B的间距布置在第二子区BR1A-2及第五子区BR1B-5中。第三部分凸块118B-3以为Sp2C的间距布置在第三子区BR1A-3及第六子区BR1B-6中，其中Sp2C>Sp2B>Sp2A。此外，侧边区BR1中的第二凸块结构118B的间距Sp2A～Sp2C大于中心区AR1中的第一凸块结构118A的第一间距Sp1。
在示例性实施例中，图4A及图4B中所示半导体封装SM3可以与图3A到图3C中所示方式相似的方式安装或贴合到电路衬底300上。在半导体封装SM3具有微笑状翘曲的情形中，由于凸块结构118被布置成从中心区AR1到侧边区BR1具有增加的高度及减小的宽度，因此翘曲问题可被补偿且冷接头问题可被防止。总体上，可改善封装结构的可靠性。
图5A及图5B是根据本公开一些其他实施例的半导体封装的示意性剖视图及俯视图。图5A及图5B中所示半导体封装SM4相似于图4A及图4B中所示半导体封装SM3。因此，相同的参考编号用于指代相同或类似的部件，且本文中将省略其详细说明。实施例之间的不同在于第一部分凸块118B-1、第二部分凸块118B-2及第三部分凸块118B-3在不同区中的布置。
参照图5A，且从图5B中所示半导体封装SM4的俯视图来看，中介层结构100’的侧边区BR1包括第一侧边区BR1A、第二侧边区BR1B及第三侧边区BR1C。第一侧边区BR1A与中心区AR1联结且包围中心区AR1。第二侧边区BR1B与第一侧边区BR1A联结且包围第一侧边区BR1A。第三侧边区BR1C包围第二侧边区BR1B且位于半导体封装SM4的外围侧处。在一些实施例中，第一部分凸块118B-1位于第一侧边区BR1A中且具有为H1的高度。第二部分凸块118B-2位于第二侧边区BR1B中且具有为H2的高度。此外，第三部分凸块118B-3位于第三侧边区中且具有为H3的高度，其中H1<H2<H3。
在示例性实施例中，图5A及图5B中所示半导体封装SM4可以与图3A到图3C中所示方式相似的方式安装或贴合到电路衬底300上。在半导体封装SM4具有微笑状翘曲的情形中，由于凸块结构118(118A、118B)被布置成从中心区AR1到侧边区BR1(BR1A、BR1B及BR1C)具有增加的高度及减小的宽度，因此翘曲问题可被补偿且冷接头问题可被防止。总体上，可改善封装结构的可靠性。
图6A及图6B是根据本公开一些其他实施例的半导体封装的示意性剖视图及俯视图。图6A及图6B中所示半导体封装SM5相似于图1L中所示半导体封装SM。因此，相同的参考编号用于指代相同或类似的部件，且本文中将省略其详细说明。实施例之间的不同在于凸块结构118的设计。
如图6A中所示，且从图6B中所示半导体封装SM5的俯视图来看，第一凸块结构118A设置在中介层结构100’的中心区AR1上，而第二凸块结构118B设置在中介层结构100’的侧边区BR1上。在一些实施例中，侧边区BR1包括第一侧边区BR1A及第二侧边区BR1B。参照图6A及图6B，第一凸块结构118A具有圆形形状，而第二凸块结构118B具有卵圆形形状(或椭圆形)。此外，第一凸块结构118A的最大宽度W1小于第二凸块结构118B的最大宽度W2。在一些实施例中，第一凸块结构118A的高度HT大于第二凸块结构118B的高度H1。在某些实施例中，设置在中心区AR1中的第一凸块结构118A彼此间隔开第一间距Sp1，而设置在侧边区BR1中的第二凸块结构118B彼此间隔开第二间距Sp2。位于中心区AR1中的第一凸块结构118A的间距Sp1大于位于侧边区BR1中的第二凸块结构118B的间距Sp2。换句话说，第一凸块结构118A在中介层结构100’(或内连线结构)上的布置比第二凸块结构118B在中介层结构100’(或内连线结构)上的布置更不稠密。
图7A到图7C是根据本公开一些其他示例性实施例的制作封装结构的方法中的各种阶段的示意性剖视图。图7A到图7C中所示封装结构PKG2相似于图3A到图3C中所示封装结构PKG1。因此，相同的参考编号用于指代相同或类似的部件，且本文中省略其详细说明。
参照图7A，在一些实施例中，通过凸块结构118(第一凸块结构118A及第二凸块结构118B)将图6A中所示半导体封装SM5安装或贴合到电路衬底300上。在示例性实施例中，半导体封装SM(或中介层结构100’)具有哭泣状翘曲(cry warpage)。举例来说，在具有哭泣状翘曲的情形中，半导体封装SM的中心区AR1远离电路衬底300向内弯折，而侧边区BR1朝电路衬底300突出。此外，在半导体封装SM5的中心区AR1与侧边区BR1之间重布线结构116的顶表面116s处的高度差WP2界定半导体封装SM5的翘曲水平。
在一些实施例中，当半导体封装SM5的高度差WP1或翘曲等于或大于45μm时，则第一凸块结构118A的最大宽度W1与第二凸块结构118B的最大宽度W2满足以下关系：W2>W1≥0.90*W2。此外，当半导体封装SM5的高度差WP1或翘曲小于45μm时，则第一凸块结构118A的最大宽度W1与第二凸块结构118B的最大宽度W2满足以下关系：0.90*W2>W1≥0.8*W2。通过设计第一凸块结构118A与第二凸块结构118B的高度及宽度以满足以上关系，可适当地解决半导体封装SM5的翘曲问题。
参照图7B，在随后的步骤中，形成底部填充结构350以填充满电路衬底300与半导体封装SM5之间的空间。在某些实施例中，底部填充结构350填充满相邻的凸块结构118之间的空间且覆盖凸块结构118。举例来说，底部填充结构350环绕凸块结构118。在一些实施例中，覆盖中介层结构100’的中心区AR1的底部填充结构350具有第一平均高度Y1，而覆盖侧边区BR1(BR1A、BR1B)的底部填充结构350具有第二平均高度Y2。此外，覆盖半导体封装SM的侧壁的底部填充结构350具有最大高度Y3。在示例性实施例中，第一平均高度Y1大于第二平均高度Y2，且最大高度Y3大于第一平均高度Y1与第二平均高度Y2二者。在一些实施例中，无源器件PDX通过底部填充结构350暴露出，且与底部填充结构350保持间隔开一定距离。换句话说，底部填充结构350不覆盖无源器件PDX。
参照图7C，在随后的步骤中，通过粘合剂Ax将环结构510贴合到电路衬底300。在将环结构510贴合到电路衬底300上之后，可实现根据本公开一些实施例的封装结构PKG2。在图7C中所示封装结构PKG2中，半导体封装SM5具有哭泣状翘曲。由于凸块结构118(118A、118B)被布置成从中心区AR1到侧边区BR1(BR1A、BR1B)具有减小的高度及增加的宽度，因此翘曲问题可被补偿且冷接头问题可被防止。总体上，可改善封装结构PKG2的可靠性。
图8是根据本公开一些其他示例性实施例的封装结构的示意性剖视图。图8中所示封装结构PKG3相似于图3C中所示封装结构PKG1。因此，相同的参考编号用于指代相同或类似的部件，且本文中将省略其详细说明。实施例之间的不同在于，图2中的半导体封装SM2用于替换图1L中的半导体封装SM。半导体封装SM2的细节可参照图2的说明，因此本文中将不再予以赘述。
如图8中所示，在一些实施例中，在图1L中获得的半导体封装SM2通过凸块结构118(第一凸块结构118A及第二凸块结构118B)安装或贴合到电路衬底300上。随后，形成底部填充结构350以填充满电路衬底300与半导体封装SM2之间的空间，且环结构510通过粘合剂Ax贴合到电路衬底300。通过相似的方式，假使半导体封装SM2具有微笑状翘曲，由于凸块结构118(118A、118B)被布置成从中心区AR1到侧边区BR1(BR1A、BR1B)具有增加的高度及减小的宽度，因此翘曲问题可被补偿且冷接头问题可被防止。总体上，可改善封装结构PKG3的可靠性。
在上述实施例中，封装结构的半导体封装被设计成至少包括具有不同的高度及不同的形状的第一凸块结构与第二凸块结构。举例来说，当半导体封装具有微笑状翘曲时，凸块结构被布置成从中心区到侧边区具有减小的高度及增加的宽度。另一方面，当半导体封装具有哭泣状翘曲时，凸块结构被布置成从中心区到侧边区具有增加的高度及减小的宽度。因此，翘曲问题(哭泣状翘曲或微笑状翘曲)可被补偿且冷接头问题可被防止。总体上，可改善封装结构的可靠性。
根据本公开的一些实施例，一种封装结构包括电路衬底、半导体封装、第一凸块结构以及第二凸块结构。所述半导体封装设置在所述电路衬底上，其中所述半导体封装包括中心区及环绕所述中心区的侧边区。所述第一凸块结构设置在所述半导体封装的所述中心区上，且将所述半导体封装电连接到所述电路衬底。所述第二凸块结构设置在所述半导体封装的所述侧边区上，且将所述半导体封装电连接到所述电路衬底，其中所述第一凸块结构与所述第二凸块结构具有不同的高度及不同的形状。
在一些实施例中，所述半导体封装的翘曲等于或大于45μm，且所述第一凸块结构的所述最大宽度W1与所述第二凸块结构的所述最大宽度W2满足以下关系：W1>W2≥0.90*W1。在一些实施例中，所述半导体封装的翘曲小于45μm，且所述第一凸块结构的所述最大宽度W1与所述第二凸块结构的所述最大宽度W2满足以下关系：0.90*W1>W2≥0.8*W1。在一些实施例中，所述侧边区包括：第一侧边区，与所述中心区联结且包围所述中心区；第二侧边区，与所述第一侧边区联结且包围所述第一侧边区；以及第三侧边区，包围所述第二侧边区且位于所述半导体封装的外围侧处；并且其中所述第二凸块结构包括：第一部分凸块，位于所述第一侧边区中且具有为H1的高度；第二部分凸块，位于所述第二侧边区中且具有为H2的高度；以及第三部分凸块，位于所述第三侧边区中且具有为H3的高度，其中H1<H2<H3。在一些实施例中，所述第一凸块结构及所述第二凸块结构分别包括金属柱及设置在所述金属柱上的焊料，且所述第一凸块结构的所述高度与所述第二凸块结构的所述高度被定义为所述金属柱与所述焊料的总高度。
根据本公开的一些其他实施例，一种封装结构包括电路衬底、中介层结构、多个凸块结构、多个半导体管芯以及绝缘包封体。所述中介层结构设置在所述电路衬底上且电连接到所述电路衬底。所述多个凸块结构设置在所述电路衬底与所述中介层结构之间，且将所述中介层结构电连接到所述电路衬底，其中设置在所述中介层结构的第一区上的所述多个凸块结构彼此间隔开第一间距，且设置在所述中介层结构的第二区上的所述多个凸块结构彼此间隔开第二间距，其中所述第二间距不同于所述第一间距，且其中设置在所述第一区及所述第二区上的所述多个凸块结构具有不同的大小。所述半导体管芯设置在所述中介层结构的背侧表面上且电连接到所述中介层结构。所述绝缘包封体设置在所述中介层结构的所述背侧表面上，且环绕所述多个半导体管芯。
在一些实施例中，设置在所述第一区上的所述多个凸块结构的最大宽度W1大于设置在所述第二区上的所述多个凸块结构的最大宽度W2。在一些实施例中，设置在所述第一区上的所述多个凸块结构具有卵圆形形状，且设置在所述第二区上的所述多个凸块结构具有圆形形状。在一些实施例中，设置在所述第一区上的所述多个凸块结构的最大宽度W1小于设置在所述第二区上的所述多个凸块结构的最大宽度W2。
根据本公开的又一实施例，一种封装结构包括电路衬底、内连线结构、第一凸块结构、第二凸块结构以及底部填充结构。所述内连线结构设置在所述电路衬底上且电连接到所述电路衬底。所述第一凸块结构设置在所述电路衬底与所述内连线结构之间。所述第二凸块结构设置在所述电路衬底与所述内连线结构之间，其中所述第二凸块结构具有比所述第一凸块结构大的高度，且所述第一凸块结构在所述内连线结构上的布置比所述第二凸块结构在所述内连线结构上的布置更稠密。所述底部填充结构覆盖所述第一凸块结构及所述第二凸块结构。
在一些实施例中，所述第一凸块结构设置在所述内连线结构的中心区上，且所述第二凸块结构设置在所述内连线结构的除所述中心区以外的侧边区上。在一些实施例中，覆盖所述中心区的所述底部填充结构具有第一平均高度Y1，且覆盖所述侧边区的所述底部填充结构具有第二平均高度Y2，其中所述第二平均高度Y2大于所述第一平均高度Y1。在一些实施例中，所述第一凸块结构具有卵圆形形状，且所述第二凸块结构具有圆形形状。
还可包括其他特征及工艺。举例来说，可包括测试结构来帮助对三维(threedimensional，3D)封装或三维集成电路(3D integrated circuit，3DIC)器件进行验证测试。测试结构可包括例如形成在重布线层中或形成在衬底上的测试焊盘，所述测试焊盘使得能够测试3D封装或3DIC、能够使用探针和/或探针卡以及进行类似操作。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可与包括对已知良好管芯进行中间验证的测试方法结合使用来提高良率(yield)及降低成本。
前述内容概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本公开的各方面。所属领域中的技术人员应理解，他们可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应意识到，此种等效构造并不背离本公开的精神及范围，且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、取代及变更。

Claims (10)

1.一种封装结构，包括：
电路衬底；
半导体封装，设置在所述电路衬底上，其中所述半导体封装包括中心区及环绕所述中心区的侧边区；
第一凸块结构，设置在所述半导体封装的所述中心区上，且将所述半导体封装电连接到所述电路衬底；以及
第二凸块结构，设置在所述半导体封装的所述侧边区上，且将所述半导体封装电连接到所述电路衬底，其中所述第一凸块结构与所述第二凸块结构具有不同的高度及不同的形状。
2.根据权利要求1所述的封装结构，其中所述第一凸块结构具有卵圆形形状，而所述第二凸块结构具有圆形形状，且所述第一凸块结构的最大宽度W1大于所述第二凸块结构的最大宽度W2。
3.根据权利要求2所述的封装结构，其中所述第一凸块结构的高度小于所述第二凸块结构的高度。
4.根据权利要求1所述的封装结构，其中所述侧边区包括：
第一侧边区，包括第一子区、第二子区及第三子区，所述第一子区与所述中心区联结，所述第三子区位于所述半导体封装的第一外围侧处，且所述第二子区位于所述第一子区与所述第三子区之间；
第二侧边区，包括第四子区、第五子区及第六子区，所述第四子区与所述中心区联结，所述第六子区位于所述半导体封装的与所述第一外围侧相对的第二外围侧处，且所述第五子区位于所述第四子区与所述第六子区之间；并且
其中所述第二凸块结构包括：
第一部分凸块，位于所述第一子区及所述第四子区中且具有为H1的高度；
第二部分凸块，位于所述第二子区及所述第五子区中且具有为H2的高度；以及
第三部分凸块，位于所述第三子区及所述第六子区中且具有为H3的高度，其中H1<H2<H3。
5.根据权利要求1所述的封装结构，其中所述第一凸块结构具有圆形形状，而所述第二凸块结构具有卵圆形形状，且所述第一凸块结构的最大宽度小于所述第二凸块结构的最大宽度。
6.一种封装结构，包括：
电路衬底；
中介层结构，设置在所述电路衬底上且电连接到所述电路衬底；
多个凸块结构，设置在所述电路衬底与所述中介层结构之间，且将所述中介层结构电连接到所述电路衬底，其中设置在所述中介层结构的第一区上的所述多个凸块结构彼此间隔开第一间距，且设置在所述中介层结构的第二区上的所述多个凸块结构彼此间隔开第二间距，其中所述第二间距不同于所述第一间距，且其中设置在所述第一区及所述第二区上的所述多个凸块结构具有不同的大小；
多个半导体管芯，设置在所述中介层结构的背侧表面上，且电连接到所述中介层结构；以及
绝缘包封体，设置在所述中介层结构的所述背侧表面上，且环绕所述多个半导体管芯。
7.根据权利要求6所述的封装结构，其中所述中介层结构具有微笑状翘曲，且设置在所述第一区上的所述多个凸块结构具有比设置在所述第二区上的所述多个凸块结构小的高度，且所述第一间距小于所述第二间距。
8.根据权利要求6所述的封装结构，其中所述中介层结构具有哭泣状翘曲，且设置在所述第一区上的所述多个凸块结构具有比设置在所述第二区上的所述多个凸块结构大的高度，且所述第一间距大于所述第二间距。
9.一种封装结构，包括：
电路衬底；
内连线结构，设置在所述电路衬底上且电连接到所述电路衬底；
第一凸块结构，设置在所述电路衬底与所述内连线结构之间；
第二凸块结构，设置在所述电路衬底与所述内连线结构之间，其中所述第二凸块结构具有比所述第一凸块结构大的高度，且所述第一凸块结构在所述内连线结构上的布置比所述第二凸块结构在所述内连线结构上的布置更稠密；以及
底部填充结构，覆盖所述第一凸块结构及所述第二凸块结构。
10.根据权利要求9所述的封装结构，其中所述内连线结构的翘曲小于45μm，且所述第一凸块结构的最大宽度W1与所述第二凸块结构的最大宽度W2满足以下关系：0.95*W1>W2≥0.9*W1。
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