BR112014005202A2 - método de alívio de soldagem e dispositivo semicondutor que emprega o mesmo - Google Patents

método de alívio de soldagem e dispositivo semicondutor que emprega o mesmo

Info

Publication number
BR112014005202A2
BR112014005202A2 BR112014005202A BR112014005202A BR112014005202A2 BR 112014005202 A2 BR112014005202 A2 BR 112014005202A2 BR 112014005202 A BR112014005202 A BR 112014005202A BR 112014005202 A BR112014005202 A BR 112014005202A BR 112014005202 A2 BR112014005202 A2 BR 112014005202A2
Authority
BR
Brazil
Prior art keywords
semiconductor device
substrate
same
foreground
locations
Prior art date
Application number
BR112014005202A
Other languages
English (en)
Inventor
Xu Jianwen
Wendell Schwarz Mark
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of BR112014005202A2 publication Critical patent/BR112014005202A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

resumo “método de alívio de soldagem e dispositivo semicondutor que emprega o mesmo” um dispositivo semicondutor inclui um substrato tendo um primeiro lado e um segundo lado, o segundo lado tendo um local de montagem para pelo menos um elemento semicondutor, e o primeiro lado tendo uma pluralidade de locais eletricamente conectados aos locais no segundo lado. uma pluralidade de interconexões eletricamente condutoras são fornecidas nos locais, cada uma tendo uma primeira extremidade anexa no local e uma segunda extremidade espaçada do substrato, e um encapsulante parcialmente encapsula uma pluralidade de interconexões e tem uma superfície que se encontra em um primeiro plano. as segundas extremidades estão localizadas no lado do primeiro plano oposto a partir do primeiro lado do substrato, um espaço anular no encapsulante cerca cada de uma pluralidade de interconexões eletricamente condutoras, e o espaço anular tem um fundo localizado entre o primeiro plano e o primeiro lado do substrato. também um método para fazer tal dispositivo semiconductor. 1/1
BR112014005202A 2011-09-09 2012-09-10 método de alívio de soldagem e dispositivo semicondutor que emprega o mesmo BR112014005202A2 (pt)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/228,925 US8461676B2 (en) 2011-09-09 2011-09-09 Soldering relief method and semiconductor device employing same
PCT/US2012/054491 WO2013036948A1 (en) 2011-09-09 2012-09-10 Soldering relief method and semiconductor device employing same

Publications (1)

Publication Number Publication Date
BR112014005202A2 true BR112014005202A2 (pt) 2017-03-21

Family

ID=46981087

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112014005202A BR112014005202A2 (pt) 2011-09-09 2012-09-10 método de alívio de soldagem e dispositivo semicondutor que emprega o mesmo

Country Status (7)

Country Link
US (2) US8461676B2 (pt)
EP (1) EP2754169B1 (pt)
JP (1) JP5905104B2 (pt)
KR (1) KR101610349B1 (pt)
CN (1) CN103782377B (pt)
BR (1) BR112014005202A2 (pt)
WO (1) WO2013036948A1 (pt)

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US8461676B2 (en) 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
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TWI800591B (zh) * 2018-01-15 2023-05-01 美商艾馬克科技公司 半導體封裝以及其製造方法
US10861779B2 (en) 2018-06-22 2020-12-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package having an electrical contact with a high-melting-point part and method of manufacturing the same
US10950529B2 (en) 2018-08-30 2021-03-16 Advanced Semiconductor Engineering Korea, Inc. Semiconductor device package

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Also Published As

Publication number Publication date
US8461676B2 (en) 2013-06-11
JP2014528166A (ja) 2014-10-23
US20130062746A1 (en) 2013-03-14
KR101610349B1 (ko) 2016-04-08
EP2754169B1 (en) 2019-11-27
WO2013036948A1 (en) 2013-03-14
US20130244384A1 (en) 2013-09-19
CN103782377A (zh) 2014-05-07
CN103782377B (zh) 2017-05-03
KR20140059297A (ko) 2014-05-15
US8841168B2 (en) 2014-09-23
EP2754169A1 (en) 2014-07-16
JP5905104B2 (ja) 2016-04-20

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B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B08F Application dismissed because of non-payment of annual fees [chapter 8.6 patent gazette]

Free format text: REFERENTE A 7A ANUIDADE.

B08K Patent lapsed as no evidence of payment of the annual fee has been furnished to inpi [chapter 8.11 patent gazette]

Free format text: EM VIRTUDE DO ARQUIVAMENTO PUBLICADO NA RPI 2531 DE 09-07-2019 E CONSIDERANDO AUSENCIA DE MANIFESTACAO DENTRO DOS PRAZOS LEGAIS, INFORMO QUE CABE SER MANTIDO O ARQUIVAMENTO DO PEDIDO DE PATENTE, CONFORME O DISPOSTO NO ARTIGO 12, DA RESOLUCAO 113/2013.